Abstract: Provided may be a gate pattern, flash memory and methods of manufacturing and operating the same. A gate pattern may include a floating gate on a tunneling dielectric layer, an inter-gate dielectric layer on the floating gate, a first control gate on the inter-gate dielectric layer, and a second control gate on the inter-gate dielectric layer and spaced apart from the first control gate. Each of the control gates sets four states according to an application time of a program voltage applied to the control gates. Thus, one control gate may program 2-bit data.

Abstract: The present disclosure provides a memory device having a cell stack and a select gate formed adjacent to the cell stack. The cell stack includes a tunneling dielectric layer, a charge storage layer, a blocking dielectric layer, a tantalum-nitride layer, and a control gate layer. When a positive bias is applied to the control gate and the select gate, negative charges are injected from a channel region of a substrate through the tunneling dielectric layer and into the charge storage layer to thereby store the negative charges in the charge storage layer. When a negative bias is applied to the control gate, negative charges are tunneled from the charge storage layer to the channel region of the substrate through the tunneling dielectric layer.

Abstract: A nonvolatile semiconductor device includes a pair of multi-bit nonvolatile memory unit cells. Each unit cell includes a grid type semiconductor body in which a plurality of parallel semiconductor bodies extend in a first direction and a plurality of parallel semiconductor bodies extend in a second direction perpendicular to the first direction, a channel region formed in a partial region of the semiconductor body along circumferences of the semiconductor bodies that extend in the first direction, a charge storage region formed on the channel region, a plurality of control gates, which are formed on the charge storage region and wherein each of the plurality of control gates is adapted to receive separate control voltages. Each unit cell further includes source and drain regions aligned on both sides of the plurality of control gates and formed in the semiconductor bodies, wherein the pair of unit cells share the source region, and the source region is formed at a cross point of the grid.

Abstract: A non-volatile memory device may include at least one semiconductor layer, a plurality of control gate electrodes, a plurality of charge storage layers, at least one first auxiliary electrode, and/or at least one second auxiliary electrode. The plurality of control gate electrodes may be recessed into the semiconductor layer. The plurality of charge storage layers may be between the plurality of control gate electrodes and the semiconductor layer. The first and second auxiliary electrodes may be arranged to face each other. The plurality of control gate electrodes may be between the first and second auxiliary electrodes and capacitively coupled with the semiconductor layer.

Abstract: The present invention provides a manufacturing method for an integrated circuit and a corresponding integrated circuit. The integrated circuit comprises a plurality of first devices, each first device including a charge storage layer and a control electrode comprising a plurality of layers; and a plurality of second devices coupled to at least one of the plurality of first devices, each second device including a control electrode comprising at least one layer different from said plurality of layers.

Abstract: A SONOS memory cell, formed within a semiconductor substrate, includes a bottom dielectric disposed on the semiconductor substrate, a charge trapping material disposed on the bottom dielectric, and a top dielectric disposed on the charge trapping material. Furthermore, the SONOS memory cell includes a word-line gate structure disposed on the top dielectric and at least one bit-line gate for inducing at least one inversion bit-line within the semiconductor substrate.

Abstract: A nonvolatile semiconductor memory device includes a semiconductor substrate. Active regions are formed on the surface of the substrate, separated from one another by element separating regions and extend in a first direction. A first word line and a second word line extend in a second direction crossing the first direction. A pair of first select gate lines extend in the second direction between the first and second word lines. Memory cell transistors are each provided at each of intersections of the first and second word lines and the active regions on the surface of the substrate. First select gate transistors are each provided at each of intersections of the pair of first select gate lines and the active regions on the surface of the substrate. A first contact is provided between the pair of first select gate lines and contacts adjacent two of the active regions.

Abstract: A nonvolatile semiconductor memory which is configured to include a plurality of word lines disposed in a row direction; a plurality of bit lines disposed in a column direction perpendicular to the word lines; memory cell transistors having a charge storage layer, provided in the column direction and an electronic storage condition of the memory cell transistor configured to be controlled by one of the plurality of the word lines connected to the memory cell; a plurality of first select transistors, each including a gate electrode, selecting the memory cell transistors provided in the column direction, arranged in the column direction and adjacent to the memory cell transistors at a first end of the memory cell transistors; and a first select gate line connected to each of the gate electrodes of the first select transistors.

Abstract: In a non-volatile memory device and methods of forming and operating the same, one memory transistor includes sidewall selection gates covering both sidewalls of a floating gate when the floating gate and a control gate are stacked. The sidewall selection gates are in a spacer form. Since the sidewall selection gates are in a spacer form on the sidewall of the floating gate, the degree of integration of cells can be improved. Additionally, since the side wall selection gates are disposed on both sidewalls of the floating gate, a voltage applied from a bit line and a common source line can be controlled and thus conventional writing/erasing errors can be prevented. Therefore, distribution of threshold voltage can be improved.

Abstract: A non-volatile memory device includes a floating gate formed on a substrate with a gate insulation layer interposed therebetween, a tunnel insulation layer formed on the floating gate, a select gate electrode inducing charge introduction through the gate insulation layer, and a control gate electrode inducing charge tunneling occurring through the tunnel insulation layer. The select gate electrode is insulated from the control gate electrode. According to the non-volatile memory device, a select gate electrode and a control gate electrode are formed on a floating gate, and thus a voltage is applied to the respective gate electrodes to write and erase data.

Abstract: Provided are non-volatile split-gate memory cells having self-aligned floating gate and the control gate structures and exemplary processes for manufacturing such memory cells that provide improved dimensional control over the relative lengths and separation of the split-gate elements. Each control gate includes a projecting portion that extends over at least a portion of the associated floating gate with the size of the projecting portion being determined by a first sacrificial polysilicon spacer that, when removed, produces a concave region in an intermediate insulating structure. The control gate is then formed as a polysilicon spacer adjacent the intermediate insulating structure, the portion of the spacer extending into the concave region determining the dimension and spacing of the projecting portion and the thickness of the interpoly oxide (IPO) separating the upper portions of the split-gate electrodes thereby providing improved performance and manufacturability.

Abstract: Several embodiments of flash EEPROM split-channel cell arrays are described that position the channels of cell select transistors along sidewalls of trenches in the substrate, thereby reducing the cell area. Select transistor gates are formed as part of the word lines and extend downward into the trenches with capacitive coupling between the trench sidewall channel portion and the select gate. In one embodiment, trenches are formed between every other floating gate along a row, the two trench sidewalls providing the select transistor channels for adjacent cells, and a common source/drain diffusion is positioned at the bottom of the trench. A third gate provides either erase or steering capabilities. In another embodiment, trenches are formed between every floating gate along a row, a source/drain diffusion extending along the bottom of the trench and upwards along one side with the opposite side of the trench being the select transistor channel for a cell.

Abstract: An integrated memory device, an integrated memory chip and a method for fabricating an integrated memory device is disclosed. One embodiment provides at least one integrated memory device with a drain, a source, a floating gate, a selection gate and a control gate, wherein the conductivity between the drain and the source can be controlled independently via the control gate.

Abstract: Disclosure is semiconductor device of a selective gate region, comprising a semiconductor layer, a first insulating film formed on the semiconductor layer, a first electrode layer formed on the first insulating layer, an element isolating region comprising an element isolating insulating film formed to extend through the first electrode layer and the first insulating film to reach an inner region of the semiconductor layer, the element isolating region isolating a element region and being self-aligned with the first electrode layer, a second insulating film formed on the first electrode layer and the element isolating region, an open portion exposing a surface of the first electrode layer being formed in the second insulating film, and a second electrode layer formed on the second insulating film and the exposed surface of the first electrode layer, the second electrode layer being electronically connected to the first electrode layer via the open portion.

Abstract: The present memory device includes first and second electrodes, a passive layer between the first and second electrodes; and an active layer between the first and second electrodes, the active layer being of dendrimeric material which provides passages through the active layer.

Abstract: Novel memory cells utilize source-side injection, allowing very small programming currents. If desired, to-be-programmed cells are programmed simultaneously while not requiring an unacceptably large programming current for any given programming operation. In one embodiment, memory arrays are organized in sectors with each sector being formed of a single column or a group of columns having their control gates connected in common. In one embodiment, a high speed shift register is used in place of a row decoder to serially shift in data for the word lines, with all data for each word line of a sector being contained in the shift register on completion of its serial loading. In one embodiment, speed is improved by utilizing a parallel loaded buffer register which receives parallel data from the high speed shift register and holds that data during the write operation, allowing the shift register to receive serial loaded data during the write operation for use in a subsequent write operation.

Abstract: A multi-function memory array that includes a DRAM distributed in several DRAM sectors, a Flash EEPROM distributed in several Flash EEPROM sectors, a data bus interconnecting the DRAM sectors and the Flash EEPROM sectors, and a plurality of memory access control circuitries. Each DRAM sector and Flash EEPROM sector can be accessed independently and data can be transferred between a DRAM sector and a Flash EEPROM sector. External data can also be written into either DRAM or Flash EEPROM. Flash EEPROM in one sector is distributed in rows and columns, and cells in each column are separated from the cells in an adjacent column by deep trench isolation regions.

Abstract: A nonvolatile memory device includes first and second impurity diffusion regions formed in a semiconductor substrate, and a memory cell formed on a channel region of a semiconductor substrate between the first and second impurity diffusion regions. The memory cell includes a stacked gate structure formed on the channel region, and first and second select gates formed on the channel regions and opposite sidewalls of the stacked gate structure. Since the first and second select gates are spacer-shaped to be self-aligned on opposite sidewalls of the stacked gate structure, a size of a memory cell is reduced to enhance an integration density of a semiconductor device.

Abstract: Disclosed is a semiconductor device and method of fabricating the same. The device is disposed on a substrate, including a fin constructed with first and second sidewalls, a first gate line formed in the pattern of spacer on the first sidewall of the fin, and a second gate line formed in the pattern of spacer on the second sidewall of the fin. First and second impurity regions are disposed in the fin. The first and second impurity regions are isolated from each other and define a channel region in the fin between the first and second gate lines.

Abstract: An element isolating region for separating an element region of a semiconductor layer is formed in a peripheral circuit section of a semiconductor memory device, and a first conductive layer is formed with the element region with a first insulating film interposed therebetween. A second conductive layer is formed on the first conductive layer to extend into the element isolating region. A surface of that section of the second conductive layer which is positioned within the element isolating region is exposed, and a third conductive layer is formed on the second conductive layer with a second insulating film interposed therebetween. Further, a contact is electrically connected to an exposed surface of the second conductive layer.

Abstract: Non-volatile memory devices highly integrated using an oxide based compound semiconductor and methods of operating and fabricating the same are provided. A non-volatile memory device may include one or more oxide based compound semiconductor layers. A plurality of auxiliary gate electrodes may be arranged to be insulated from the one or more oxide based compound semiconductor layers. A plurality of control gate electrodes may be positioned between adjacent pairs of the plurality of auxiliary gate electrodes at a different level from the plurality of auxiliary gate electrodes. The plurality of control gate electrodes may be insulated from the one or more oxide based compound semiconductor layers. A plurality of charge storing layers may be interposed between the one or more oxide based compound semiconductor layers and the plurality of control gate electrodes.

Abstract: Provided are a nonvolatile memory device and a method of fabricating the same in which a channel length is effectively increased and high-integration may be possible. In the nonvolatile memory device, a semiconductor device may include an active region defined by a device isolation film. The active region may include at least one projecting portion. A pair of control gate electrodes may cover both side surfaces of the at least one projecting portion, and may be spaced apart from each other. A pair of charge storage layers may be between both side surfaces of the at least one projecting portion and the pair of control gate electrodes.

Abstract: Shield plates for reduced coupling between charge storage regions in nonvolatile semiconductor memory devices, and associated techniques for forming the same, are provided. Electrical fields associated with charge stored in the floating gates or other charge storage regions of a memory device can couple to neighboring charge storage regions because of the close, and continually decreasing proximity of these regions. A shield plate can be formed adjacent to the bit line sides of floating gates that face opposing bit line sides of adjacent floating gates. Insulating layers can be formed between each shield plate and its corresponding adjacent charge storage region. The insulating layers can extend to the levels of the upper surfaces of the control gates formed above the charge storage regions. In such a configuration, sidewall fabrication techniques can be implemented to form the insulating members and shield plates.

Abstract: Provided are a nonvolatile memory device and a method of operating the same, which have increased operation reliability and which facilitate increased integration. The nonvolatile memory device may include a semiconductor substrate, and at least one charge storage layer may be provided on a semiconductor substrate. At least one control gate electrode may be provided on the at least one charge storage layer. At least one first auxiliary gate electrode may be disposed on one side of and apart from the at least one charge storage layer and isolated from the semiconductor substrate.

Abstract: NAND arrays of memory cells are described, as well as methods of forming and using them. Memory cell charge storage devices, such as conductive floating gates, are oriented vertically in trenches, with control gates positioned both in the trenches between charge storage elements and over a horizontal surface between the trenches. Individual charge storage devices are therefore field coupled with two control gates, one on either side.

Abstract: A non-volatile memory is provided. A substrate having a plurality of trenches and a plurality of select gates is provided. The trenches are arranged in parallel and extend in a first direction. Each of the select gates is disposed on the substrate between two adjacent trenches respectively. A plurality of select gate dielectric layers are disposed between the select gates and the substrate. A plurality of composite layers are disposed over the surface of the trenches and each composite layer has a charge trapping layer. A plurality of word lines are arranged in parallel in a second direction, wherein each of the word lines fills the trenches between adjacent select gates and is disposed over the composite layers.

Abstract: A flash memory device having a region doped with a first impurity formed on a semiconductor substrate, a first polysilicon pattern having a substantially rectangular configuration formed on and/or over the region; a second polysilicon pattern having a substantially rectangular configuration formed on and/or over the first polysilicon pattern; a plurality of charge trapping layers formed on and/or over sidewalls of the first and second polysilicon patterns; and a plurality of control gates formed on and/or over the charge trapping layers.

Abstract: A non-volatile semiconductor memory device, which is intended to prevent data destruction by movements of electric charges between floating gates and thereby improve the reliability, includes element isolation/insulation films buried into a silicon substrate to isolate stripe-shaped element-forming regions. Formed on the substrate are a floating gate via a first gate insulating film and further a control gate via a second gate insulating film. Source and drain diffusion layers are formed in self-alignment with control gates. The second gate insulating film on the floating gate is divided and separated together with the floating gate by slits above the element isolation/insulation films into discrete portions of individual memory cells.

Abstract: A method for forming a split gate memory cell (10,11) using a semiconductor substrate (12) includes forming a select gate structure (48) and a sacrificial structure (50) over the substrate. An opening is between the select gate structure and the sacrificial structure. The opening is lined with a storage layer (56,168). The opening is further filled with select gate material (58,170). The sacrificial structure is removed after filling the opening with the select gate material.

Abstract: Split-gate memory cells and fabrication methods thereof. A split-gate memory cell comprises a plurality of isolation regions formed on a semiconductor substrate along a first direction, between two adjacent isolation regions defining an active region having a pair of drains and a source region. A pair of floating gates are disposed on the active regions and self-aligned with the isolation regions, wherein a top level of the floating gate is equal to a top level of the isolation regions. A pair of control gates are self-aligned with the floating gates and disposed on the floating gates along a second direction. A source line is disposed between the pair of control gates along the second direction. A pair of select gates are disposed on the outer sidewalls of the pair of control gates along the second direction.

Abstract: An insulating film provided below a floating gate electrode includes a first insulating film located at both end portions below the floating gate electrode, and a second insulating film sandwiched between the first insulating films and located in a middle portion below the floating gate electrode. The first insulating film and the second insulating film are formed in separate steps, and the first insulating film is thicker than the second insulating film. With this structure, when an insulating film is provided between the floating gate electrode and a silicon substrate to have a thickness more increased at its end portion than at its middle portion, the thickness can be increased more freely and a degree of the increase can be controlled more readily.

Abstract: A nonvolatile memory (NVM) device includes a floating gate on a semiconductor substrate and a gate insulating layer between the semiconductor substrate and the floating gate. A tunnel insulating layer is disposed between the semiconductor substrate and the floating gate. The tunnel insulating layer is thinner than the gate insulating layer. A first inter-gate insulating layer is disposed on the floating gate, and a sensing gate is disposed on the first inter-gate insulating layer. The sensing gate covers a first portion of the floating gate. A control gate is disposed to cover a top surface and a sidewall of a second portion of the floating gate. A second inter-gate insulating layer is disposed between the control gate and the sensing gate and between the control gate and the floating gate. Operation methods and fabrication methods of the NVM device are also provided.

Abstract: Memory devices, arrays, and strings are included that facilitate the use of vertical floating gate memory cells in NAND architecture memory strings, arrays, and devices. NAND Flash memory strings, arrays, and devices, include vertical Flash memory cells to form NAND architecture memory cell strings and memory arrays. These vertical memory cell NAND architecture strings allow for an improved high density memory devices or arrays that can take advantage of the feature sizes semiconductor fabrication processes are generally capable of and still allow for appropriate device sizing for operational considerations.

Abstract: A semiconductor device includes a device isolation layer in a semiconductor substrate, an active region defined by the device isolation layer, the active region including a main surface and a recess region including a bottom surface that is lower than the main surface, and a gate electrode formed over the recess region, wherein a top surface of the device isolation layer adjacent to the recess region is lower than the bottom surface of the recess region.

Abstract: A memory system is disclosed that includes a set of non-volatile storage elements. Each of said non-volatile storage elements includes source/drain regions at opposite sides of a channel in a substrate and a floating gate stack above the channel. The memory system also includes a set of shield plates positioned between adjacent floating gate stacks and electrically connected to the source/drain regions for reducing coupling between adjacent floating gates. The shield plates are selectively grown on the active areas of the memory without being grown on the inactive areas. In one embodiment, the shield plates are epitaxially grown silicon positioned above the source/drain regions.

Abstract: Provided are an EEPROM cell, an EEPROM device, and methods of manufacturing the EEPROM cell and the EEPROM device. The EEPROM cell is formed on a substrate including a first region and a second region. A first EEPROM device having a first select transistor and a first memory transistor is disposed in the first region, while a second EEPROM device having a second select transistor and a second memory transistor is disposed in the second region. In the first region, a first drain region and a second floating region are formed apart from each other. In the second region, a second drain region and a second floating region are formed apart from each other. A first impurity region, a second impurity region, and a third impurity region are disposed in a common source region between the first and second regions of the substrate. The first and third impurity regions form a DDD structure, and the first and second impurity region form an LDD structure.

Abstract: The channel of each nonvolatile semiconductor memory element has a plate-like shape, and a charge accumulating layer is formed on one face of the channel region, with an insulating film being interposed in between. A control gate electrode is then formed on the charge accumulating layer, with another insulating film being interposed in between. Another control gate electrode is formed on the other face of the channel region, with yet another insulating film being interposed in between. The plate-like semiconductor region is designed to have a thickness smaller than twice the largest depletion layer thickness determined by the impurity concentration. In this manner, variations of the threshold voltages varying with the voltage of the control gate electrodes can be made smaller than the minimum value in conventional elements.

Abstract: Disclosure is semiconductor device of a selective gate region, comprising a semiconductor layer, a first insulating film formed on the semiconductor layer, a first electrode layer formed on the first insulating layer, an element isolating region comprising an element isolating insulating film formed to extend through the first electrode layer and the first insulating film to reach an inner region of the semiconductor layer, the element isolating region isolating a element region and being self-aligned with the first electrode layer, a second insulating film formed on the first electrode layer and the element isolating region, an open portion exposing a surface of the first electrode layer being formed in the second insulating film, and a second electrode layer formed on the second insulating film and the exposed surface of the first electrode layer, the second electrode layer being electrically connected to the first electrode layer via the open portion.

Abstract: A memory device and a method for fabricating the same provide a device capable of increasing or maximizing the performance of a microstructure device. The device includes: a plurality of word lines formed with a gap therebetween and extending in parallel with each other in a first direction of extension; and a bit line insulated from the plurality of word lines, intersecting the plurality of word lines and extending in a second direction of extension, a transition electrode portion of the bit line positioned in the gap and spaced apart from the plurality of word lines by a predetermined distance, the transition electrode portion of the bit line configured and arranged to be bent toward any one of the plurality of word lines in response to an electrical signal applied to at least one of the plurality of word lines.

Abstract: A non-volatile memory including one or more EEPROM cell pairs. Each EEPROM cell pair includes three transistors and stores two data bits, effectively providing a 1.5 transistor EEPROM cell. An EEPROM cell pair includes a first non-volatile memory transistor, a second non-volatile memory transistor and a source access transistor. The source access transistor includes: a first source region continuous with a source region of the first non-volatile memory transistor; a second source region continuous with a source region of the second non-volatile memory transistor, and a drain region that extends downward through a first well region to contact a second well region. The first, second and third semiconductor regions and the second well region have a first conductivity type, and the first well region has a second conductivity type, opposite the first conductivity type.

Abstract: Embodiments herein present a structure, method, etc. for making high density MOSFET circuits with different height contact lines. The MOSFET circuits include a contact line, a first gate layer situated proximate the contact line, and at least one subsequent gate layer situated over the first gate layer. The contact line includes a height that is less than a combined height of the first gate layer and the subsequent gate layer(s). The MOSFET circuits further include gate spacers situated proximate the gate layers and a single contact line spacer situated proximate the contact line. The gate spacers are taller and thicker than the contact line spacer.

Abstract: A semiconductor device having a multi-bit nonvolatile memory cell is provided. The semiconductor device comprises a multi-bit nonvolatile memory unit cell sharing a source and a drain region and having a plurality of transistors. The plurality of transistors each comprise at least one control gate and at least one charge storage region. The charge storage regions are for accumulating charges within each of the plurality of transistors of the memory unit cell. Each of the control gates are connected to at least one control voltage to shift a threshold voltage in each of the plurality of transistors for storing multi-bit per unit cell.

Abstract: A device is described comprising a substrate of a first conductivity type having a first dopant concentration, a first well formed in the substrate, a second well of the first conductivity type formed in the substrate and being deeper than the first well, the second well having a higher dopant concentration than the first dopant concentration, and a nonvolatile memory cell formed on the second well. A device is described comprising four wells of various conductivity types with a nonvolatile memory cell formed on the second well. A device is described comprising a plurality of wells for isolating transistors of a plurality of voltage ranges, wherein each one of the plurality of wells contains at least one transistor of a particular voltage range, and wherein transistors of only one of the plurality of voltage ranges are within each of the plurality of wells.

Abstract: Provided is a nonvolatile memory device and method of operating and fabricating the same for higher integration and higher speed, while allowing for a lower operating current. The nonvolatile memory device may include a semiconductor substrate. Resistive layers each storing a variable resistive state may be formed on the surface of the semiconductor substrate. Buried electrodes may be formed on the semiconductor substrate under the resistive layers and may connect to the resistive layers. Channel regions may be formed on the surface of the semiconductor substrate and connect adjacent resistive layers to each other, but not to the buried electrodes. Gate insulating layers may be formed on the channel regions of the semiconductor substrate. Gate electrodes may be formed on the gate insulating layers and extend over the resistive layers.

Abstract: Non-volatile memory devices and methods for fabricating non-volatile memory devices are disclosed. More specifically, split gate memory devices are provided having frameworks that provide increased floating gate coupling ratios, thereby enabling enhanced programming and erasing efficiency and performance.

Abstract: A manufacturing method of a nonvolatile semiconductor memory includes steps (a) to (d). The (a) is a step of laminating a 2nd insulating film, a gate film and a hard mask film which cover a 1st gate electrode of a 1st memory cell transistor formed on a 1st region of a semiconductor substrate through a 1st insulating layer and a 3rd gate electrode of a 2nd memory cell transistor formed on a 2nd region through the 1st insulating layer. The (b) is a step of forming a 1st hard mask layer which covers a bottom portion and a side surface of a concave portion formed using the gate film between the 1st gate electrode and the 3rd gate electrode by etching the hard mask film. The (c) is a step of forming a 2nd gate electrode of the 1st memory cell transistor on the 1st region, a 4th gate electrode of the 2nd memory cell transistor on the 2nd region, and a connection layer which connects the 2nd gate electrode and the 4th gate electrode under the 1st hard mask layer by etching the gate film.

Abstract: A multi-bit memory cell (200) with a control gate (220) for controlling a middle portion of a channel region (208) provides improved operation including faster programming at smaller voltages and currents. The memory cell (200) includes a source (204) and a drain (206) diffused into a substrate (202) forming a channel region (208) therebetween. A first charge storing layer (214), a second charge storing layer (216) and the control gate (220) are formed on the substrate (202) over the channel region (208) and a gate (218) is formed over the source (204), the drain (206), the first and second charge storing layers (214, 216) and the control gate (220). Dielectric material (210, 212, 224, 226, 228) separates the source (204) and the drain (206) from the gate (218), and the control gate (220) from the first charge storing layer (214), the second charge storing layer (216) and the gate (218).

Abstract: A non-volatile memory having a gate structure, a pair of storage units and two assist gates is provided. The gate structure is disposed on the substrate. The storage units are disposed on the sidewalls of the gate structure. The assist gates are disposed on the respective sides of the gate structure and adjacent to the storage units. Each assist gate is shared between two adjacent memory cells. The gate structure, the storage units and the assist gates are electrically isolated from one another.

Abstract: Nonvolatile memory wordlines (160) are formed as sidewall spacers on sidewalls of control gate structures (280). Each control gate structure may contain floating and control gates (120, 140), or some other elements. Pedestals (340) are formed adjacent to the control gate structures before the conductive layer (160) for the wordlines is deposited. The pedestals will facilitate formation of the contact openings (330.1) that will be etched in an overlying dielectric (310) to form contacts to the wordlines. The pedestals can be dummy structures. A pedestal can physically contact two wordlines.

Abstract: Disclosed is a self-aligned non-volatile memory cell including a small sidewall spacer electrically coupled and being located next to a main floating gate region. Both the small sidewall spacer and the main floating gate region are formed on a substrate and both form the floating gate of the non-volatile memory cell. Both are isolated electrically from the substrate by an oxide layer which is thinner between the small sidewall spacer and the substrate; and is thicker between the main floating gate region and the substrate. The small sidewall spacer can be made small; therefore, the thin oxide layer area can also be made small to create a small pathway for electrons to tunnel into the floating gate.