With Additional, Non-memory Control Electrode Or Channel Portion (e.g., Accessing Field Effect Transistor Structure) Patents (Class 257/326)
  • Patent number: 11515325
    Abstract: A three-dimensional semiconductor memory device may include a peripheral circuit structure including transistors on a first substrate, and a cell array structure on the peripheral circuit structure, the cell array structure including: a first stack structure block comprising first stack structures arranged side by side in a first direction on a second substrate, a second stack structure block comprising second stack structures arranged side by side in the first direction on the second substrate, a separation structure disposed on the second substrate between the first stack structure block and the second stack structure block and comprising first mold layers and second mold layers, and a contact plug penetrating the separation structure. The cell array structure may include a first metal pad and the peripheral circuit structure may include a second metal pad. The first metal pad may be in contact with the second metal pad.
    Type: Grant
    Filed: September 18, 2020
    Date of Patent: November 29, 2022
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Bongsoon Lim, Sang-Wan Nam, Sang-Won Park, Sang-Won Shim, Hongsoo Jeon, Yonghyuk Choi
  • Patent number: 11515327
    Abstract: According to one embodiment, a source layer includes a semiconductor layer including an impurity. A stacked body includes a plurality of electrode layers stacked with an insulator interposed. A gate layer is provided between the source layer and the stacked body. The gate layer is thicker than a thickness of one layer of the electrode layers. A semiconductor body extends in a stacking direction of the stacked body through the stacked body and the gate layer. The semiconductor body further extends in the semiconductor layer where a side wall portion of the semiconductor body contacts the semiconductor layer. The semiconductor body does not contact the electrode layers and the gate layer.
    Type: Grant
    Filed: March 15, 2021
    Date of Patent: November 29, 2022
    Assignee: Kioxia Corporation
    Inventor: Shinya Arai
  • Patent number: 11508743
    Abstract: Embodiments of structure and methods for forming a three-dimensional (3D) memory device are provided. In an example, a 3D memory device includes a substrate and a stack structure in an insulating structure on the substrate. The stack structure includes alternating a plurality of conductor layers and a plurality of insulating layers. The 3D memory device further includes a source structure extending vertically through the alternating stack structure. The source structure includes at least one staggered portion along a respective sidewall. The 3D memory device further includes a channel structure and a support pillar each extending vertically through the alternating stack structure and a plurality of contact structures extending vertically through the insulating structure.
    Type: Grant
    Filed: December 26, 2019
    Date of Patent: November 22, 2022
    Assignee: YANGTZE MEMORY TECHNOLOGIES CO., LTD.
    Inventors: Hongbin Zhu, Juan Tang
  • Patent number: 11508525
    Abstract: A capacitor according to an embodiment includes a substrate having a first surface and a second surface and provided with one or more first through holes each extending from the first surface to the second surface, a first conductive layer covering the first surface, the second surface, and side walls of the one or more first through holes, a second conductive layer facing the first surface, the second surface, and the side walls of the one or more first through holes, with the first conductive layer interposed therebetween, and a dielectric layer interposed between the first conductive layer and the second conductive layer.
    Type: Grant
    Filed: March 16, 2020
    Date of Patent: November 22, 2022
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Kazuhito Higuchi, Susumu Obata, Keiichiro Matsuo, Mitsuo Sano
  • Patent number: 11495541
    Abstract: A three-dimensional semiconductor memory device may include a first stack structure block including first stack structures arranged in a first direction on a substrate, a second stack structure block including second stack structures arranged in the first direction on the substrate, a separation structure disposed on the substrate between the first and second stack structure blocks and including first mold layers and second mold layers, and a contact plug penetrating the separation structure. A bottom surface of the contact plug may contact the substrate.
    Type: Grant
    Filed: October 4, 2019
    Date of Patent: November 8, 2022
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Bongsoon Lim, Sang-Wan Nam, Sang-Won Park, Sang-Won Shim, Hongsoo Jeon, Yonghyuk Choi
  • Patent number: 11482537
    Abstract: According to an embodiment, a non-volatile memory device includes a first conductive layer, electrodes, an interconnection layer and at least one semiconductor layer. The electrodes are arranged between the first conductive layer and the interconnection layer in a first direction perpendicular to the first conductive layer. The interconnection layer includes a first interconnection and a second interconnection. The semiconductor layer extends through the electrodes in the first direction, and is electrically connected to the first conductive layer and the first interconnection. The device further includes a memory film between each of the electrodes and the semiconductor layer, and a conductive body extending in the first direction. The conductive body electrically connects the first conductive layer and the second interconnection, and includes a first portion and a second portion connected to the second interconnection. The second portion has a width wider than the first portion.
    Type: Grant
    Filed: July 28, 2020
    Date of Patent: October 25, 2022
    Assignee: Kioxia Corporation
    Inventors: Masaki Tsuji, Yoshiaki Fukuzumi
  • Patent number: 11476274
    Abstract: A memory array comprising strings of memory cells comprises an upper stack above a lower stack. The lower stack comprises vertically-alternating lower conductive tiers and lower insulative tiers. The upper stack comprises vertically-alternating upper conductive tiers and upper insulative tiers. An intervening tier is vertically between the upper and lower stacks. The intervening tier is at least predominantly polysilicon and of different composition from compositions of the upper conductive tier and the upper insulative tier immediately-above the intervening tier and of different composition from compositions of the lower conductive tier and the lower insulative tier immediately-below the intervening tier. Channel-material strings of memory cells extend through the upper stack, the intervening tier, and the lower stack. Other structures and methods are disclosed.
    Type: Grant
    Filed: July 14, 2020
    Date of Patent: October 18, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Daniel Billingsley, Jordan D. Greenlee, John D. Hopkins, Yongjun Jeff Hu
  • Patent number: 11462561
    Abstract: According to one embodiment, a semiconductor device includes: a wiring layer including a first metallic film provided on an oxide film, a second metallic film provided on the first metallic film, and a polysilicon film provided on the second metallic film; and an element layer provided on the wiring layer and including semiconductor elements electrically connected to the first metallic film. Standard Gibbs energy of formation of a first metal included in the first metallic film is lower than that of a second metal included in the second metallic film.
    Type: Grant
    Filed: August 28, 2020
    Date of Patent: October 4, 2022
    Assignee: Kioxia Corporation
    Inventors: Takashi Izumi, Akitsugu Hatazaki, Masaaki Hatano, Tatsumi Usami
  • Patent number: 11398498
    Abstract: Some embodiments include an integrated assembly having a first deck, a second deck over the first deck, and a third deck over the second deck. The first deck has first conductive levels disposed one atop another. The second deck has second conductive levels disposed one atop another. The third deck has third conductive levels disposed one atop another. A first staircase region extends to the first and second conductive levels, and passes through the third conductive levels. A second staircase region extends to the third conductive levels and not to the first and second conductive levels. Some embodiments include methods of forming integrated assemblies.
    Type: Grant
    Filed: May 28, 2020
    Date of Patent: July 26, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Shuangqiang Luo, Indra V. Chary
  • Patent number: 11393727
    Abstract: A structure and a formation method of a semiconductor device are provided. The semiconductor device includes a semiconductor substrate and a fin structure over the semiconductor substrate. The semiconductor device also includes a gate stack covering a portion of the fin structure and an epitaxially grown source/drain structure over the fin structure and adjacent to the gate stack. The semiconductor device further includes a semiconductor protection layer over the epitaxially grown source/drain structure. The semiconductor protection layer has an atomic concentration of silicon greater than that of the epitaxially grown source/drain structure.
    Type: Grant
    Filed: May 8, 2020
    Date of Patent: July 19, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Shiu-Ko Jangjian, Tzu-Kai Lin, Chi-Cherng Jeng
  • Patent number: 11393838
    Abstract: When a memory cell is formed over a first fin and a low breakdown voltage transistor is formed over a second fin, the depth of a first trench for dividing the first fins in a memory cell region is made larger than that of a second trench for dividing the second fins in a logic region. Thereby, in the direction perpendicular to the upper surface of a semiconductor substrate, the distance between the upper surface of the first fin and the bottom surface of an element isolation region in the memory cell region becomes larger than that between the upper surface of the second fin and the bottom surface of the element isolation region in the logic region.
    Type: Grant
    Filed: February 10, 2020
    Date of Patent: July 19, 2022
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Shibun Tsuda, Tomohiro Yamashita
  • Patent number: 11380716
    Abstract: An array substrate and manufacturing method thereof are provided. The array substrate includes: a substrate; a first gate electrode insulating layer disposed on the substrate, wherein the first gate electrode insulating layer has a recess therein; a gate electrode layer disposed in the recess of the first gate electrode insulating layer; a second gate electrode insulating layer covering the first gate electrode insulating layer and the gate electrode layer; and an active layer disposed on the second gate electrode insulating layer.
    Type: Grant
    Filed: November 11, 2019
    Date of Patent: July 5, 2022
    Assignee: TCL China Star Optoelectronics Technology Co., Ltd.
    Inventor: Meng Chen
  • Patent number: 11367681
    Abstract: Methods and apparatuses for slit oxide and via formation techniques are described, for example, for fabricating three dimensional memory devices that may include multiple decks of memory cells that each include memory cell stacks and associated access lines. The techniques may create an interconnect region without removing a portion of the memory cell stacks. The interconnect region may include one or more conductive vias extending through the decks of memory cells to couple the access lines with logic circuitry that may be located underneath the decks of memory cells. Further, the techniques may divide an array of memory cells into multiple subarrays of memory cells by forming trenches, which may sever the access lines. In some cases, each subarray of memory cells may be electrically isolated from other subarrays of memory cells. The techniques may reduce a total number of fabrication process steps.
    Type: Grant
    Filed: January 24, 2019
    Date of Patent: June 21, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Hongqi Li, Kaushik Varma Sagi, Manzar Siddik
  • Patent number: 11362104
    Abstract: A semiconductor memory device includes a substrate including a peripheral circuit, a stepped dummy stack overlapping the substrate and including a plurality of steps extending in a first direction, a plurality of contact groups passing through the stepped dummy stack, and upper lines respectively connected to the contact groups. The contact groups include a first contact group having two or more first contact plugs arranged in the first direction. The upper lines include a first upper line commonly connected to the first contact plugs.
    Type: Grant
    Filed: June 30, 2020
    Date of Patent: June 14, 2022
    Assignee: SK hynix Inc.
    Inventors: Byung Woo Kang, Min Sung Ko, Gwang Been Kim, Hwal Pyo Kim, Jin Taek Park, Young Ock Hong
  • Patent number: 11362186
    Abstract: A non-volatile memory device is provided. The non-volatile memory device includes a substrate, a first gate structure disposed on the substrate, a second gate structure disposed on the substrate, and a memory gate structure disposed on the substrate and between the first gate structure and the second gate structure. The memory gate structure at least covers the first gate structure and the second gate structure. The memory gate structure includes a charge storage layer disposed on the substrate and a memory gate layer disposed on the charge storage layer.
    Type: Grant
    Filed: March 27, 2020
    Date of Patent: June 14, 2022
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Kuo-Lung Li, Chih-Hao Pan, Szu-Ping Wang, Po-Hsuan Chen, Chi-Cheng Huang
  • Patent number: 11355513
    Abstract: According to one embodiment, a semiconductor storage device includes a stacked body that includes a plurality of first conductive layers stacked with a first insulating layer interposed therebetween and has a stair portion and a memory portion; and a first structure that extends in the stacked body in a predetermined direction and divides the stacked body, the first structure including a projection extending in the stacking direction across the plurality of first conductive layers, on a side surface thereof in the stair portion wherein the first structure includes: a second insulating layer that is provided in the projection; and a third insulating layer that covers end surfaces of the plurality of first conductive layers and the first insulating layer facing toward the first structure and continuously extends in the first structure over the memory portion and the stair portion.
    Type: Grant
    Filed: September 4, 2020
    Date of Patent: June 7, 2022
    Assignee: Kioxia Corporation
    Inventor: Kenichi Kadota
  • Patent number: 11349035
    Abstract: A semiconductor device includes a non-volatile memory (NVM) cell. The NVM cell includes a semiconductor wire disposed over an insulating layer disposed on a substrate. The NVM cell includes a select transistor and a control transistor. The select transistor includes a gate dielectric layer disposed around the semiconductor wire and a select gate electrode disposed on the gate dielectric layer. The control transistor includes a stacked dielectric layer disposed around the semiconductor wire and a control gate electrode disposed on the stacked dielectric layer. The stacked dielectric layer includes a charge trapping layer. The select gate electrode is disposed adjacent to the control gate electrode with the stacked dielectric layer interposed therebetween.
    Type: Grant
    Filed: June 22, 2020
    Date of Patent: May 31, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Cheng-Bo Shu, Yun-Chi Wu, Chung-Jen Huang
  • Patent number: 11342468
    Abstract: A semiconductor device includes a semiconductor layer, a charge storage layer disposed on the surface of the semiconductor layer via a first insulating film, and an electrode layer disposed on the surface of the charge storage layer via a second insulating film. The charge storage layer includes a first layer containing elemental aluminum and elemental nitrogen, a second layer containing elemental silicon and elemental nitrogen, and a third layer containing elemental oxygen.
    Type: Grant
    Filed: August 26, 2019
    Date of Patent: May 24, 2022
    Assignee: KIOXIA CORPORATION
    Inventors: Masaki Noguchi, Akira Takashima, Tatsunori Isogai
  • Patent number: 11322514
    Abstract: According to one embodiment, storage device comprises first wiring layers stacked along a first direction and a memory pillar extending through the first wiring layers. The memory pillar includes a first semiconductor layer. A second wiring layer is above an upper end of the memory pillar. A second semiconductor layer has a first portion between the first semiconductor layer and the second wiring layer and a second portion extending away from the first semiconductor layer. A first insulating layer is between the first portion and the second wiring layer in first direction, and also between the second portion and the second wiring layer in a second direction intersecting the first direction.
    Type: Grant
    Filed: March 2, 2020
    Date of Patent: May 3, 2022
    Assignee: KIOXIA CORPORATION
    Inventor: Hiroshi Nakaki
  • Patent number: 11302710
    Abstract: Some embodiments include an integrated assembly having a base (e.g., a monocrystalline silicon wafer), and having memory cells over the base and along channel-material-pillars. A conductive structure is between the memory cells and the base. The channel-material-pillars are coupled with the conductive structure. A foundational structure extends into the base and projects upwardly to a level above the conductive structure. The foundational structure locks the conductive structure to the base to provide foundational support to the conductive structure.
    Type: Grant
    Filed: January 10, 2020
    Date of Patent: April 12, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Darwin A. Clampitt, Matthew J. King, John D. Hopkins, M. Jared Barclay
  • Patent number: 11302828
    Abstract: A semiconductor device includes a memory cell which is configured of a FinFET having a split-gate type MONOS structure, the FinFET has a plurality of source regions formed in a plurality of fins, and the plurality of source regions are commonly connected by a source line contact. Further, the FinFET has a plurality of drain regions formed in the plurality of fins, the plurality of drain regions are commonly connected by a bit line contact, and the FinFET constitutes a memory cell of 1 bit.
    Type: Grant
    Filed: October 29, 2020
    Date of Patent: April 12, 2022
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Digh Hisamoto, Yoshiyuki Kawashima, Takashi Hashimoto
  • Patent number: 11289501
    Abstract: Some embodiments include a memory array which has a vertical stack of alternating insulative levels and wordline levels. A channel material extends vertically along the stack. The channel material includes a semiconductor composition and has first segments alternating with second segments. The first segments are adjacent the wordline levels and the second segments are adjacent the insulative levels. The first segments have a first dopant distribution and the second segments have a second dopant distribution which is different from the first dopant distribution. Some embodiments include methods of forming integrated assemblies.
    Type: Grant
    Filed: May 20, 2019
    Date of Patent: March 29, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Shyam Surthi, Byeung Chul Kim, Richard J. Hill, Francois H. Fabreguette, Gurtej S. Sandhu
  • Patent number: 11282858
    Abstract: According to one embodiment, a semiconductor memory device includes a plurality of first interconnect layers, first and second memory pillars, and a plurality of first plugs. The plurality of first interconnect layers include a first array region where the first memory pillar penetrates the plurality of first interconnect layers, a second array region where the second memory pillar penetrates the plurality of first interconnect layers, and a coupling region where a plurality of coupling parts respectively coupled to the plurality of first plugs are formed. Along a first direction parallel to the semiconductor substrate, the first array region, the coupling region, and the second array region are arranged in order.
    Type: Grant
    Filed: November 3, 2020
    Date of Patent: March 22, 2022
    Assignee: KIOXIA CORPORATION
    Inventors: Go Oike, Tsuyoshi Sugisaki
  • Patent number: 11276762
    Abstract: A semiconductor device includes a semiconductor layer structure, a gate insulating pattern on the semiconductor layer structure, a gate electrode on the gate insulating pattern, and an interface layer between the gate insulating pattern and the semiconductor layer structure, the interface layer having a first segment and a second segment with a gap therebetween.
    Type: Grant
    Filed: April 22, 2020
    Date of Patent: March 15, 2022
    Assignee: Wolfspeed, Inc.
    Inventor: Daniel Jenner Lichtenwalner
  • Patent number: 11257829
    Abstract: A semiconductor device includes: a semiconductor substrate; a first transistor provided at an upper surface of the semiconductor substrate; and a first capacitor provided above the first transistor and connected to a gate of the first transistor. A tunnel current is able to flow between the gate and the semiconductor substrate.
    Type: Grant
    Filed: March 12, 2020
    Date of Patent: February 22, 2022
    Assignees: KABUSHIKI KAISHA TOSHIBA, TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION
    Inventors: Shinji Kawahara, Takeshi Yamamoto, Kazuaki Yamaura, Nobuyuki Toda
  • Patent number: 11245071
    Abstract: Provided are a memory cell and a method of forming the same. The memory cell includes a bottom electrode, an etching stop layer, a variable resistance layer, and a top electrode. The etching stop layer is disposed on the bottom electrode. The variable resistance layer is embedded in the etching stop layer and in contact with the bottom electrode. The top electrode is disposed on the variable resistance layer. A semiconductor device having the memory cell is also provided.
    Type: Grant
    Filed: January 8, 2020
    Date of Patent: February 8, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yu-Chao Lin, Carlos H. Diaz, Shao-Ming Yu, Tung-Ying Lee
  • Patent number: 11244955
    Abstract: A memory array comprising strings of memory cells comprises laterally-spaced memory blocks individually comprising a vertical stack comprising alternating insulative tiers and conductive tiers. Operative channel-material strings of memory cells extend through the insulative tiers and the conductive tiers. Insulative pillars are laterally-between and longitudinally-spaced-along immediately-laterally-adjacent of the memory blocks. The pillars are directly against conducting material of conductive lines in the conductive tiers. Other arrays, and methods, are disclosed.
    Type: Grant
    Filed: August 25, 2019
    Date of Patent: February 8, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Paolo Tessariol, Justin B. Dorhout, Jian Li, Ryan L. Meyer
  • Patent number: 11239161
    Abstract: A memory device includes a semiconductor layer including adjacent cell and non-cell areas in a first direction, first and second conductive lines on the layer, extending along the first direction and arranged away from each other in a second direction crossing the first direction, conductor layers arranged above the semiconductor layer in a third direction crossing the first and second directions, pillars on the cell area, passing through the conductor layers in the third direction and forming memories at intersections with the conductor layers, and shunt lines extending along the second direction and arranged in the first direction above the cell area, each of the shunt lines connected to the first and second lines via third conductive lines. A length between the shunt line closest to the non-cell area and a boundary between the cell and non-cell areas is less than a length between adjacent shunt lines.
    Type: Grant
    Filed: March 3, 2020
    Date of Patent: February 1, 2022
    Assignee: KIOXIA CORPORATION
    Inventor: Yoichi Minemura
  • Patent number: 11222954
    Abstract: A three-dimensional memory device includes an alternating stack of word-line-isolation insulating layers and word-line-level electrically conductive layers located over a substrate, a plurality of drain-select-level electrodes that are laterally spaced apart from each other overlying the alternating stack, memory stack structures containing a respective vertical semiconductor channel laterally surrounded by a respective memory film and vertically extending through the alternating stack and the plurality of drain-select-level electrodes, inter-select-gate electrodes located between a respective neighboring pair of the drain-select-level electrodes, and inter-select-gate dielectrics located between each of the inter-select-gate electrodes and a neighboring one of the drain-select-level electrodes. The inter-select-gate electrodes are not electrically connected to the drain-select-level electrodes.
    Type: Grant
    Filed: March 24, 2020
    Date of Patent: January 11, 2022
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Zhixin Cui, Hardwell Chibvongodze, Masatoshi Nishikawa
  • Patent number: 11211397
    Abstract: Embodiments of three-dimensional (3D) memory devices and methods for forming the 3D memory devices are disclosed. In an example, a NAND memory device includes a substrate, one or more peripheral devices on the substrate, a plurality of NAND strings above the peripheral devices, a single crystalline silicon layer above and in contact with the NAND strings, and interconnect layers formed between the peripheral devices and the NAND strings. In some embodiments, the NAND memory device includes a bonding interface at which an array interconnect layer contacts a peripheral interconnect layer.
    Type: Grant
    Filed: July 27, 2018
    Date of Patent: December 28, 2021
    Assignee: Yangtze Memory Technologies Co., Ltd.
    Inventors: Zhenyu Lu, Jun Chen, Jifeng Zhu, Yushi Hu, Qian Tao, Simon Shi-Ning Yang, Steve Weiyi Yang
  • Patent number: 11211503
    Abstract: In an example, a memory array may include a memory cell around at least a portion of a semiconductor. The memory cell may include a gate, a first dielectric stack to store a charge between a first portion of the gate and the semiconductor, and a second dielectric stack to store a charge between a second portion of the gate and the semiconductor, the second dielectric stack separate from the first dielectric stack.
    Type: Grant
    Filed: July 26, 2019
    Date of Patent: December 28, 2021
    Assignee: Micron Technology, Inc.
    Inventor: Arup Bhattacharyya
  • Patent number: 11201219
    Abstract: An integrated circuit device of an embodiment includes a substrate, a first transistor, an insulation layer, a first contact, a second contact, and a first single crystal portion. The first transistor includes a first gate electrode, and a first drain region, and wherein the first source region and the first drain region are disposed in the substrate. The first contact faces the first gate electrode. The second contact faces a first region that is first one of the first source region and the first drain region. The first single crystal portion is disposed on the first region and convex from a surface of the first region, and is located between the first region and the second contact.
    Type: Grant
    Filed: March 12, 2019
    Date of Patent: December 14, 2021
    Assignee: Toshiba Memory Corporation
    Inventors: Tomoya Inden, Katsuyuki Kitamoto
  • Patent number: 11201164
    Abstract: Some embodiments include a NAND memory array which has a vertical stack of alternating insulative levels and wordline levels. The wordline levels have terminal ends corresponding to control gate regions. Charge-trapping material is along the control gate regions of the wordline levels, and is spaced from the control gate regions by charge-blocking material. The charge-trapping material along vertically adjacent wordline levels is spaced by intervening regions through which charge migration is impeded. Channel material extends vertically along the stack and is spaced from the charge-trapping material by charge-tunneling material. Some embodiments include methods of forming NAND memory arrays.
    Type: Grant
    Filed: August 21, 2019
    Date of Patent: December 14, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Akira Goda, Yushi Hu
  • Patent number: 11195850
    Abstract: A method used in forming a memory array comprising strings of memory cells comprises forming a stack comprising vertically-alternating first tiers and second tiers. Intervening material is formed into the stack laterally-between and longitudinally-along immediately-laterally-adjacent memory block regions. The forming of the intervening material comprises forming pillars laterally-between and longitudinally-spaced-along the immediately-laterally-adjacent memory-block regions. The pillars individually extend through multiple of each of the first tiers and the second tiers. After forming the pillars, an intervening opening is formed individually alongside and between immediately-longitudinally-adjacent of the pillars. Fill material is formed in the intervening openings. Other embodiments, including structure, are disclosed.
    Type: Grant
    Filed: October 18, 2019
    Date of Patent: December 7, 2021
    Assignee: Micron Technology, Inc.
    Inventor: Matthew J. King
  • Patent number: 11195855
    Abstract: According to one embodiment, a semiconductor memory device includes: a plurality of first interconnect layers including first and second conductors; a second interconnect layer arranged above the first interconnect layers; a third interconnect layer arranged adjacently to the second interconnect layer; a first pillar passing through the first interconnect layers and the second interconnect layer; a second pillar passing through the first interconnect layers and the third interconnect layer; and a third pillar arranged between the second interconnect layer and the third interconnect layer and passing through the first interconnect layers. The second conductor covers a top surface and a bottom surface of the first conductor, and a side surface of an end portion of the first conductor.
    Type: Grant
    Filed: February 19, 2020
    Date of Patent: December 7, 2021
    Assignee: Kioxia Corporation
    Inventors: Kenichi Kadota, Kazuhiro Nojima, Taro Shiokawa
  • Patent number: 11195858
    Abstract: Provided is a semiconductor memory device according to an embodiment including: a stacked body including gate electrode layers stacked in a first direction; a semiconductor layer provided in the stacked body and extending in the first direction; and a gate insulating layer provided between the semiconductor layer and at least one of the gate electrode layers, and the gate insulating layer including a first region containing a first oxide including at least one of a hafnium oxide and a zirconium oxide, in which a first length of the at least one of the gate electrode layers in the first direction is larger than a second length of the first region in the first direction.
    Type: Grant
    Filed: June 8, 2020
    Date of Patent: December 7, 2021
    Assignee: Kioxia Corporation
    Inventors: Kunifumi Suzuki, Masumi Saitoh
  • Patent number: 11164629
    Abstract: Some embodiments include apparatuses, and methods of operating the apparatuses. Some of the apparatuses include a data line, a first memory cell string including first memory cells located in different levels of the apparatus, first access lines to access the first memory cells, a first select gate coupled between the data line and the first memory cell string, a first select line to control the first select gate, a second memory cell string including second memory cells located in different levels of the apparatus, second access lines to access the second memory cells, the second access lines being electrically separated from the first access lines, a second select gate coupled between the data line and the second memory cell string, a second select line to control the second select gate, and the first select line being in electrical contact with the second select line.
    Type: Grant
    Filed: July 6, 2020
    Date of Patent: November 2, 2021
    Assignee: Micron Technology, Inc.
    Inventor: Aaron Yip
  • Patent number: 11158646
    Abstract: A memory device with a dielectric blocking layer for improving interpoly dielectric breakdown is provided. Embodiments include.
    Type: Grant
    Filed: January 14, 2019
    Date of Patent: October 26, 2021
    Assignee: GLOBALFOUNDRIES Singapore Pte. Ltd.
    Inventor: Soh Yun Siah
  • Patent number: 11133465
    Abstract: Embodiments of 3D memory devices and methods for forming the same are disclosed. In an example, a method for forming a 3D memory device is disclosed. A lower bit line contact and a lower bit line in contact with the lower bit line contact are formed. Lower memory cells are formed above and in contact with the lower bit line. Each lower memory cell includes stacked a phase-change memory (PCM) element, a selector, and electrodes. Parallel word lines in a same plane are formed above and in contact with the lower memory cells. Each word line is perpendicular to the lower bit line. Upper memory cells are formed above and in contact with the word lines. Each upper memory cell includes stacked a PCM element, a selector, and electrodes. An upper bit line is formed above and in contact with the upper memory cells. The upper bit line is perpendicular to each word line. An upper bit line contact is formed above and in contact with the upper bit line.
    Type: Grant
    Filed: December 26, 2019
    Date of Patent: September 28, 2021
    Assignee: YANGTZE MEMORY TECHNOLOGIES CO., LTD.
    Inventor: Jun Liu
  • Patent number: 11133326
    Abstract: In a semiconductor device including a plurality of memory regions formed of split-gate type MONOS memories, threshold voltages of memory cells are set to different values for each memory region. Memory cells having different threshold voltages are formed by forming a metal film, which is a work function film constituting a memory gate electrode of a memory cell in a data region, and a metal film, which is a work function film constituting a memory gate electrode of a memory cell in a code region, of different materials or different thicknesses.
    Type: Grant
    Filed: May 13, 2019
    Date of Patent: September 28, 2021
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Naoki Takizawa, Tomoya Saito
  • Patent number: 11127691
    Abstract: A method of forming a semiconductor device comprising forming a patterned resist over a stack comprising at least one material and removing a portion of the stack exposed through the patterned resist to form a stack opening. A portion of the patterned resist is laterally removed to form a trimmed resist and an additional portion of the stack exposed through the trimmed resist is removed to form steps in sidewalls of the stack. A dielectric material is formed between the sidewalls of the stack to substantially completely fill the stack opening, and the dielectric material is planarized. Additional methods are disclosed, as well as semiconductor devices.
    Type: Grant
    Filed: December 28, 2018
    Date of Patent: September 21, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Rohit Kothari, Adam L. Olson, John D. Hopkins, Jeslin J. Wu
  • Patent number: 11120883
    Abstract: A semiconductor storage device includes a first semiconductor extending above a substrate and including a first part and a second part, a first word line at a first level above the substrate and facing the first part of the first semiconductor, a second word line at the first level above the substrate and facing the second part of the first semiconductor, a first cell transistor including a first area of the first part of the first semiconductor that faces the first word line, and a second cell transistor including a second area of the second part of the first semiconductor that faces the second word line, wherein during an operation of reading data from the first cell transistor, a first voltage that is less than a threshold voltage of the second cell transistor and greater than or equal to zero voltage is applied to the second word line.
    Type: Grant
    Filed: September 16, 2020
    Date of Patent: September 14, 2021
    Assignee: KIOXIA CORPORATION
    Inventors: Takuya Futatsuyama, Masanobu Shirakawa
  • Patent number: 11107828
    Abstract: A semiconductor memory device includes a first semiconductor chip and a second semiconductor chip. Each semiconductor chip of the first and second semiconductor chips may include a cell array region and a peripheral circuit region. The cell array region may include an electrode structure including electrodes sequentially stacked on a body conductive layer and vertical structures extending through the electrode structure and connected to the body conductive layer. The peripheral circuit region may include a residual substrate on the body conductive layer and on which a peripheral transistor is located. A bottom surface of the body conductive layer of the second semiconductor chip may face a bottom surface of the body conductive layer of the first semiconductor chip.
    Type: Grant
    Filed: June 16, 2020
    Date of Patent: August 31, 2021
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sung-Min Hwang, Joon-Sung Lim, Eunsuk Cho
  • Patent number: 11049877
    Abstract: A semiconductor memory includes a substrate and an alternating stack of first insulators and first conductors above the substrate. First to third regions are provided in this order along a direction parallel to a surface of the substrate. The alternating stack is in a dummy region at part of each of the first to third regions. Second and third conductors extend in parallel to each other in the direction above a top one of the first conductors. A plurality of first pillars extend through the second conductor. A plurality of second pillars extend through the third conductor. A columnar first contact is provided on the second conductor in the first region, and a columnar second contact is provided on the third conductor in the first region. The second and third conductors are separated from each other in the first and second regions, and connected to each other in the third region.
    Type: Grant
    Filed: June 8, 2020
    Date of Patent: June 29, 2021
    Assignee: KIOXIA CORPORATION
    Inventor: Go Oike
  • Patent number: 10998334
    Abstract: A three-dimensional semiconductor memory device may include a stack including gate electrodes sequentially stacked on a substrate and a vertical structure penetrating the stack. The vertical structure may include a vertical channel portion, a charge storing structure on an outer side surface of the vertical channel portion, and a pad. The pad may include a first pad portion disposed in an internal space surrounded by the vertical channel portion and a second pad portion provided on the first pad portion and extended onto a top surface of the charge storing structure. A portion of the first pad portion may be disposed at the same level as an uppermost electrode of the gate electrodes.
    Type: Grant
    Filed: August 9, 2019
    Date of Patent: May 4, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Bongyong Lee, Minkyung Bae, Myunghun Woo
  • Patent number: 10971507
    Abstract: A first alternating stack of first insulating layers and first sacrificial material layers with first stepped surfaces is formed over a substrate. A first retro-stepped dielectric material portion is formed on the first stepped surfaces. A second alternating stack of second insulating layers and second sacrificial material layers with second stepped surfaces is formed over the first alternating stack. A second retro-stepped dielectric material portion is formed on the second stepped surfaces. A first conductive via structure is formed through the second retro-stepped dielectric material portion, a bottommost insulating layer of the second alternating stack, and the first retro-stepped dielectric material portion. The sacrificial material layers are replaced with electrically conductive layers.
    Type: Grant
    Filed: October 1, 2019
    Date of Patent: April 6, 2021
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventor: Michimoto Kaminaga
  • Patent number: 10964752
    Abstract: A vertically alternating sequence of insulating layers and sacrificial material layers is formed over a substrate. Line trenches extending along a first horizontal direction are formed through the vertically alternating sequence. The vertically alternating sequence is divided into vertically alternating stacks of insulating strips and sacrificial material strips. Laterally alternating sequences of memory opening fill structures and dielectric pillar structures are formed within the line trenches. Each of the memory opening fill structures includes a respective vertical bit line and memory material portion located between each laterally neighboring pair of the sacrificial material strip and the vertical bit line.
    Type: Grant
    Filed: June 13, 2019
    Date of Patent: March 30, 2021
    Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
    Inventors: Yuji Takahashi, Masatoshi Nishikawa, Wei Kuo Shih
  • Patent number: 10950625
    Abstract: A method of manufacturing a semiconductor device includes replacing sacrificial layers with conductive patterns through slits and at least one opening that pass through a stack structure. The stack structure includes interlayer insulating layers and the sacrificial layers. The interlayer insulating layers and the sacrificial layers surround a support and are alternately stacked on each other.
    Type: Grant
    Filed: June 17, 2019
    Date of Patent: March 16, 2021
    Assignee: SK hynix Inc.
    Inventor: Yeo Jin Jeong
  • Patent number: 10943782
    Abstract: Disclosed are semiconductor devices and methods of manufacturing the same. The method comprises alternately stacking a plurality of dielectric layers and a plurality of first semiconductor layers to form a mold structure on a substrate, forming a hole penetrating the mold structure, forming on the substrate a second semiconductor layer filling the hole, and irradiating a laser onto the second semiconductor layer.
    Type: Grant
    Filed: July 2, 2019
    Date of Patent: March 9, 2021
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hui-jung Kim, Kiseok Lee, Keunnam Kim, Yoosang Hwang
  • Patent number: 10923601
    Abstract: A split gate device that includes a memory gate and a select gate disposed side by side, a dielectric structure having a first portion disposed between the memory gate and a substrate and a second portion disposed along an inner sidewall of the select gate to separate the select gate from the memory gate, and a spacer formed over the select gate along an inner sidewall of the memory gate. Other embodiments of embedded split gate devices including high voltage and low voltage transistors are also disclosed.
    Type: Grant
    Filed: April 10, 2018
    Date of Patent: February 16, 2021
    Assignee: Cypress Semiconductor Corporation
    Inventors: Chun Chen, Shenqing Fang, Unsoon Kim, Mark T. Ramsbey, Kuo Tung Chang, Sameer S. Haddad