Plural Gate Electrodes Or Grid Shaped Gate Electrode Patents (Class 257/331)
  • Patent number: 10727246
    Abstract: A three-dimensional semiconductor device includes a stacked structure including a plurality of conductive layers stacked on a substrate, a distance along a first direction between sidewalls of an upper conductive layer and a lower conductive layer being smaller than a distance along a second direction between sidewalls of the upper conductive layer and the lower conductive layer, the first and second directions crossing each other and defining a plane parallel to a surface supporting the substrate, and vertical channel structures penetrating the stacked structure.
    Type: Grant
    Filed: November 15, 2017
    Date of Patent: July 28, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Sang-Yong Park, Jintaek Park
  • Patent number: 10727339
    Abstract: Vertical semiconductor devices having selectively regrown top contacts and method of fabricating vertical semiconductor devices having selectively regrown top contacts are described. For example, a semiconductor device includes a substrate having a surface. A first source/drain region is disposed on the surface of the substrate. A vertical channel region is disposed on the first source/drain region and has a first width parallel with the surface of the substrate. A second source/drain region is disposed on the vertical channel region and has a second width parallel with and substantially greater than the first width. A gate stack is disposed on and completely surrounds a portion of the vertical channel region.
    Type: Grant
    Filed: March 28, 2014
    Date of Patent: July 28, 2020
    Assignee: Intel Corporation
    Inventors: Benjamin Chu-Kung, Gilbert Dewey, Van H. Le, Jack T. Kavalieros, Marko Radosavljevic, Ravi Pillarisetty, Han Wui Then, Niloy Mukherjee, Sansaptak Dasgupta
  • Patent number: 10707343
    Abstract: A method of manufacturing a semiconductor device includes in this order: a semiconductor base body preparing step; a first trench forming step; a first insulation film forming step of forming a first insulation film; a gate insulation film forming step; a gate electrode forming step; a second trench forming step of forming a second trench in the inside of a first trench by removing a center portion of the first insulation film; a second insulation film forming step of forming a second insulation film in the inside of the second trench under a condition that a gap remain in the inside of the second trench; a shield electrode forming step of forming a shield electrode in the inside of the gap; and a source electrode forming step of forming a source electrode.
    Type: Grant
    Filed: March 31, 2016
    Date of Patent: July 7, 2020
    Assignee: SHINDENGEN ELECTRIC MANUFACTURING CO., LTD.
    Inventor: Kinya Ohtani
  • Patent number: 10699964
    Abstract: Among other things, one or semiconductor arrangements, and techniques for forming such semiconductor arrangements are provided. For example, one or more silicon and silicon germanium stacks are utilized to form PMOS transistors comprising germanium nanowire channels and NMOS transistors comprising silicon nanowire channels. In an example, a first silicon and silicon germanium stack is oxidized to transform silicon to silicon oxide regions, which are removed to form germanium nanowire channels for PMOS transistors. In another example, silicon and germanium layers within a second silicon and silicon germanium stack are removed to form silicon nanowire channels for NMOS transistors. PMOS transistors having germanium nanowire channels and NMOS transistors having silicon nanowire channels are formed as part of a single fabrication process.
    Type: Grant
    Filed: November 30, 2018
    Date of Patent: June 30, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Kuo-Cheng Ching, Carlos H. Diaz, Jean-Pierre Colinge
  • Patent number: 10686066
    Abstract: This semiconductor device includes: an n-type SiC drift layer; a p-type base region; an n-type source region selectively embedded in the top part of the base region; p-type base contact regions selectively embedded in the top part of the base region so as to form a first gap with the source region along the <11-20> direction; a gate electrode provided via a gate insulating film; and an n-type drain region. The top surface of the drain region has an off-angle relative to the <11-20> direction towards the <0001> direction, and an alignment mark for positioning is formed on the top surface. The drift layer and the base region are epitaxially grown films, and a width wg of the first gap is set in accordance with a positional deviation width of the alignment mark caused by the off-angle and epitaxial growth.
    Type: Grant
    Filed: October 24, 2018
    Date of Patent: June 16, 2020
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventor: Keiji Okumura
  • Patent number: 10679994
    Abstract: Circuits employing asymmetric diffusion breaks in different type semiconductor diffusion regions are disclosed. In examples herein, diffusion breaks having dimensions asymmetric to each other are provided in different types of diffusion regions in a circuit to increase carrier mobility in semiconductor channels of a semiconductor device formed in different diffusion regions. In examples herein, the circuit includes a P-type and N-type semiconductor device(s) formed in a P-type and an N-type diffusion region(s), respectively, formed in the substrate. Complementary metal oxide semiconductor (CMOS) circuits can be realized from the P-type and N-type semiconductor devices. Diffusion breaks can induce strain in the diffusion regions with a magnitude of the induced strain related to a dimension of the diffusion breaks. As one example, an induced tensile strain may increase carrier mobility in N-type devices and decrease carrier mobility in P-type devices, with induced compressive strain having the opposite effect.
    Type: Grant
    Filed: November 28, 2018
    Date of Patent: June 9, 2020
    Assignee: QUALCOMM Incorporated
    Inventor: Haining Yang
  • Patent number: 10672782
    Abstract: A semiconductor memory device includes a semiconductor substrate, transistors formed in an upper surface of the semiconductor substrate, a stacked body provided on the semiconductor substrate, a first contact, and a second contact. The transistors are arranged along a first direction. A minimum period of an arrangement of the transistors is a first period. The stacked body includes electrode films. A configuration of a first portion of the stacked body is a staircase-like having terraces. A first region and a second region are set along the first direction in the first portion. A length in the first direction of the terrace disposed in the second region is longer than the first period. A length in the first direction of the terrace disposed in the first region is shorter than the first period.
    Type: Grant
    Filed: April 29, 2019
    Date of Patent: June 2, 2020
    Assignee: Toshiba Memory Corporation
    Inventor: Tetsuaki Utsumi
  • Patent number: 10658351
    Abstract: An electronic device can include a transistor having a gate electrode, a first portion, and a second portion, wherein along the gate electrode, the first portion of the transistor has a first gate-to-drain capacitance and a first gate-to-source capacitance, the second portion of the transistor has a second gate-to-drain capacitance and a second gate-to-source capacitance, and a ratio of the first gate-to-drain capacitance to the first gate-to-source capacitance is less than a ratio of the second gate-to-drain capacitance to the second gate-to-source capacitance.
    Type: Grant
    Filed: August 16, 2018
    Date of Patent: May 19, 2020
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Balaji Padmanabhan, Kirk K. Huang, Prasad Venkatraman, Emily M. Linehan, Zia Hossain
  • Patent number: 10651276
    Abstract: A semiconductor device has a cell which includes a first semiconductor region of a first conductive type, a base region of a second conductive type on the first semiconductor region, a source region of the first conductive type on the base region, a gate electrode penetrating through the base region in a first direction to reach the first semiconductor region and extending in a second direction, and a gate insulting film between the gate electrode and the first semiconductor region, between the gate electrode and the base region, and between the gate electrode and the source region. The cell has a region having a first threshold voltage and a region having a second threshold voltage higher than the first threshold voltage.
    Type: Grant
    Filed: September 12, 2018
    Date of Patent: May 12, 2020
    Assignees: KABUSHIKI KAISHA TOSHIBA, TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION
    Inventors: Tatsuya Nishiwaki, Kohei Oasa, Hiroshi Matsuba, Hung Hung, Kikuo Aida, Kentaro Ichinoseki
  • Patent number: 10651301
    Abstract: In one embodiment, a semiconductor device includes a semiconductor substrate having an upper surface, a trench electrode placed inside a trench formed on the upper surface, and a trench insulating film placed between the trench electrode and the semiconductor substrate, and the semiconductor substrate includes a drift layer, a floating layer for electric field reduction, a hole barrier layer, a body layer and an emitter layer, and the emitter layer, the body layer and the hole barrier layer are separated from the drift layer by the floating layer for electric field reduction, and a path of a carrier passing through an inverted layer formed in the body layer includes the body layer, the hole barrier layer, a non-inverted region of the floating layer for electric field reduction, and the drift layer.
    Type: Grant
    Filed: May 15, 2018
    Date of Patent: May 12, 2020
    Assignee: Renesas Electronics Corporation
    Inventors: Ryo Kanda, Hitoshi Matsuura
  • Patent number: 10629595
    Abstract: A power semiconductor device includes a semiconductor substrate having a first side. A plurality of active transistor cells is formed in an active area of the semiconductor substrate. Each of the plurality of active transistor cells includes a spicular trench which extends from the first side into the semiconductor substrate and has a field electrode. A gate electrode structure has a plurality of intersecting gate trenches running between the spicular trenches. The intersecting gate trenches form gate crossing regions of different shape when seen in a plan projection onto the first side of the power semiconductor device.
    Type: Grant
    Filed: June 27, 2018
    Date of Patent: April 21, 2020
    Assignee: Infineon Technologies Austria AG
    Inventors: Cedric Ouvrard, Cesar Augusto Braz, Olivier Guillemant, David Laforet, Gerhard Noebauer, Li Juin Yip
  • Patent number: 10622365
    Abstract: A semiconductor device, the device including: a plurality of memory cells; and peripheral circuits, the peripheral circuits include controlling the plurality of memory cells, where each of the plurality of memory cells includes a first gate and a second gate, where the plurality of memory cells each include a channel region, at least one channel facet, a charge trap region and a tunneling region, where a portion of the peripheral circuits are designed to control the first gate and the second gate so to position two distinct memory sites, a first memory site and second a memory site, within the charge trap region of the at least one channel facet of at least one of the plurality of memory cells, and where the first memory site is substantially closer to the first gate than the second memory site.
    Type: Grant
    Filed: April 7, 2019
    Date of Patent: April 14, 2020
    Assignee: MONOLITHIC 3D INC.
    Inventors: Zvi Or-Bach, Jin-Woo Han
  • Patent number: 10615215
    Abstract: A solid-state imaging device includes a pixel having a photoelectric conversion element which generates a charge in response to incident light, a first transfer gate which transfers the charge from the photoelectric conversion element to a charge holding section, and a second transfer gate which transfers the charge from the charge holding section to a floating diffusion. The first transfer gate includes a trench gate structure having at least two trench gate sections embedded in a depth direction of a semiconductor substrate, and the charge holding section includes a semiconductor region positioned between adjacent trench gate sections.
    Type: Grant
    Filed: July 6, 2018
    Date of Patent: April 7, 2020
    Assignee: Sony Semiconductor Solutions Corporation
    Inventor: Takahiro Kawamura
  • Patent number: 10615118
    Abstract: An anti-fuse device includes a program transistor and a read transistor. The program transistor executes a program via insulation breakdown of a gate insulating layer. The read transistor is adjacent to the program transistor and reads the state of the program transistor. At least one of a first gate electrode of the program transistor or a second gate electrode of the read transistor is buried in a substrate.
    Type: Grant
    Filed: February 26, 2019
    Date of Patent: April 7, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventor: Dong-hyun Lee
  • Patent number: 10600886
    Abstract: A vertical fin field-effect-transistor and a method for fabricating the same. The vertical fin field-effect-transistor includes a substrate, a first source/drain layer including a plurality of pillar structures, and a plurality of fins disposed on and in contact with the plurality of pillar structures. A doped layer epitaxially grown from the first source/drain layer is in contact with the plurality of fins and the plurality of pillar structures. A gate structure is disposed in contact with two or more fins in the plurality of fins. The gate structure includes a dielectric layer and a gate layer. A second source/drain layer is disposed on the gate structure. The method includes epitaxially growing a doped layer in contact with a plurality of fins and a plurality of pillar structures. A gate structure is formed in contact with two or more fins. A second source/drain layer is formed on the gate structure.
    Type: Grant
    Filed: November 2, 2018
    Date of Patent: March 24, 2020
    Assignee: International Business Machines Corporation
    Inventors: Kangguo Cheng, Xin Miao, Wenyu Xu, Chen Zhang
  • Patent number: 10593787
    Abstract: A semiconductor layer may be subjected to etching to form a trench therein. An epitaxial layer may be further formed in the trench. Here, the impurity concentration of the epitaxial layer is controlled to be lower than that of the semiconductor layer. In this manner, concentration of electrical fields in the trench is reduced. A first innovations herein provides a semiconductor device including a first semiconductor layer containing impurities of a first conductivity type, a trench provided in the first semiconductor layer on a front surface side thereof, and a second semiconductor layer provided on an inner wall of the trench, where the second semiconductor layer contains impurities of the first conductivity type at a lower concentration than the first semiconductor layer.
    Type: Grant
    Filed: April 1, 2016
    Date of Patent: March 17, 2020
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventor: Takeyoshi Nishimura
  • Patent number: 10586862
    Abstract: A semiconductor device according to embodiments includes, a SiC substrate, SiC layer, a trench having a side face and a bottom face, a first conductivity type first SiC region, a second conductivity type second SiC region between the first SiC region and the SiC substrate, a first conductivity type third SiC region between the second SiC region and the SiC substrate, a boundary between the second SiC region and the third SiC region provided at a side of the side face, the boundary including a first region, a distance between the first region and a front face of the SiC layer increasing as a distance from the side face to the first region increasing, and distance from the side face to the first region being 0 ?m or more and 0.3 ?m or less, a gate insulating film and gate insulating film.
    Type: Grant
    Filed: August 1, 2016
    Date of Patent: March 10, 2020
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Teruyuki Ohashi, Ryosuke Iijima
  • Patent number: 10566330
    Abstract: A CMOS system on chip including a series of partial gate-all-around field effect transistors. Each partial GAA FET includes a fin having a stack of channel regions, source and drain regions on opposite sides of the fin, a dielectric separation region including a dielectric material between first and second channel regions, a gate stack on the fin, and a pair of sidewall spacers on opposite sides of the gate stack. A portion of the dielectric separation region has a length from an outer edge of the dielectric separation region to an inner edge of a respective sidewall spacer. The length of the portion of the dielectric separation region of one of the partial GAA FETs is different than the length of the portion of the dielectric separation region of another one of the partial GAA FETs.
    Type: Grant
    Filed: May 11, 2018
    Date of Patent: February 18, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Mark S. Rodder, Borna J. Obradovic, Dharmendar Palle, Rwik Sengupta, Mohammad Ali Pourghaderi
  • Patent number: 10546872
    Abstract: A three-dimensional nonvolatile memory device and a method for fabricating the same include a semiconductor substrate, a plurality of active pillars, a plurality of gate electrodes, and a plurality of supporters. The semiconductor substrate includes a memory cell region and a contact region. The active pillars extend in the memory cell region perpendicularly to the semiconductor substrate. The gate electrodes intersect the active pillars, extend from the memory cell region to the contact region and are stacked on the semiconductor substrate. The supporters extend in the contact region perpendicularly to the semiconductor substrate to penetrate at least one or more of the gate electrodes.
    Type: Grant
    Filed: June 27, 2017
    Date of Patent: January 28, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Soodoo Chae, Myoungbum Lee, HuiChang Moon, Hansoo Kim, JinGyun Kim, Kihyun Kim, Siyoung Choi, Hoosung Cho
  • Patent number: 10546867
    Abstract: According to one embodiment, a method for manufacturing a semiconductor device includes forming a first metal material inside the first holes; forming a plurality of metal layers on the first region, the metal layers being stacked with an insulator interposed, the metal layers including a plurality of terrace portions arranged in a staircase configuration with a level difference; forming a second insulating layer on the first insulating layer and on the terrace portions; simultaneously forming a second hole and a plurality of third holes piercing the second insulating layer, the second hole reaching the first metal material, the third holes reaching the terrace portions; and forming a second metal material inside the second hole and inside the third holes.
    Type: Grant
    Filed: February 28, 2018
    Date of Patent: January 28, 2020
    Assignee: Toshiba Memory Corporation
    Inventor: Yuya Matsuda
  • Patent number: 10546857
    Abstract: A complementary metal oxide semiconductor (CMOS) vertical transistor structure with closely spaced p-type and n-type vertical field effect transistors (FETs) is provided. After forming a dielectric material portion contacting a proximal sidewall of a first semiconductor fin for formation of a p-type vertical FET and a proximal sidewall of a second semiconductor fin for formation of an n-type vertical FET, a first gate structure is formed contacting a distal sidewall of the first semiconductor fin, and a second gate structure is formed contacting a distal sidewall of the second semiconductor fin. Because no gate structures are formed between the first and second semiconductor fins, the p-type vertical FET is spaced from the n-type FET only by the dielectric material portion.
    Type: Grant
    Filed: February 16, 2017
    Date of Patent: January 28, 2020
    Assignee: International Business Machines Corporation
    Inventors: Karthik Balakrishnan, Kangguo Cheng, Pouya Hashemi, Alexander Reznicek
  • Patent number: 10522466
    Abstract: The present disclosure provides a semiconductor structure. The semiconductor structure includes a semiconductor substrate, a target layer, a plurality of metal pads, a plurality of conductive lines, a plurality of conductive plugs, an isolating liner, and a plurality of metal contacts. The semiconductor substrate has a front surface, a rear surface opposite to the front surface, and an implanted region connected to the rear surface. The target layer is disposed over the front surface. The metal pads are disposed over the target layer. The plurality of conductive lines are disposed within the semiconductor substrate and the target layer and connected to the metal pads. The conductive plugs are disposed in the implanted region. The isolating liner encircles the conductive plugs. The metal contacts are disposed over the conductive lines and the conductive plugs.
    Type: Grant
    Filed: October 5, 2018
    Date of Patent: December 31, 2019
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventor: Hsih-Yang Chiu
  • Patent number: 10515976
    Abstract: A semiconductor device includes a semiconductor substrate, an isolation structure; a first gate dielectric layer and a first gate electrode. The isolation structure is formed in the semiconductor substrate to divide the semiconductor substrate at least into a first active region and a second active region. The first gate dielectric layer is disposed on the first active region, and has a plane top surface contacting to a sidewall of the isolation structure and forming an acute angle therewith. The first gate electrode stacked on the plane top surface.
    Type: Grant
    Filed: February 1, 2018
    Date of Patent: December 24, 2019
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Wen-Chung Chang, Tzu-Ping Chen
  • Patent number: 10515981
    Abstract: A multilevel semiconductor device, the device including: a first level including a first array of first programmable cells and a first control line; a second level including a second array of second programmable cells and a second control line; and a third level including a third array of third programmable cells and a third control line, where the second level overlays the first level, where the third level overlays the second level, where the first programmable cells are self-aligned to the second programmable cells, and where a programmable logic cell includes a plurality of the first programmable cells and a plurality of the second programmable cells.
    Type: Grant
    Filed: September 21, 2016
    Date of Patent: December 24, 2019
    Assignee: MONOLITHIC 3D INC.
    Inventors: Zvi Or-Bach, Jin-Woo Han
  • Patent number: 10515954
    Abstract: A semiconductor device includes at least one first fin, a first gate, a first gate dielectric layer, at least one second fin, a second gate electrode, and a second gate dielectric layer. The first fin has a first width. The first gate electrode crosses the first fin. The first gate dielectric layer is between the first fin and the first gate electrode and has a first thickness. The second fin has a second width greater than the first width. The second gate electrode crosses the second fin. The second gate dielectric layer is between the second fin and the second gate electrode and has a second thickness less than the first thickness.
    Type: Grant
    Filed: March 18, 2018
    Date of Patent: December 24, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventor: Jhon-Jhy Liaw
  • Patent number: 10516018
    Abstract: A super junction MOSFET device including a semiconductor substrate; a base region provided on a primary surface side of the semiconductor substrate and having impurities of a first conductivity type; a source region that includes a portion of a frontmost surface of the base region and has impurities of a second conductivity type; a gate electrode that penetrates through the base region; a source electrode that is provided on the base region and is electrically connected to the source region; and a front surface region that is provided on an entirety of the frontmost surface of the base region in a region differing from a region where the source region and the gate electrode are provided in the base region, is electrically connected to the source electrode provided on the base region, and has a lower impurity concentration of impurities of the second conductivity type than the source region.
    Type: Grant
    Filed: January 18, 2019
    Date of Patent: December 24, 2019
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Tohru Shirakawa, Tatsuya Naito, Shigemi Miyazawa
  • Patent number: 10490408
    Abstract: A method for manufacturing a semiconductor device comprises: a stacking process that stacks a p-type semiconductor layer of Group III nitride containing a p-type impurity on a first n-type semiconductor layer of Group III nitride containing an n-type impurity; a p-type ion implantation process that ion-implants the p-type impurity into the p-type semiconductor layer; and a heat treatment process that performs heat treatment to activate the ion-implanted p-type impurity. The p-type ion implantation process and the heat treatment process are performed such that the p-type impurity of the p-type semiconductor layer is diffused into the n-type semiconductor layer to form a first p-type impurity containing region in at least part of the first n-type semiconductor layer and below a region of the p-type semiconductor layer into which the ion implantation has been performed.
    Type: Grant
    Filed: March 8, 2018
    Date of Patent: November 26, 2019
    Assignee: TOYODA GOSEI CO., LTD.
    Inventors: Junya Nishii, Tohru Oka, Nariaki Tanaka
  • Patent number: 10483390
    Abstract: An insulated gate semiconductor device includes p+ gate bottom protection regions embedded in a drift layer at the bottoms of trenches that goes through n+ source regions and p-type base regions, and p+ base bottom embedded regions embedded in the drift layer below the base regions. The base bottom embedded regions have trapezoidal shapes due to a channeling phenomenon, and the bottom surfaces of the base bottom embedded regions are deeper than the bottom surfaces of the gate bottom protection regions.
    Type: Grant
    Filed: May 8, 2018
    Date of Patent: November 19, 2019
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventor: Keiji Okumura
  • Patent number: 10468430
    Abstract: According to one embodiment, a semiconductor storage device includes a substrate including an insulating region and a semiconductor region, an insulating film disposed on upper surfaces of the semiconductor region and the insulating region, a first conductive film disposed on an upper surface of the insulating film, and including a terrace region, and a first contact plug disposed on an upper surface of the terrace region of the first conductive film. The insulating region includes an upper surface positioned directly under the first contact plug. A lower surface of the insulating film is in contact with the upper surfaces of the semiconductor region and the insulating region, in the region directly under the terrace region.
    Type: Grant
    Filed: March 10, 2017
    Date of Patent: November 5, 2019
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Shinji Saito, Toshifumi Minami
  • Patent number: 10446685
    Abstract: III-V compound semiconductor devices, such transistors, may be formed in active regions of a III-V semiconductor material disposed over a silicon substrate. A heterojunction between an active region of III-V semiconductor and the substrate provides a diffusion barrier retarding diffusion of silicon from the substrate into III-V semiconductor material where the silicon might otherwise behave as an electrically active amphoteric contaminate. In some embodiments, the heterojunction is provided within a base portion of a sub-fin disposed between the substrate and a fin containing a transistor channel region. The heterojunction positioned closer to the substrate than active fin region ensures thermal diffusion of silicon atoms is contained away from the active region of a III-V finFET.
    Type: Grant
    Filed: September 25, 2015
    Date of Patent: October 15, 2019
    Assignee: Intel Corporation
    Inventors: Chandra S. Mohapatra, Matthew V. Metz, Harold W. Kennel, Gilbert Dewey, Willy Rachmady, Anand S. Murthy, Jack T. Kavalieros, Tahir Ghani
  • Patent number: 10418378
    Abstract: A nonvolatile semiconductor memory device, includes: a stacked structural unit including a plurality of insulating films alternately stacked with a plurality of electrode films in a first direction; a selection gate electrode stacked on the stacked structural unit in the first direction; an insulating layer stacked on the selection gate electrode in the first direction; a first semiconductor pillar piercing the stacked structural unit, the selection gate electrode, and the insulating layer in the first direction, a first cross section of the first semiconductor pillar having an annular configuration, the first cross section being cut in a plane orthogonal to the first direction; a first core unit buried in an inner side of the first semiconductor pillar, the first core unit being recessed from an upper face of the insulating layer; and a first conducting layer of the first semiconductor pillar provided on the first core unit to contact the first core unit.
    Type: Grant
    Filed: March 8, 2018
    Date of Patent: September 17, 2019
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Yoshiaki Fukuzumi, Ryota Katsumata, Masaru Kito, Masaru Kidoh, Hiroyasu Tanaka, Yosuke Komori, Megumi Ishiduki, Junya Matsunami, Tomoko Fujiwara, Hideaki Aochi, Ryouhei Kirisawa, Yoshimasa Mikajiri, Shigeto Oota
  • Patent number: 10403717
    Abstract: Semiconductor devices are provided. A semiconductor device includes a substrate. The semiconductor device includes an isolation layer defining active portions of the substrate that are spaced apart from each other in a direction. The semiconductor device includes an epitaxial layer on the active portions. The semiconductor device includes a metal silicide layer on the epitaxial layer. Moreover, the semiconductor device includes a contact structure that only partially overlaps the metal silicide layer on the epitaxial layer. Related methods of forming semiconductor devices are also provided.
    Type: Grant
    Filed: August 25, 2017
    Date of Patent: September 3, 2019
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Do-Sun Lee, Chang-Woo Sohn, Chul-Sung Kim, Shigenobu Maeda, Young-Moon Choi, Hyo-Seok Choi, Sang-Jin Hyun
  • Patent number: 10388774
    Abstract: A semiconductor device includes: a first electrode; a second electrode; a semiconductor region forming region between the first electrode and the second electrode; a first insulating film between the semiconductor region forming region and the second electrode; an actuation gate electrode in the semiconductor region forming region via a second insulating film; a dummy gate electrode, at a distance from the actuation gate electrode, on each of both sides of the actuation gate electrode in the semiconductor region forming region via a third insulating film; a trench contact, in a manner facing the actuation gate electrode, at a position in the third insulating film and between the dummy gate electrode and the semiconductor region forming region; and a contact electrode in the first insulating film and configured to electrically connect the trench contact to the second electrode.
    Type: Grant
    Filed: March 5, 2018
    Date of Patent: August 20, 2019
    Assignees: Kabushiki Kaisha Toshiba, Toshiba Electronic Devices & Storage Corporation
    Inventor: Hideki Sekiguchi
  • Patent number: 10381351
    Abstract: The present disclosure provides a transistor structure and a semiconductor layout structure. The transistor structure includes an active region, a buried gate structure disposed in the active region, a plurality of first dielectric layers disposed over sidewalls of the buried gate structure, and a source/drain region disposed in the active region at two opposite sides of the buried gate structure. In some embodiments, the buried gate structure includes a first portion and a second portion perpendicular to the first portion. In some embodiments, the buried gate structure is separated from the source/drain region by the first dielectric layers as viewed in a top view.
    Type: Grant
    Filed: January 25, 2018
    Date of Patent: August 13, 2019
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventors: Ching-Chia Huang, Tseng-Fu Lu, Wei-Ming Liao
  • Patent number: 10381436
    Abstract: To provide a semiconductor device having a structure capable of forming a superjunction with less thermal history, a semiconductor device is provided, the semiconductor device including a contact trench formed between two gate trenches, penetrating through a source region, and including its lower end arranged in a base region, and a second conductivity-type protruding portion formed protruding toward a lower side from the lower end of the base region in a region opposite to the lower end of the contact trench, wherein the depth from the upper end of the source region to a lower end of the protruding portion is 3 ?m or more, and a carrier concentration Nd in a first conductivity-type region adjacent to the protruding portion in a lateral direction perpendicular to a depth direction and a carrier concentration Na of the protruding portion satisfy a predetermined equation.
    Type: Grant
    Filed: May 17, 2018
    Date of Patent: August 13, 2019
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Isamu Sugai, Takeyoshi Nishimura
  • Patent number: 10347759
    Abstract: Techniques relate to forming a vertical field effect transistor (FET). One or more fins are formed on a bottom source or drain of a substrate, and one or more fins extend in a vertical direction. Gate material is formed to be positioned on sides of the one or more fins. Gate encapsulation material is formed on sides of the gate material to form a trench, such that top portions of the one or more fins are exposed in the trench. A top source or drain is formed on top of the one or more fins such that the top source or drain is laterally confined by the trench in a lateral direction that is parallel to the one or more fins.
    Type: Grant
    Filed: April 27, 2018
    Date of Patent: July 9, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Brent A. Anderson, Huiming Bu, Fee Li Lie, Edward J. Nowak, Junli Wang
  • Patent number: 10340270
    Abstract: An integrated circuit is provided. The integrated circuit includes a substrate, a first FinFET device supported by the substrate, the first FinFET device having a first fin with a non-tiered fin profile, and a second FinFET supported by the substrate, the second FinFET having a second fin with a tiered fin profile.
    Type: Grant
    Filed: February 24, 2017
    Date of Patent: July 2, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company
    Inventor: Jhon-Jhy Liaw
  • Patent number: 10332809
    Abstract: A semiconductor structure is provided that includes a pFET gate-all-around nanosheet structure and an nFET gate-all-around nanosheet structure integrated together on the same substrate. The pFET gate-all-around nanosheet structure contains a nickel monosilicide gate electrode layer that does not introduce strain into each suspended semiconductor channel material nanosheet of a first vertical stack of suspended semiconductor channel material nanosheets. The nFET gate-all-around nanosheet structure contains a Ni3Si gate electrode layer that introduces strain into each suspended semiconductor channel material nanosheet of a second vertical stack of suspended semiconductor channel material nanosheets.
    Type: Grant
    Filed: June 21, 2018
    Date of Patent: June 25, 2019
    Assignee: International Business Machines Corporation
    Inventors: Takashi Ando, Jingyun Zhang, Choonghyun Lee, Pouya Hashemi, Alexander Reznicek
  • Patent number: 10332938
    Abstract: A display panel includes a base substrate, an active pattern on the base substrate, and including a first active pattern of a first transistor, and a second active pattern of a second transistor, a gate pattern on the base substrate, and including a first gate electrode that overlaps the first active pattern, and a second gate electrode that overlaps the second active pattern, an insulation layer covering the gate pattern, a first conductive pattern on the insulation layer, and electrically connected to the first gate electrode through a first contact hole formed through the insulation layer, and a second conductive pattern electrically connected to the second gate electrode through a second contact hole formed through the insulation layer, wherein each of the first contact hole and the second contact hole overlaps, partially overlaps, or does not overlap each of the first active pattern and the second active pattern, and wherein a first overlapped area at which the first active pattern overlaps the first con
    Type: Grant
    Filed: March 10, 2017
    Date of Patent: June 25, 2019
    Assignee: Samsung Display Co., Ltd.
    Inventors: Jin-Tae Jeong, Yang-Wan Kim
  • Patent number: 10319737
    Abstract: The semiconductor device includes a stacked structure having alternately stacked conductive patterns and interlayer insulating patterns, a through-hole passing through the stacked structure, a channel pattern formed in the through-hole and protruding from an inside of the through hole over the through-hole, and a capping conductive pattern formed to be in contact with the protruded channel pattern and have a width greater than the through-hole.
    Type: Grant
    Filed: November 16, 2017
    Date of Patent: June 11, 2019
    Assignee: SK hynix Inc.
    Inventor: Jong Man Kim
  • Patent number: 10319724
    Abstract: Some embodiments include a memory cell having a first transistor supported by a semiconductor base, and having second and third transistors above the first transistor and vertically stacked one atop the other. Some embodiments include a memory cell having first, second and third transistors. The third transistor is above the second transistor, and the second and third transistors are above the first transistor. The first transistor has first and second source/drain regions, the second transistor has third and fourth source/drain regions, and the third transistor has fifth and sixth source/drain regions. A read bitline is coupled with the sixth source/drain region. A write bitline is coupled with the first source/drain region. A write wordline includes a gate of the first transistor. A read wordline includes a gate of the third transistor. A capacitor is coupled with the second source/drain region and with a gate of the second transistor.
    Type: Grant
    Filed: July 12, 2018
    Date of Patent: June 11, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Suraj J. Mathew, Kris K. Brown, Raghunath Singanamalla, Vinay Nair, Fawad Ahmed, Fatma Arzum Simsek-Ege, Diem Thy N. Tran
  • Patent number: 10312156
    Abstract: A vertical fin field effect transistor (V-FinFET) is provided as follows. A substrate has a lower source/drain (S/D). A fin structure extends vertically from an upper surface of the lower S/D. The fin structure includes a sidewall having an upper sidewall portion, a lower sidewall portion and a center sidewall portion positioned therebetween. An upper S/D is disposed on an upper surface of the fin structure. An upper spacer is disposed on the upper sidewall portion. A lower spacer is disposed on the lower sidewall portion. A stacked structure including a gate oxide layer and a first gate electrode is disposed on an upper surface of the lower spacer, the center sidewall portion and a lower surface of the upper spacer. A second gate electrode is disposed on the first gate electrode.
    Type: Grant
    Filed: December 12, 2017
    Date of Patent: June 4, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Soo Yeon Jeong, Myung Gil Kang
  • Patent number: 10312380
    Abstract: A semiconductor diode includes a semiconductor body, having a first main area formed from an inner area, on which a first contact layer is arranged, and from an edge area, a current path from the first contact layer to a second contact layer arranged on a second main area situated opposite the first main area, wherein the semiconductor diode, by virtue of the configuration of the first contact layer or of the semiconductor body, is formed such that upon current flow, such current flows through a current path having the greatest heating per unit volume, and which proceeds from a further partial area of the inner area, wherein the further partial area is arranged on the other side of a boundary of an inner partial area of the inner area, said inner partial area preferably being arranged centrally, with respect to an outer partial area adjoining said inner partial area.
    Type: Grant
    Filed: January 10, 2018
    Date of Patent: June 4, 2019
    Assignee: SEMIKRON ELEKTRONIK GmbH & CO. KG
    Inventors: Christian Göbl, Boris Rosensaft, Uwe Schilling, Wolfgang-Michael Schulz, Sven Teuber
  • Patent number: 10297611
    Abstract: A transistor comprises channel material having first and second opposing sides. A gate is on the first side of the channel material and a gate insulator is between the gate and the channel material. A first insulating material has first and second opposing sides, with the first side being adjacent the second side of the channel material. A second insulating material of different composition from that of the first insulating material is adjacent the second side of the first insulating material. The second insulating material has at least one of (a), (b), and (c), where, (a): lower oxygen diffusivity than the first material, (b): net positive charge, and (c): at least two times greater shear strength than the first material. In some embodiments, an array of elevationally-extending strings of memory cells comprises such transistors. Other embodiments, including method, are disclosed.
    Type: Grant
    Filed: February 23, 2018
    Date of Patent: May 21, 2019
    Assignee: Micron Technology, Inc.
    Inventors: David H. Wells, Luan C. Tran, Jie Li, Anish A. Khandekar, Kunal Shrotri
  • Patent number: 10290707
    Abstract: A semiconductor device includes: a drain region; a drift layer made of a first conductivity type semiconductor with lower impurity concentration than the drain region; a base region made of a second conductivity type semiconductor; a source region made of the first conductivity type semiconductor with higher concentration; a contact region made of the second conductivity type semiconductor with higher concentration; a trench structure having a first gate insulation film and a first gate electrode arranged at an opening side of the trench and to be deeper than the base region, and a bottom part insulation film; a source electrode electrically connected to the source and contact regions; and a drain electrode at a rear side of the drain region. The drain is arranged to be deeper than the base region. The first gate insulation film is made of higher dielectric insulation material than the bottom part insulation film.
    Type: Grant
    Filed: March 10, 2016
    Date of Patent: May 14, 2019
    Assignee: TOYOTA JIDOSHA KABUSHIKI KAISHA
    Inventors: Tomohiro Mimura, Takashi Kanemura, Masahiro Sugimoto, Narumasa Soejima
  • Patent number: 10290547
    Abstract: A method of manufacturing a semiconductor device includes forming a first layer of a conductive material in gate spaces created by removing portions of a dummy gate structure. The first layer further includes a top layer on an entire structure formed on a fin structure, and a gate space for a short channel gate and a gate space for a long channel gate. A first portion of the top layer is removed to leave a hard mask layer over a long channel gate region. The hard mask layer and a portion of heights of the conductive material in the gate spaces are removed to form a first structure. A second layer of the conductive material is formed over the first structure. Portions of the second layer are removed to create a recessed conductive portion for the short channel gate and a recessed conductive portion for the long channel gate.
    Type: Grant
    Filed: November 27, 2017
    Date of Patent: May 14, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chia-Ching Tsai, Yi-Wei Chiu, Li-Te Hsu
  • Patent number: 10283521
    Abstract: Disclosed are a semiconductor device and a manufacturing method thereof. The semiconductor device includes source select lines, word lines, drain select lines, and a bit line stacked on a substrate in which a first cell string region and a second cell string region are defined; channel layers and memory layers vertically passing through the source select lines, the word lines, and the drain select lines in each of the first cell string region and the second cell string region; and a common source line vertically passing through the source select lines, the word lines, and the drain select lines at centers of the first cell string region and the second cell string region, and extended to a lower side of the source select lines.
    Type: Grant
    Filed: June 23, 2017
    Date of Patent: May 7, 2019
    Assignee: SK hynix Inc.
    Inventor: Min Sik Jang
  • Patent number: 10276392
    Abstract: First, second, and third trenches are formed in a layer over a substrate. The third trench is substantially wider than the first and second trenches. The first, second, and third trenches are partially filled with a first conductive material. A first anti-reflective material is coated over the first, second, and third trenches. The first anti-reflective material has a first surface topography variation. A first etch-back process is performed to partially remove the first anti-reflective material. Thereafter, a second anti-reflective material is coated over the first anti-reflective material. The second anti-reflective material has a second surface topography variation that is smaller than the first surface topography variation. A second etch-back process is performed to at least partially remove the second anti-reflective material in the first and second trenches. Thereafter, the first conductive material is partially removed in the first and second trenches.
    Type: Grant
    Filed: July 6, 2017
    Date of Patent: April 30, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Jin-Dah Chen, Ming-Feng Shieh, Han-Wei Wu, Yu-Hsien Lin, Po-Chun Liu, Stan Chen
  • Patent number: 10269986
    Abstract: A diode includes a first plurality of combo fins having lengthwise directions parallel to a first direction, wherein the first plurality of combo fins comprises portions of a first conductivity type. The diodes further includes a second plurality of combo fins having lengthwise directions parallel to the first direction, wherein the second plurality of combo fins includes portions of a second conductivity type opposite the first conductivity type. An isolation region is located between the first plurality of combo fins and the second plurality of combo fins. The first and the second plurality of combo fins form a cathode and an anode of the diode. The diode is configured to have a current flowing in a second direction perpendicular to the first direction, with the current flowing between the anode and the cathode.
    Type: Grant
    Filed: March 18, 2016
    Date of Patent: April 23, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Sun-Jay Chang, Ming-Hsiang Song, Jen-Chou Tseng, Wun-Jie Lin, Bo-Ting Chen
  • Patent number: 10269955
    Abstract: A vertical FET includes a silicon carbide substrate having a top surface and a bottom surface opposite the top surface; a drain/collector contact on the bottom surface of the silicon carbide substrate; and an epitaxial structure on the top surface of the silicon carbide substrate having formed therein a first source/emitter implant. A gate dielectric is provided on a portion of the epitaxial structure. First source/emitter contact segments are spaced apart from each other and on the first source/emitter implant. A first elongated gate contact and a second elongated gate contact are on the gate dielectric and positioned such that the first source/emitter implant is below and between the first elongated gate contact and the second elongated gate contact. Inter-gate plates extend from at least one of the first elongated gate contact and the second elongated gate contact into spaces formed between the first source/emitter contact segments.
    Type: Grant
    Filed: January 17, 2017
    Date of Patent: April 23, 2019
    Assignee: Cree, Inc.
    Inventors: Sei-Hyung Ryu, Marcelo Schupbach, Adam Barkley, Scott Allen