Plural Gate Electrodes Or Grid Shaped Gate Electrode Patents (Class 257/331)
  • Patent number: 11626498
    Abstract: A semiconductor memory device that may include a substrate, an array of memory cells arranged in rows and columns, bit lines and word lines. The memory cells each may include a pillar-shaped active region extending vertically, which includes source/drain regions at upper and lower ends respectively and a channel region between the source/drain regions. The channel region may include a single-crystalline semiconductor material. The memory cells each may further include a gate stack formed around a periphery of the channel region. Each of the bit lines is located below a corresponding column, and electrically connected to the lower source/drain regions of the respective memory cells in the corresponding column. Each of the word lines is electrically connected to the gate stacks of the respective memory cells in a corresponding row.
    Type: Grant
    Filed: September 6, 2018
    Date of Patent: April 11, 2023
    Assignee: INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES
    Inventor: Huilong Zhu
  • Patent number: 11626477
    Abstract: A semiconductor component includes: gate structures extending from a first surface into an SiC semiconductor body; a drift zone of a first conductivity type formed in the SiC semiconductor body; first mesas and second mesas arranged between the gate structures in the SiC semiconductor body; body areas of a second conductivity type arranged in the first mesas and the second mesas, the body areas each adjoining a first side wall of one of the gate structures; first shielding areas of the second conductivity type adjoining a second side wall of one of the gate structures; second shielding areas of the second conductivity type adjoining the body areas in the second mesas; and diode areas of the conductivity type of the drift zone, the diode areas forming Schottky contacts with a load electrode between the first shielding areas and the second shielding areas.
    Type: Grant
    Filed: July 14, 2021
    Date of Patent: April 11, 2023
    Assignee: Infineon Technologies AG
    Inventors: Ralf Siemieniec, Thomas Aichinger, Thomas Basler, Wolfgang Bergner, Rudolf Elpelt, Romain Esteve, Michael Hell, Daniel Kueck, Caspar Leendertz, Dethard Peters, Hans-Joachim Schulze
  • Patent number: 11616138
    Abstract: A field-effect transistor includes an n-type semiconductor layer that includes a Ga2O3-based single crystal and a plurality of trenches opening on one surface, a gate electrode buried in each of the plurality of trenches, a source electrode connected to a mesa-shaped region between adjacent trenches in the n-type semiconductor layer, and a drain electrode directly or indirectly connected to the n-type semiconductor layer on an opposite side to the source electrode.
    Type: Grant
    Filed: September 26, 2018
    Date of Patent: March 28, 2023
    Assignees: Tamura Corporation, Novel Crystal Technology, Inc.
    Inventor: Kohei Sasaki
  • Patent number: 11605733
    Abstract: The present disclosure provides a method of manufacturing a semiconductor device. The method includes steps of providing a patterned mask having a plurality of openings on a substrate; etching the substrate through the openings to form an etched substrate and a trench in the etched substrate, wherein the etched substrate comprises a protrusion; introducing dopants having a first conductivity type in the etched substrate and on either side of the trench to form a plurality of first impurity regions; forming an isolation film in the trench; and depositing a conductive material on the isolation film.
    Type: Grant
    Filed: January 5, 2022
    Date of Patent: March 14, 2023
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventor: Tsung-Yu Tsai
  • Patent number: 11581399
    Abstract: Methods and semiconductor circuits are described in which a polysilicon resistor body is formed over a semiconductor substrate. A first dopant species is implanted into the polysilicon resistor body at a first angle about parallel to a surface normal of a topmost surface of the polysilicon resistor body. A second dopant species is implanted into the polysilicon resistor body at a second angle greater than about 10° relative to the surface normal. The combination of implants reduces the different between the temperature coefficient (tempco) of resistance of narrow resistors relative to the tempco of wide resistors, and brings the tempco of the resistors closer to a preferred value of zero.
    Type: Grant
    Filed: June 30, 2020
    Date of Patent: February 14, 2023
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventor: Mahalingam Nandakumar
  • Patent number: 11563080
    Abstract: A semiconductor device includes a semiconductor layer structure of a wide band-gap semiconductor material. The semiconductor layer structure includes a drift region having a first conductivity type and a well region having a second conductivity type. A plurality of segmented gate trenches extend in a first direction in the semiconductor layer structure. The segmented gate trenches include respective gate trench segments that are spaced apart from each other in the first direction with intervening regions of the semiconductor layer structure therebetween. Related devices and fabrication methods are also discussed.
    Type: Grant
    Filed: April 30, 2020
    Date of Patent: January 24, 2023
    Assignee: Wolfspeed, Inc.
    Inventor: Daniel Jenner Lichtenwalner
  • Patent number: 11469136
    Abstract: A technique to make silicon oxide regions from porous silicon and related semiconductor structures is disclosed. The porous silicon is made in situ by anodizing P doped silicon regions. Thus, the shape and profile of the oxide regions may be controlled by controlling the shape and profile of the P doped silicon regions.
    Type: Grant
    Filed: August 24, 2020
    Date of Patent: October 11, 2022
    Assignee: STMICROELECTRONICS S.r.l.
    Inventors: Simone Dario Mariani, Fabrizio Fausto Renzo Toia, Marco Sambi, Davide Giuseppe Patti, Marco Morelli, Giuseppe Barillaro
  • Patent number: 11469319
    Abstract: The present disclosure provides a semiconductor device and a method of manufacturing the semiconductor device. The semiconductor device includes a substrate, a word line, a plurality of first impurity regions, a second impurity region, and an isolation film. The word line is W-shaped, is disposed in the substrate, and includes a base and a pair of legs connected to the base. The first impurity regions are disposed in the substrate and on either side of the word line. The second impurity region is disposed between the legs of the word line. The isolation film is disposed in the substrate, wherein the word line is surrounded by the isolation film.
    Type: Grant
    Filed: April 10, 2020
    Date of Patent: October 11, 2022
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventor: Tsung-Yu Tsai
  • Patent number: 11450763
    Abstract: Provided is an IGBT power device. The device includes: a p-type collector region; an n-type drift region located above the p-type collector region; multiple first grooves, where a second groove is provided below each of the multiple first grooves; a gate structure located in the first groove and the second groove; a p-type body region located between two adjacent first grooves; an n-type emitter region located in the p-type body region; and an n-type hole charge blocking region located between two adjacent second grooves.
    Type: Grant
    Filed: January 30, 2019
    Date of Patent: September 20, 2022
    Assignee: Suzhou Oriental Semiconductor Co., Ltd.
    Inventors: Wei Liu, Lei Liu, Zhendong Mao, Yuanlin Yuan
  • Patent number: 11444167
    Abstract: A method of manufacturing a trench type semiconductor device includes the following steps. First, an epitaxial layer is formed on a substrate, then a trench is formed in the epitaxial layer, and a gate structure is formed in the trench. The gate structure includes an upper gate and a lower gate, and an intermediate insulating portion, and the intermediate insulating portion is located in and above the upper gate.
    Type: Grant
    Filed: November 18, 2020
    Date of Patent: September 13, 2022
    Assignee: Advanced Power Electronics Corp.
    Inventor: Jau-Yan Lin
  • Patent number: 11430793
    Abstract: A microelectronic device comprises a first pillar of a semiconductive material, a second pillar of the semiconductive material adjacent to the first pillar of the semiconductive material, an active word line extending between the first pillar and the second pillar, and a passing word line extending on a side of the second pillar opposite the active word line, the passing word line extending into an isolation region within the semiconductive material, the isolation region comprising a lower portion and an upper portion having a substantially circular cross-sectional shape and a larger lateral dimension than the lower portion. Related microelectronic devices, electronic systems, and methods are also described.
    Type: Grant
    Filed: June 11, 2020
    Date of Patent: August 30, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Deepak Chandra Pandey, Venkata Naveen Kumar Neelapala, Haitao Liu
  • Patent number: 11404550
    Abstract: According to one embodiment, a semiconductor device includes first, and second conductive members, first, second, and third semiconductor regions, and an insulating part. A direction from the first conductive member toward the second conductive member is along a first direction. The first semiconductor region includes first and second partial regions. A second direction from the first partial region toward the second partial region crosses the first direction. The first conductive member is between the first partial region and the second conductive member. A direction from the second partial region toward the second semiconductor region is along the first direction. A direction from the second conductive member toward the second semiconductor region is along the second direction. The third semiconductor region is between the second partial region and the second semiconductor region. The insulating part includes a first insulating region, a second insulating region, and a third insulating region.
    Type: Grant
    Filed: September 10, 2020
    Date of Patent: August 2, 2022
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Tomoaki Inokuchi, Hiro Gangi, Yusuke Kobayashi, Kentaro Ikeda, Tatsunori Sakano, Ryosuke Iijima
  • Patent number: 11342425
    Abstract: A semiconductor device includes: a semiconductor substrate; a plurality of needle-shaped field plate trenches and a plurality of needle-shaped gate trenches formed in the semiconductor substrate and interspersed with one another; a first dielectric layer above the semiconductor substrate; a gate interconnect structure including electrically conductive lines separated from the semiconductor substrate by the first dielectric layer and first conductive vias extending through the first dielectric layer to connect the electrically conductive lines to gate electrodes in the needle-shaped gate trenches; and a field plate interconnect structure electrically isolated from the gate interconnect structure and including second conductive vias that extend through the first dielectric layer and connect to field plates in the needle-shaped field plate trenches.
    Type: Grant
    Filed: September 23, 2020
    Date of Patent: May 24, 2022
    Assignee: Infineon Technologies Austria AG
    Inventor: Ling Ma
  • Patent number: 11342348
    Abstract: This non-volatile semiconductor memory device includes a memory cell array including NAND cell units formed in a first direction vertical to a surface of a semiconductor substrate. A local source line is electrically coupled to one end of the NAND cell unit formed on the surface of the substrate. The memory cell array includes: a laminated body where plural conductive films, which are to be control gate lines of memory cells or selection gate lines of selection transistors, are laminated sandwiching interlayer insulating films; a semiconductor layer that extends in the first direction; and an electric charge accumulating layer sandwiched between: the semiconductor layer and the conductive film. The local source line includes a silicide layer. The electric charge accumulating layer is continuously formed from the memory cell array to cover a peripheral area of the silicide layer.
    Type: Grant
    Filed: July 17, 2020
    Date of Patent: May 24, 2022
    Assignee: KIOXIA CORPORATION
    Inventors: Yoshihiro Akutsu, Ryota Katsumata
  • Patent number: 11251266
    Abstract: A power semiconductor device includes a semiconductor body having a drift region of a first conductivity type inside an active region. An edge termination region includes: a guard region of a second conductivity type at a front side of the semiconductor body and surrounding the active region; and a field plate trench structure extending vertically into the body from the front side and at least partially filled with a conductive material that is electrically connected with the guard region and insulated from the body external of the guard region. A first portion of the field plate trench structure at least partially extends into the guard region and is at least partially arranged below a metal layer arranged at the front side. A second portion of the field plate trench structure extends outside of the guard region and surrounds the active area, the metal layer not extending above the second portion.
    Type: Grant
    Filed: February 14, 2020
    Date of Patent: February 15, 2022
    Assignee: Infineon Technologies AG
    Inventors: Philip Christoph Brandt, Manfred Pfaffenlehner, Frank Dieter Pfirsch, Francisco Javier Santos Rodriguez, Steffen Schmidt, Frank Umbach
  • Patent number: 11245063
    Abstract: A semiconductor device includes a semiconductor substrate, a polysilicon layer fixed to the semiconductor substrate, and a silicon nitride layer in contact with the polysilicon layer, wherein the polysilicon layer includes an n-type layer and a p-type layer in contact with the n-type layer; a semiconductor device manufacturing method includes forming the polysilicon layer covering at least one hydrogen-containing layer, and heating the polysilicon layer and the hydrogen-containing layer.
    Type: Grant
    Filed: February 13, 2019
    Date of Patent: February 8, 2022
    Assignee: DENSO CORPORATION
    Inventors: Kensuke Nagata, Katsutoshi Narita
  • Patent number: 11239118
    Abstract: A method for fabricating a semiconductor device includes forming a trench in a substrate, forming a gate dielectric layer on a surface of the trench, forming a lower gate, which partially fills the trench, over the gate dielectric layer, forming a low work function layer over the lower gate, forming a spacer over the low work function layer, etching the low work function layer to be self-aligned with the spacer in order to form vertical gate on both upper edges of the lower gate, and forming an upper gate over the lower gate between inner sidewalls of the vertical gate.
    Type: Grant
    Filed: April 20, 2020
    Date of Patent: February 1, 2022
    Assignee: SK hynix Inc.
    Inventors: Dong-Soo Kim, Se-Han Kwon
  • Patent number: 11227916
    Abstract: According to an embodiment, a semiconductor device 1 includes a semiconductor substrate 50 including an upper surface, a trench electrode 22 provided inside a trench 20 formed on the upper surface, and a trench insulating film 21 provided between the trench electrode 22 and the semiconductor substrate 50. The semiconductor substrate 50 includes a first semiconductor layer of a first conductivity type, a lower end of the trench electrode 22 reaching the first semiconductor layer, a deep layer 19 of a second conductivity type partially provided on the first semiconductor layer in contact with the trench insulating film 21, a second semiconductor layer of the second conductivity type provided on the first semiconductor layer and on the deep layer 19 in contact with the trench insulating film 21, and a third semiconductor layer of the first conductivity type provided on the second semiconductor layer above the deep layer 19.
    Type: Grant
    Filed: March 23, 2018
    Date of Patent: January 18, 2022
    Assignee: Renesas Electronics Corporation
    Inventor: Ryo Kanda
  • Patent number: 11222966
    Abstract: A semiconductor device includes first and second electrodes. A first-type layer is between the first and second electrodes. A pair of first gate electrodes is between the first and second electrodes and each is surrounded by a gate insulating film. Second gate electrodes are disposed between the pair of first gate electrodes. A second-type layer is on the first-type layer in a first region between a first gate electrode and one of the second gate electrodes. Another first-type layer is on the second-type layer. This other first-type layer is directly adjacent to the gate insulating film. Another second-type layer is on the other second-type layer. A width of the first-type layer between adjacent second gate electrodes is less than a length of the first-type layer in the region between adjacent second gate electrodes.
    Type: Grant
    Filed: February 26, 2020
    Date of Patent: January 11, 2022
    Assignees: KABUSHIKI KAISHA TOSHIBA, TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION
    Inventors: Keiko Kawamura, Tomoko Matsudai, Yoko Iwakaji
  • Patent number: 11217675
    Abstract: A semiconductor device includes a trench in a semiconductor material having a device section and a termination section. A gate structure is located in the trench. With some embodiments, the transverse cross-sectional width of the termination section is wider than the transverse cross-sectional width of the device section.
    Type: Grant
    Filed: March 31, 2020
    Date of Patent: January 4, 2022
    Assignee: NXP USA, INC.
    Inventors: Saumitra Raj Mehrotra, Bernhard Grote, Ljubo Radic
  • Patent number: 11205663
    Abstract: A vertical memory device includes conductive lines on a substrate, first and second semiconductor patterns, first and second pads, first and second electrodes, a third electrode, and a first division pattern. The conductive lines are stacked in a vertical direction and extend in a first direction. The first and second semiconductor patterns extend through the conductive lines in the vertical direction. The first and second pads are formed on the first and second semiconductor patterns. The first and second electrodes are electrically connected to the first and second pads. The third electrode is electrically connected to a first conductive line of the conductive lines. The first division pattern extends in a second direction, and extends through and divides the first conductive line. In a plan view, the first and second semiconductor patterns and the first conductive line are disposed at one side of the first division pattern.
    Type: Grant
    Filed: September 11, 2020
    Date of Patent: December 21, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventor: Jang-Gn Yun
  • Patent number: 11189725
    Abstract: Semiconductor devices and methods of forming the same include forming a restraint structure over a channel fin, having an opening that is smaller than a top surface of the channel fin. A top semiconductor structure is grown from the top surface of the channel fin, with lateral growth of the semiconductor structure being limited by the restraint structure.
    Type: Grant
    Filed: January 7, 2020
    Date of Patent: November 30, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Heng Wu, Ruilong Xie, Lan Yu, Alexander Reznicek, Junli Wang
  • Patent number: 11164968
    Abstract: According to one embodiment, a semiconductor device includes first and second electrodes, first, second and third semiconductor regions, a first conductive portion, a gate electrode, and a second insulating portion. The first and second semiconductor regions are provided on the first semiconductor region. The third semiconductor regions are selectively provided respectively on the second semiconductor regions. The first conductive portion is provided inside the first semiconductor region with a first insulating portion interposed. The gate electrode is provided on the first conductive portion and the first insulating portion and separated from the first conductive portion. The gate electrode includes first and second electrode parts. The second insulating portion is provided between the first and second electrode parts. The second insulating portion includes first and second insulating parts. The second electrode is provided on the second and third semiconductor regions.
    Type: Grant
    Filed: September 4, 2019
    Date of Patent: November 2, 2021
    Assignees: Kabushiki Kaisha Toshiba, Toshiba Electronic Devices & Storage Corporation
    Inventors: Saya Shimomura, Tetsuya Ohno, Hiroaki Katou
  • Patent number: 11158733
    Abstract: A semiconductor device including a semiconductor substrate; a trench formed in a front surface of the semiconductor substrate; a gate conducting portion formed within the gate trench; and a first region formed adjacent to the trench in the front surface of the semiconductor substrate and having a higher impurity concentration than the semiconductor substrate. A shoulder portion is provided on a side wall of the gate trench between the top end of the gate conducting portion and the front surface of the semiconductor substrate and has an average slope, relative to a depth direction of the semiconductor substrate, that is greater than a slope of the side wall of the gate trench at a position opposite the top end of the gate conducting portion, and a portion of the first region that contacts the gate trench is formed as a deepest portion thereof.
    Type: Grant
    Filed: November 26, 2019
    Date of Patent: October 26, 2021
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventor: Tatsuya Naito
  • Patent number: 11152488
    Abstract: Semiconductor device and the manufacturing method thereof are disclosed herein. An exemplary semiconductor device comprises a nanostructure disposed over a substrate, wherein the nanostructure includes a plurality of semiconductor layers separated vertically from each other and a dummy pattern layer including dielectric material disposed over and separated vertically from a top semiconductor layer of the plurality of semiconductor layers. The exemplary semiconductor device also comprises a gate structure disposed over a channel region, wherein the gate structure wraps around each of the plurality of semiconductor layers and the dummy pattern layer of the nanostructure.
    Type: Grant
    Filed: August 21, 2019
    Date of Patent: October 19, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Ta-Chun Lin, Kuo-Hua Pan, Jhon Jhy Liaw
  • Patent number: 11145511
    Abstract: A power semiconductor device and a method of fabricating such a power semiconductor device are disclosed. In the method, spacers are formed, which cover sidewalls of a source polysilicon layer and reside on trench portions around the source polysilicon layer. As such, a contact is allowed to be directly formed above the source polysilicon layer, eliminating the need for a special photomask for defining a connection between the contact and the gate electrode, reducing the number of required steps, lowering the process cost and avoiding the risk of contact of the subsequently-formed contact above the source polysilicon layer with a gate polysilicon layer. With the spacers protecting a second oxide layer, during the subsequent formation of a source electrode, the implantation of some n-type ions into the second oxide layer, which may degrade the properties of the second oxide layer, is prevented.
    Type: Grant
    Filed: October 13, 2020
    Date of Patent: October 12, 2021
    Assignee: Shanghai Huahong Grace Semiconductor Manufacturing Corporation
    Inventor: Xue Gao
  • Patent number: 11145757
    Abstract: Integrated circuit devices and methods of forming the same are provided. Integrated circuit devices may include a vertical field-effect transistor (VFET) that includes a bottom source/drain region in a substrate, a channel region on the bottom source/drain region, a top source/drain region on the channel region, and a gate structure on a side of the channel region. The channel region may have a cross-shaped upper surface.
    Type: Grant
    Filed: December 13, 2019
    Date of Patent: October 12, 2021
    Inventors: Young Chai Jung, Seon Bae Kim, Seung Hyun Song
  • Patent number: 11127731
    Abstract: An electronic device can include a transistor having a gate electrode, a first portion, and a second portion, wherein along the gate electrode, the first portion of the transistor has a first gate-to-drain capacitance and a first gate-to-source capacitance, the second portion of the transistor has a second gate-to-drain capacitance and a second gate-to-source capacitance, and a ratio of the first gate-to-drain capacitance to the first gate-to-source capacitance is less than a ratio of the second gate-to-drain capacitance to the second gate-to-source capacitance.
    Type: Grant
    Filed: April 13, 2020
    Date of Patent: September 21, 2021
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Balaji Padmanabhan, Kirk K. Huang, Prasad Venkatraman, Emily M. Linehan, Zia Hossain
  • Patent number: 11114559
    Abstract: A semiconductor device includes a first group of trench-like structures and a second group of trench-like structures. Each trench-like structure in the first group includes a gate electrode contacted to gate metal and a source electrode contacted to source metal. Each of the trench-like structures in the second group is disabled. The second group of disabled trench-like structures is interleaved with the first group of trench-like structures.
    Type: Grant
    Filed: May 18, 2012
    Date of Patent: September 7, 2021
    Assignee: Vishay-Siliconix, LLC
    Inventors: Chanho Park, Kyle Terrill
  • Patent number: 11107817
    Abstract: Some embodiments include an integrated assembly having a first semiconductor material between two regions of a second semiconductor material. The second semiconductor material is a different composition than the first semiconductor material. Hydrogen is diffused within the first and second semiconductor materials. The conductivity of the second semiconductor material increases in response to the hydrogen diffused therein to thereby create a structure having the second semiconductor material as source/drain regions, and having the first semiconductor material as a channel region between the source/drain regions. A transistor gate is adjacent the channel region and is configured to induce an electric field within the channel region. Some embodiments include methods of forming integrated assemblies.
    Type: Grant
    Filed: March 11, 2019
    Date of Patent: August 31, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Kamal M. Karda, Yi Fang Lee, Haitao Liu, Durai Vishak Nirmal Ramaswamy, Ramanathan Gandhi, Karthik Sarpatwari, Scott E. Sills, Sameer Chhajed
  • Patent number: 11101343
    Abstract: A semiconductor component has a gate structure that extends from a first surface into an SiC semiconductor body. A body area in the SiC semiconductor body adjoins a first side wall of the gate structure. A first shielding area and a second shielding area of the conductivity type of the body area have at least twice as high a level of doping as the body area. A diode area forms a Schottky contact with a load electrode between the first shielding area and the second shielding area.
    Type: Grant
    Filed: May 6, 2019
    Date of Patent: August 24, 2021
    Assignee: Infineon Technologies AG
    Inventors: Ralf Siemieniec, Thomas Aichinger, Thomas Basler, Wolfgang Bergner, Rudolf Elpelt, Romain Esteve, Michael Hell, Daniel Kueck, Caspar Leendertz, Dethard Peters, Hans-Joachim Schulze
  • Patent number: 11101360
    Abstract: A semiconductor device includes a channel region, a source/drain region adjacent to the channel region, and a source/drain epitaxial layer. The source/drain epitaxial layer includes a first epitaxial layer epitaxially formed on the source/drain region, a second epitaxial layer epitaxially formed on the first epitaxial layer and a third epitaxial layer epitaxially formed on the second epitaxial layer. The first epitaxial layer includes at least one selected from the group consisting of a SiAs layer, a SiC layer and a SiCP layer.
    Type: Grant
    Filed: October 1, 2019
    Date of Patent: August 24, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Cheng-Yi Peng, Wen-Hsing Hsieh, Wen-Yuan Chen, Jon-Hsu Ho, Song-Bor Lee, Bor-Zen Tien
  • Patent number: 11101273
    Abstract: A method of manufacturing a semiconductor structure includes: receiving a substrate having an active region and a non-active region adjacent to the active region; forming an etch stop layer over the non-active region of the substrate, in which the etch stop layer is oxide-free; forming an isolation over the etch stop layer; removing a portion of the active region and a portion of the isolation to form a first trench in the active region and a second trench over the etch stop layer, respectively, in which a thickness of the etch stop layer beneath the second trench is greater than a depth difference between the first trench and the second trench; forming a dielectric layer in the first trench; and filling a conductive material on the dielectric layer in the first trench and in the second trench. A semiconductor structure is also provided.
    Type: Grant
    Filed: February 25, 2020
    Date of Patent: August 24, 2021
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventors: Ching-Chia Huang, Wei-Ming Liao
  • Patent number: 11088283
    Abstract: The present application provides a thin film transistor, a method of fabricating a thin film transistor and an array substrate. The thin film transistor includes: a gate electrode on a substrate and having first and second side surfaces facing each other; and an active layer between the first side surface and the second side surface of the gate electrode and having a third side surface and a fourth side surface. The third side surface of the active layer and the first side surface of the gate electrode face and are spaced apart from each other, the fourth side surface of the active layer and the second side surface of the gate electrode face and are spaced apart from each other, and at least one portion of the gate electrode is in the same range as at least one portion of the active layer in a height direction.
    Type: Grant
    Filed: August 27, 2018
    Date of Patent: August 10, 2021
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Guoying Wang, Zhen Song, Hongda Sun
  • Patent number: 11081554
    Abstract: A semiconductor device structure includes a region of semiconductor material comprising a first conductivity type, an active region, and a termination region. A first active trench structure is disposed in the active region, and a second active trench structure is disposed in the active region and laterally separated from the first active trench by an active mesa region having a first width. A first termination trench structure is disposed in the termination region and separated from the second active trench by a transition mesa region having a second width and a higher carrier charge than that of the active mesa region. In one example, the second width is greater than the first width to provide the higher carrier charge. In another example, the dopant concentration in the transition mesa region is higher than that in the active mesa region to provide the higher carrier charge.
    Type: Grant
    Filed: September 18, 2018
    Date of Patent: August 3, 2021
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Zia Hossain, Tetsuro Asano, Syoji Miyahara, Yasuyuki Sayama
  • Patent number: 11081394
    Abstract: A method of fabricating a fin-like field-effect transistor device is disclosed. The method includes forming mandrel features over a substrate and performing a first cut to remove mandrel features to form a first space. The method also includes performing a second cut to remove a portion of mandrel features to form a line-end and an end-to-end space. After the first and the second cuts, the substrate is etched using the mandrel features, with the first space and the end-to-end space as an etch mask, to form fins. Depositing a space layer to fully fill in a space between adjacent fins and cover sidewalls of the fins adjacent to the first space and the end-to-end space. The spacer layer is etched to form sidewall spacers on the fins adjacent to the first space and the end-to-end space and an isolation trench is formed in the first space and the end-to-end space.
    Type: Grant
    Filed: October 8, 2018
    Date of Patent: August 3, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Ming-Feng Shieh, Wen-Hung Tseng, Tzung-Hua Lin, Hung-Chang Hsieh
  • Patent number: 11075278
    Abstract: A three-dimensional (3D) capacitor includes a semiconductor substrate; one or more fins extending from the semiconductor substrate; an insulator material between each of the one or more fins; a dielectric layer over a first portion of the one or more fins and over the insulator material; a first electrode over the dielectric layer; spacers on sidewalls of the first electrode; and a second electrode over a second portion of the one or more fins and over the insulator material, wherein the first and second portions are different.
    Type: Grant
    Filed: April 25, 2019
    Date of Patent: July 27, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chi-Wen Liu, Chao-Hsiung Wang
  • Patent number: 11062956
    Abstract: A semiconductor structure and a method for fabricating the same. The semiconductor structure includes at least one semiconductor fin disposed on a substrate. A disposable gate contacts the at least one semiconductor fin. A spacer is disposed on the at least one semiconductor fin and in contact with the disposable gate. Epitaxially grown source and drain regions are disposed at least partially within the at least one semiconductor fin. A first one of silicide and germanide is disposed on and in contact with the source region. A second one of one of silicide and germanide is disposed on and in contact with the drain region. The method includes epitaxially growing source/drain regions within a semiconductor fin. A contact metal layer contacts the source/drain regions. One of a silicide and a germanide is formed on the source/drain regions from the contact metal layer prior to removing the disposable gate.
    Type: Grant
    Filed: December 27, 2017
    Date of Patent: July 13, 2021
    Assignee: International Business Machines Corporation
    Inventors: Praneet Adusumilli, Hemanth Jagannathan, Christian Lavoie, Ahmet S. Ozcan
  • Patent number: 11056484
    Abstract: A semiconductor device includes an IGBT region extending from a front surface to a rear surface of a semiconductor substrate including a first conductive type drift layer, and a diode region lying adjacent to the IGBT region. The IGBT region includes a second conductive type base layer on a side facing the front surface and a first trench portion penetrating the base layer. The first trench portion includes a first gate electrode, a second gate electrode provided directly below the first gate electrode, and an insulating film provided on a side surface of the first gate electrode, between the first gate electrode and the second gate electrode and in a position to contact the second gate electrode. The diode region includes a second conductive type anode layer and a second trench portion including a dummy gate electrode on the side facing the front surface.
    Type: Grant
    Filed: August 7, 2019
    Date of Patent: July 6, 2021
    Assignee: Mitsubishi Electric Corporation
    Inventor: Ryu Kamibaba
  • Patent number: 11049950
    Abstract: A trench power semiconductor device and a manufacturing method thereof are provided. The trench power semiconductor device includes a substrate, an epitaxial layer disposed on the substrate, and a gate structure. The epitaxial layer has at least one trench formed therein, and the gate structure is disposed in the trench. A gate structure includes a lower doped region and an upper doped region disposed above the lower doped region to form a PN junction. The concentration of the impurity decreases along a direction from a peripheral portion of the upper doped region toward a central portion of the upper doped region.
    Type: Grant
    Filed: August 30, 2019
    Date of Patent: June 29, 2021
    Assignee: SUPER GROUP SEMICONDUCTOR CO., LTD.
    Inventor: Hsiu-Wen Hsu
  • Patent number: 11049965
    Abstract: A semiconductor device includes a first external electrode with a first electrode surface portion; a second external electrode with a second electrode surface portion; a MOSFET chip with a built-in Zener diode which includes an active region and a peripheral region; a control IC chip which drives the MOSFET chip based on voltage or current between a drain electrode and a source electrode of the MOSFET chip; and a capacitor which supplies power to the MOSFET chip and the control IC chip. The first electrode surface portion is connected to either the drain electrode or the source, the second electrode surface portion is connected to either the source electrode or the drain electrode, a plurality of unit cells of the MOSFET with the built-in Zener diode are provided in the active region, and the breakdown voltage of the Zener diode is set to be lower than that of the peripheral region.
    Type: Grant
    Filed: August 6, 2018
    Date of Patent: June 29, 2021
    Assignee: HITACHI POWER SEMICONDUCTOR DEVICE, LTD.
    Inventors: Masaki Shiraishi, Tetsuya Ishimaru, Junichi Sakano, Mutsuhiro Mori, Shinichi Kurita
  • Patent number: 11011538
    Abstract: A transistor comprises channel material having first and second opposing sides. A gate is on the first side of the channel material and a gate insulator is between the gate and the channel material. A first insulating material has first and second opposing sides, with the first side being adjacent the second side of the channel material. A second insulating material of different composition from that of the first insulating material is adjacent the second side of the first insulating material. The second insulating material has at least one of (a), (b), and (c), where, (a): lower oxygen diffusivity than the first material, (b): net positive charge, and (c): at least two times greater shear strength than the first material. In some embodiments, an array of elevationally-extending strings of memory cells comprises such transistors. Other embodiments, including method, are disclosed.
    Type: Grant
    Filed: May 8, 2019
    Date of Patent: May 18, 2021
    Assignee: Micron Technology, Inc.
    Inventors: David H. Wells, Luan C. Tran, Jie Li, Anish A. Khandekar, Kunal Shrotri
  • Patent number: 11011468
    Abstract: The present disclosure provides a semiconductor structure. The semiconductor structure includes a semiconductor substrate, a target layer, a plurality of metal pads, a plurality of conductive lines, a plurality of conductive plugs, an isolating liner, and a plurality of metal contacts. The semiconductor substrate has a front surface, a rear surface opposite to the front surface, and an implanted region connected to the rear surface. The target layer is disposed over the front surface. The metal pads are disposed over the target layer. The plurality of conductive lines are disposed within the semiconductor substrate and the target layer and connected to the metal pads. The conductive plugs are disposed in the implanted region. The isolating liner encircles the conductive plugs. The metal contacts are disposed over the conductive lines and the conductive plugs.
    Type: Grant
    Filed: November 6, 2019
    Date of Patent: May 18, 2021
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventor: Hsih-Yang Chiu
  • Patent number: 11004936
    Abstract: Insulated gate semiconductor device includes drift layer of first conductivity type; first base region of second conductivity type on the drift layer; carrier-supply region of the first conductivity type on the first base region and having higher impurity concentration than the drift layer; a first contact region of the second conductivity type on the first base region and having higher impurity concentration than the first base regions; cell-pillars each having polygonal-shape, arranged in a lattice-pattern, sidewalls of the cell-pillars are defined by trenches penetrating the carrier-supply region, the first contact region, and the first base region; and insulated-gate electrode-structures in the trenches. A first pillar selected from the cell-pillars includes the carrier-supply region, the first contact region and the first base region, and the first contact regions are in contact with a limited portion of an outer periphery of a first pillar at a top surface of the first pillar.
    Type: Grant
    Filed: April 29, 2019
    Date of Patent: May 11, 2021
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventor: Syunki Narita
  • Patent number: 10991762
    Abstract: In a memory unit according to an embodiment of the present disclosure, a memory cell array is configured, when, of a plurality of memory cells, multiple first memory cells whose corresponding fourth wiring line and first wiring line are different from one another are simultaneously accessed, to allow for simultaneous access to the multiple first memory cells, without allowing for simultaneous access to memory cells corresponding to the fourth wiring line shared by the first memory cells.
    Type: Grant
    Filed: March 5, 2018
    Date of Patent: April 27, 2021
    Assignee: Sony Semiconductor Solutions Corporation
    Inventors: Makoto Kitagawa, Yoshiyuki Shibahara, Haruhiko Terada, Yotaro Mori
  • Patent number: 10964783
    Abstract: A semiconductor device according to an exemplary embodiment of the present disclosure includes a substrate, an n? type layer, a plurality of trenches, a p type region, a p+ type region, an n+ type region, a gate electrode, a source electrode, and a drain electrode. The semiconductor device may include a plurality of unit cells. A unit cell among the plurality of unit cells may include a contact portion with which the source electrode and the n+ type region are in contact, a first branch part disposed above the contact portion on a plane, and a second branch part disposed below the contact portion on a plane, the plurality of trenches are separated from each other and disposed with a stripe shape on a plane.
    Type: Grant
    Filed: July 1, 2019
    Date of Patent: March 30, 2021
    Assignees: Hyundai Motor Company, Kia Motors Corporation
    Inventor: Dae Hwan Chun
  • Patent number: 10957534
    Abstract: A method of manufacturing a semiconductor device includes forming a first sacrificial layer including a nitride over a first source layer, forming a second sacrificial layer including aluminum oxide over the first sacrificial layer, forming a second source layer over the second sacrificial layer, forming a stacked structure over the second source layer, forming a channel layer that passes through the stacked structure, the second source layer, the second sacrificial layer, and the first sacrificial layer, the channel layer being enclosed by a memory layer, forming a slit that passes through the stacked structure and the second source layer, forming a polysilicon spacer in the slit, forming an opening by removing the first sacrificial layer and the second sacrificial layer, exposing the channel layer by etching the memory layer, and forming a third source layer in the opening.
    Type: Grant
    Filed: October 18, 2019
    Date of Patent: March 23, 2021
    Assignee: SK hynix Inc.
    Inventors: Sun Young Kim, Nam Jae Lee
  • Patent number: 10943833
    Abstract: Among other things, one or semiconductor arrangements, and techniques for forming such semiconductor arrangements are provided. For example, one or more silicon and silicon germanium stacks are utilized to form PMOS transistors comprising germanium nanowire channels and NMOS transistors comprising silicon nanowire channels. In an example, a first silicon and silicon germanium stack is oxidized to transform silicon to silicon oxide regions, which are removed to form germanium nanowire channels for PMOS transistors. In another example, silicon and germanium layers within a second silicon and silicon germanium stack are removed to form silicon nanowire channels for NMOS transistors. PMOS transistors having germanium nanowire channels and NMOS transistors having silicon nanowire channels are formed as part of a single fabrication process.
    Type: Grant
    Filed: October 11, 2019
    Date of Patent: March 9, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Kuo-Cheng Chiang, Carlos H. Diaz, Jean-Pierre Colinge
  • Patent number: 10937874
    Abstract: A semiconductor device includes: a gate electrode groove formed in contact with a drift region, a well region, and a source region; a gate electrode formed on a surface of the gate electrode groove via an insulating film; a source electrode groove in contact with the gate electrode groove; a source electrode electrically connected to a source region; and a gate wiring electrically insulated from the source electrode and formed inside the source electrode groove in contact with the gate electrode.
    Type: Grant
    Filed: August 10, 2016
    Date of Patent: March 2, 2021
    Assignee: NISSAN MOTOR CO., LTD.
    Inventors: Ryota Tanaka, Tetsuya Hayashi, Wei Ni, Yasuaki Hayami
  • Patent number: 10930741
    Abstract: A p-type base region is configured by a p?-type channel region and a p-type high-impurity-concentration region adjacent to the channel region in a horizontal direction. A point having a highest impurity concentration in the high-concentration region is located at a position separated from a lower surface of an n++-type source region. The impurity concentration in the high-impurity-concentration region decreases toward the front surface of the semiconductor substrate and the rear surface of the semiconductor substrate in the depth direction. The impurity concentration in the high-impurity-concentration region decreases toward the low-impurity-concentration region in a direction parallel to the front surface of the semiconductor substrate.
    Type: Grant
    Filed: October 22, 2019
    Date of Patent: February 23, 2021
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Makoto Utsumi, Tsuyoshi Araoka