With Thick Insulator To Reduce Gate Capacitance In Non-channel Areas (e.g., Thick Oxide Over Source Or Drain Region) Patents (Class 257/333)
  • Patent number: 10553717
    Abstract: A semiconductor device includes a medium voltage MOSFET having a vertical drain drift region between RESURF trenches containing field plates which are electrically coupled to a source electrode of the MOSFET. A split gate with a central opening is disposed above the drain drift region between the RESURF trenches. A two-level LDD region is disposed below the central opening in the split gate. A contact metal stack makes contact with a source region at lateral sides of the triple contact structure, and with a body contact region and the field plates in the RESURF trenches at a bottom surface of the triple contact structure. A perimeter RESURF trench surrounds the MOSFET. A field plate in the perimeter RESURF trench is electrically coupled to the source electrode of the MOSFET. An integrated snubber may be formed in trenches formed concurrently with the RESURF trenches.
    Type: Grant
    Filed: April 26, 2016
    Date of Patent: February 4, 2020
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Christopher Boguslaw Kocon, Hideaki Kawahara, Simon John Molloy, Satoshi Suzuki, John Manning Savidge Neilson
  • Patent number: 10535765
    Abstract: A power semiconductor device including a substrate having an active region and a terminal region is provided. The terminal region surrounds the active region. A first epitaxial layer is disposed on the substrate in the active region and the terminal region. A second epitaxial layer is disposed on the first epitaxial layer. The second epitaxial layer includes a first termination trench, a second termination trench, and a third termination trench. The first termination trench is disposed in the terminal region and is adjacent to the active region. The second termination trench is disposed in the terminal region. The third termination trench is disposed in the terminal region. The second termination trench is located between the first termination trench and the third termination trench. The third termination trench has a third electrode electrically connected to a drain.
    Type: Grant
    Filed: August 31, 2018
    Date of Patent: January 14, 2020
    Assignee: uPI Semiconductor Corp.
    Inventor: Chin-Fu Chen
  • Patent number: 10411188
    Abstract: A mask plate for vapor deposition of an organ light-emitting diode (OLED) device and an OLED device manufactured thereby are provided. The mask plate has first slot-type mask portions disposed at intervals along a predetermined direction; second slot-type mask portions disposed at intervals along a direction perpendicular to the first slot-type mask portion and pixel regions into at least two displaying regions with the first slot-type mask portion. An intersection portion formed by the first slot-type mask portion and the second slot-type mask portion covers a connection hole connected to an auxiliary cathode.
    Type: Grant
    Filed: November 10, 2017
    Date of Patent: September 10, 2019
    Assignee: SHENZHEN CHINA STAR OPTOELECTRONICS SEMICONDUCTOR DISPLAY TECHNOLOGY CO., LTD.
    Inventors: Feng Wei, Liang Jiang, Jinchuan Li
  • Patent number: 10381460
    Abstract: A semiconductor device and a method for manufacturing the same are provided. The semiconductor device includes a well region, a drain region and a source region disposed in the well region, a gate electrode disposed above the well region, a thin gate insulating layer and a thick gate insulating layer disposed under the gate electrode, the thick gate insulating layer being disclosed closer to the drain region than the thin gate insulating layer, and an extended drain junction region disposed below the gate electrode.
    Type: Grant
    Filed: January 27, 2017
    Date of Patent: August 13, 2019
    Assignee: MagnaChip Semiconductor, Ltd.
    Inventors: Yu Shin Ryu, Bo Seok Oh, Jin Yeong Son
  • Patent number: 10236182
    Abstract: A method of forming a nitrogen-doped amorphous carbon layer on a substrate in a processing chamber is provided. The method generally includes depositing a predetermined thickness of a sacrificial dielectric layer over a substrate, forming patterned features on the substrate by removing portions of the sacrificial dielectric layer to expose an upper surface of the substrate, depositing conformally a predetermined thickness of a nitrogen-doped amorphous carbon layer on the patterned features and the exposed upper surface of the substrate, selectively removing the nitrogen-doped amorphous carbon layer from an upper surface of the patterned features and the upper surface of the substrate using an anisotropic etching process to provide the patterned features filled within sidewall spacers formed from the nitrogen-doped amorphous carbon layer, and removing the patterned features from the substrate.
    Type: Grant
    Filed: February 14, 2017
    Date of Patent: March 19, 2019
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Sungjin Kim, Deenesh Padhi, Sung Hyun Hong, Bok Hoen Kim, Derek R. Witty
  • Patent number: 10121779
    Abstract: Integrated circuits and methods of producing integrated circuits are provided. In an exemplary embodiment, an integrated circuit includes a source and a drain defined within a body isolation well. A gate overlies the body isolation well between the source and the drain, and an isolating structure is formed within the body isolation well. The isolating structure sections the source into a plurality of source sections with the plurality of source sections adjacent to one gate.
    Type: Grant
    Filed: December 13, 2016
    Date of Patent: November 6, 2018
    Assignee: Globalfoundries Singapore Pte. Ltd.
    Inventors: Handoko Linewih, Chao Cheng
  • Patent number: 10008579
    Abstract: Schottky structure fabrication includes forming two trenches in a semiconductor material. The trenches are separated from each other by a mesa. Sidewalls and a bottom surface of the trenches are lined with a dielectric material. A conductive material is disposed in the trenches lining the dielectric material on the sidewalls and the bottom surface. The conductive material on the bottom surface of the trenches is removed so that a first portion of conductive material remains on a first sidewall of each trench, and a second portion of conductive material remains on a second sidewall of each trench. The first and second portions of conductive material are electrically isolated from each other. The space between the first and second portions of the conductive material is filled with a trench filling insulator material and a Schottky contact is formed between the outermost sidewalls of the two trenches.
    Type: Grant
    Filed: June 17, 2016
    Date of Patent: June 26, 2018
    Assignee: ALPHA AND OMEGA SEMICONDUCTOR INCORPORATED
    Inventors: Daniel Calafut, Yeeheng Lee
  • Patent number: 10002838
    Abstract: An integrated radio frequency (RF) circuit structure may include an active device on a first surface of an isolation layer. The integrated RF circuit structure may also include a back-bias metallization on a second surface opposite the first surface of the isolation layer. A body of the active device is biased by the back-bias metallization. The integrated RF circuit structure may further include a handle substrate on a front-side dielectric layer on the active device.
    Type: Grant
    Filed: June 22, 2016
    Date of Patent: June 19, 2018
    Assignee: QUALCOMM Incorporated
    Inventor: Sinan Goktepeli
  • Patent number: 9972796
    Abstract: Provided is a display device including: a first wiring over an insulating surface; a sidewall over the insulating surface and covering a side surface of the first wiring; an insulating film over the first wiring and the sidewall; and a second wiring over the insulating film, the second wiring intersecting with the first wiring, where an angle of a surface of the sidewall with respect to the insulating surface is smaller than an angle of the side surface of the first wiring with respect to the insulating surface. The angle increases with decreasing distance from the first wiring. An intersection portion of the first wiring and the second wiring is located in a display region of the display device and included in a bent portion of the display device when the display device is bent so that the first wiring is bent.
    Type: Grant
    Filed: October 4, 2016
    Date of Patent: May 15, 2018
    Assignee: Japan Display Inc.
    Inventor: Kenta Kajiyama
  • Patent number: 9954003
    Abstract: A semiconductor device with high design flexibility is provided. A first transistor and a second transistor having electrical characteristics different from those of the first transistor are provided over the same layer without significantly increasing the number of manufacturing steps. For example, semiconductor materials with different electron affinities are used for a semiconductor layer in which a channel of the first transistor is formed and a semiconductor layer in which a channel of the second transistor is formed. This allows the threshold voltages of the first transistor and the second transistor to differ from each other. Forming a gate electrode using a damascene process enables miniaturization and high density of the transistors. Furthermore, a highly-integrated semiconductor device is provided.
    Type: Grant
    Filed: February 13, 2017
    Date of Patent: April 24, 2018
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shinpei Matsuda, Masayuki Sakakura, Yuki Hata, Shuhei Nagatsuka, Yuta Endo, Shunpei Yamazaki
  • Patent number: 9953982
    Abstract: A method for fabricating semiconductor device includes the steps of: forming a shallow trench isolation (STI) in a substrate; removing part of the STI to form a first trench; forming a cap layer in the first trench; forming a mask layer on the cap layer and the substrate; and removing part of the mask layer, part of the cap layer, and part of the STI to form a second trench.
    Type: Grant
    Filed: March 23, 2017
    Date of Patent: April 24, 2018
    Assignees: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.
    Inventors: Pin-Hong Chen, Tsun-Min Cheng, Chih-Chieh Tsai, Tzu-Chieh Chen, Kai-Jiun Chang, Chia-Chen Wu, Yi-An Huang, Yi-Wei Chen
  • Patent number: 9793342
    Abstract: In an insulated-gate type semiconductor device in which a gate-purpose conductive layer is embedded into a trench which is formed in a semiconductor substrate, and a source-purpose conductive layer is provided on a major surface of the semiconductor substrate, a portion of a gate pillar which is constituted by both the gate-purpose conductive layer and a cap insulating film for capping an upper surface of the gate-purpose conductive layer is projected from the major surface of the semiconductor substrate; a side wall spacer is provided on a side wall of the projected portion of the gate pillar; and the source-purpose conductive layer is connected to a contact region of the major surface of the semiconductor substrate, which is defined by the side wall spacer.
    Type: Grant
    Filed: December 21, 2015
    Date of Patent: October 17, 2017
    Assignees: Renesas Electronics Corporation, Renesas Semiconductor Package & Test Solutions Co., Ltd
    Inventors: Hiroshi Inagawa, Nobuo Machida, Kentaro Oishi
  • Patent number: 9627265
    Abstract: A method comprises providing a substrate with a second conductivity type, growing a first epitaxial layer having the second conductivity type, growing a second epitaxial layer having a first conductivity type, forming a trench in the first epitaxial layer and the second epitaxial layer, forming a gate electrode in the trench, applying an ion implantation process using first gate electrode as an ion implantation mask to form a drain-drift region, forming a field plate in the trench, forming a drain region in the second epitaxial layer, wherein the drain region has the first conductivity type and forming a source region in the first epitaxial layer, wherein the source region has the first conductivity type, and wherein the source region is electrically coupled to the field plate.
    Type: Grant
    Filed: March 21, 2016
    Date of Patent: April 18, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Po-Chih Su, Hsueh-Liang Chou, Chun-Wai Ng, Ruey-Hsin Liu
  • Patent number: 9570545
    Abstract: A method of forming a device is disclosed. A substrate defined with a device region is provided. A gate having a gate electrode, first and second gate dielectric layers is formed in a trench. The trench has an upper trench portion and a lower trench portion. A field plate is formed in the trench. First and second diffusion regions are formed. The gate is displaced from the second diffusion region.
    Type: Grant
    Filed: April 22, 2015
    Date of Patent: February 14, 2017
    Assignee: GLOBALFOUNDRIES SINGAPORE PTE. LTD.
    Inventors: Yemin Dong, Liang Yi, Zhanfeng Liu, Purakh Raj Verma, Ramadas Nambatyathu
  • Patent number: 9558990
    Abstract: A semiconductor device and a method for forming the same can block a moving path of electrons between neighbor buried gates. A semiconductor device includes a device isolation film formed to define an active region over a semiconductor substrate. The semiconductor device also includes a plurality of buried gates formed over the active region, and a barrier film formed between neighboring buried gates from the plurality of buried gates.
    Type: Grant
    Filed: September 24, 2015
    Date of Patent: January 31, 2017
    Assignee: SK HYNIX INC.
    Inventor: Kyung Kyu Min
  • Patent number: 9437470
    Abstract: A system and method for providing electrical isolation between closely spaced devices in a high density integrated circuit (IC) are disclosed herein. An integrated circuit (IC) comprising a substrate, a first device, a second device, and a trench in the substrate and a method of fabricating the same are also discussed. The trench is self-aligned between the first and second devices and comprises a first filled portion and a second filled portion. The first fined portion of the trench comprises a dielectric material that forms a buried trench isolation for providing electrical isolation between the first and second devices. The self-aligned placement of the buried trench isolation allows for higher packing density without negatively affecting the operation of closely spaced devices in a high density IC.
    Type: Grant
    Filed: October 8, 2013
    Date of Patent: September 6, 2016
    Assignee: Cypress Semiconductor Corporation
    Inventors: Ching-Huang Lu, Lei Xue, Kenichi Ohtsuka, Simon Siu-Sing Chan, Rinji Sugino
  • Patent number: 9406793
    Abstract: Semiconductor devices and manufacturing methods are provided for making channel and gate lengths independent from lithography. Also, semiconductor devices and manufacturing methods are provided for increasing resistivity between drain and channel to allow for higher voltage operation. For example, a semiconductor device includes a first doped layer implanted in a semiconductor substrate forming one of a source or a drain and a gate metal layer disposed over the first doped layer. The semiconductor device further includes a second doped layer disposed over the gate metal forming the other the source or the drain, where the first doped layer, the gate metal layer and the second doped layer form a vertical stack of layers of the semiconductor device. The semiconductor device further includes a conduction channel formed in a trench that extends vertically through the vertical stack of layers and terminates at the semiconductor substrate.
    Type: Grant
    Filed: October 31, 2014
    Date of Patent: August 2, 2016
    Assignee: Broadcom Corporation
    Inventors: Sam Ziqun Zhao, Frank Hui
  • Patent number: 9368576
    Abstract: Embodiments of semiconductor devices and methods of their formation include providing a semiconductor substrate having a top surface, a bottom surface, an active region, and an edge region, and forming a gate structure in a first trench in the active region of the semiconductor substrate. A termination structure is formed in a second trench in the edge region of the semiconductor substrate. The termination structure has an active region facing side and a device perimeter facing side. The method further includes forming first and second source regions of the first conductivity type are formed in the semiconductor substrate adjacent both sides of the gate structure. A third source region is formed in the semiconductor substrate adjacent the active region facing side of the termination structure. The semiconductor device may be a trench metal oxide semiconductor device, for example.
    Type: Grant
    Filed: September 12, 2012
    Date of Patent: June 14, 2016
    Assignee: FREESCALE SEMICONDUCTOR, INC.
    Inventors: Peilin Wang, Jingjing Chen, Edouard D. de Fresart
  • Patent number: 9356022
    Abstract: A semiconductor device may have an active device region containing a plurality of active devices and a termination structure that surrounds the active device region. The termination structure includes a first conductive region that surrounds the active device region, an insulator region that surrounds the first conductive region, and a second conductive region that surrounds the first conductive region and the insulator region. The active device region and termination structure are formed into a semiconductor material of a first conductivity type. The first conductive region is electrically connected to a gate metal and the second conductive region is connected to a drain metal.
    Type: Grant
    Filed: July 23, 2015
    Date of Patent: May 31, 2016
    Assignee: ALPHA AND OMEGA SEMICONDUCTOR INCORPORATED
    Inventors: Yeeheng Lee, Madhur Bobde, Daniel Calafut, Hamza Yilmaz, Xiaobin Wang, Ji Pan, Hong Chang, Jongoh Kim
  • Patent number: 9214515
    Abstract: The invention relates to a method for making a semiconducting structure, including: a) forming, on the surface of a semiconductor substrate (2), called the final substrate, a semiconducting layer (4), doped with elements from columns III and V of the Periodic Table so as to form a ground plane, b) forming a dielectric layer (3), c) then assembling, by direct adhesion of the source substrate, on the final substrate (2), the layer (4) forming the ground plane between the final substrate and the source substrate, the dielectric layer being between the source substrate and the ground plane, d) then thinning the source substrate, leaving, on the surface of the semiconductor structure, a film (20) made from a semiconducting material.
    Type: Grant
    Filed: June 10, 2013
    Date of Patent: December 15, 2015
    Assignee: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
    Inventors: Yannick Le Tiec, Francois Andrieu
  • Patent number: 9177851
    Abstract: A semiconductor device and a method for forming the same can block a moving path of electrons between neighbor buried gates. A semiconductor device includes a device isolation film formed to define an active region over a semiconductor substrate. The semiconductor device also includes a plurality of buried gates formed over the active region, and a barrier film formed between neighboring buried gates from the plurality of buried gates.
    Type: Grant
    Filed: December 13, 2013
    Date of Patent: November 3, 2015
    Assignee: SK HYNIX INC.
    Inventor: Kyung Kyu Min
  • Patent number: 9159827
    Abstract: A method of forming a manufacture includes forming a trench in a doped layer. The trench has an upper portion and a lower portion, and a width of the upper portion is greater than that of the lower portion. A first insulating layer is formed along sidewalls of the lower portion of the trench and a bottom surface of the trench. A gate dielectric layer is formed along sidewalls of the upper portion of the trench. A first conductive feature is formed along sidewalls of the gate dielectric layer. A second insulating layer covering the first conductive feature and the first insulating layer is formed, and a second conductive feature is formed along sidewalls of the second insulating layer and a bottom surface of the second insulating layer.
    Type: Grant
    Filed: July 2, 2014
    Date of Patent: October 13, 2015
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chih-Chang Cheng, Fu-Yu Chu, Ruey-Hsin Liu
  • Patent number: 9136380
    Abstract: Aspects of the present disclosure describe a high density trench-based power MOSFETs with self-aligned source contacts and methods for making such devices. The source contacts are self-aligned with spacers that are formed along the sidewall of the gate caps. Additionally, the active devices may have a two-step gate oxide. A lower portion may have a thickness that is larger than the thickness of an upper portion of the gate oxide. The two-step gate oxide combined with the self-aligned source contacts allow for the production of devices with a pitch in the deep sub-micron level. It is emphasized that this abstract is provided to comply with rules requiring an abstract that will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims.
    Type: Grant
    Filed: July 11, 2014
    Date of Patent: September 15, 2015
    Assignee: Alpha and Omega Semiconductor Incorporated
    Inventors: Hamza Yilmaz, Madhur Bobde, Hong Chang, Yeeheng Lee, Daniel Calafut, Jongoh Kim, Sik Lui, John Chen
  • Patent number: 9117903
    Abstract: A buried layer of a second conductivity type and a lower layer of a second conductivity type are formed in a drift layer. A boundary insulating film is formed in the boundary between the lateral portion of the buried layer of a second conductivity type and the drift layer. The lower layer of a second conductivity type is in contact with the lower end of the buried layer of a second conductivity type and the lower end of the boundary insulating film. The buried layer of a second conductivity type is electrically connected to a source electrode. A high-concentration layer of a second conductivity type is formed in the surface layer of the buried layer of a second conductivity type.
    Type: Grant
    Filed: March 11, 2014
    Date of Patent: August 25, 2015
    Assignee: Renesas Electronics Corporation
    Inventors: Akihiro Shimomura, Yutaka Akiyama, Saya Shimomura, Yasutaka Nakashiba
  • Patent number: 9048215
    Abstract: A semiconductor device includes a first layer of a first-type, a second layer of a second-type formed on the first layer, a third layer of the first type formed on the second layer, a first electrode connected to the second and third layers, a second electrode connected to the first layer, a third electrode embedded in a trench formed through the third and second layers and into the first layer, a fourth electrode embedded in the trench below the third electrode, and an insulating layer formed in the trench around the fourth electrode. The first layer includes a first region that is in contact with the insulating layer and at which a concentration of the first-type dopant is lower than the concentration at a second region that is formed around the first region.
    Type: Grant
    Filed: August 29, 2013
    Date of Patent: June 2, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Hidetoshi Asahara
  • Patent number: 9041008
    Abstract: A semiconductor device of an embodiment includes a first conductive type silicon carbide substrate having first and second main surfaces, a first conductive type silicon carbide layer formed on the first main surface, a second conductive type first silicon carbide region formed in the silicon carbide layer, and a first conductive type second silicon carbide region formed in the first silicon carbide region. The device includes a trench penetrating through the first and second silicon carbide regions, and a second conductive type third silicon carbide region formed on a bottom and a side surface of the trench. The third silicon carbide region is in contact with the first silicon carbide region, and is formed between the trench and the silicon carbide layer. In addition, the device includes a gate insulating film formed in the trench, a gate electrode, a first electrode, and a second electrode.
    Type: Grant
    Filed: March 5, 2012
    Date of Patent: May 26, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yukio Nakabayashi, Takashi Shinohe, Atsuko Yamashita
  • Patent number: 9029941
    Abstract: A vertical transistor component includes a semiconductor body with first and second surfaces, a drift region, and a source region and body region arranged between the drift region and the first surface. The body region is also arranged between the source region and the drift region. The vertical transistor component further includes a gate electrode arranged adjacent to the body zone, a gate dielectric arranged between the gate electrode and the body region, and a drain region arranged between the drift region and the second surface. A source electrode electrically contacts the source region, is electrically insulated from the gate electrode and arranged on the first surface. A drain electrode electrically contacts the drain region and is arranged on the second surface. A gate contact electrode is electrically insulated from the semiconductor body, extends in the semiconductor body to the second surface, and is electrically connected with the gate electrode.
    Type: Grant
    Filed: July 24, 2013
    Date of Patent: May 12, 2015
    Assignee: Infineon Technologies AG
    Inventors: Andreas Meiser, Markus Zundel, Christoph Kadow
  • Patent number: 9006821
    Abstract: An electronic device can include a semiconductor layer overlying a substrate and having a primary surface and a thickness, wherein a trench extends through at least approximately 50% of the thickness of semiconductor layer to a depth. The electronic device can further include a conductive structure within the trench, wherein the conductive structure extends at least approximately 50% of the depth of the trench. The electronic device can still further include a vertically-oriented doped region within the semiconductor layer adjacent to and electrically insulated from the conductive structure; and an insulating layer disposed between the vertically-oriented doped region and the conductive structure. A process of forming an electronic device can include patterning a semiconductor layer to define a trench extending through at least approximately 50% of the thickness of the semiconductor layer and forming a vertically-oriented doped region after patterning the semiconductor layer to define the trench.
    Type: Grant
    Filed: February 3, 2014
    Date of Patent: April 14, 2015
    Assignee: Semiconductor Components Industries, LLC
    Inventors: Prasad Venkatraman, Gordon M. Grivna, Gary H. Loechelt
  • Patent number: 9006829
    Abstract: Among other things, a semiconductor device comprising an aligned gate and a method for forming the semiconductor device are provided. The semiconductor device comprises a gate formed according to a multi-gate structure, such as a gate-all-around structure. A first gate portion of the gate is formed above a first channel of the semiconductor device. A second gate portion of the gate is formed below the first channel, and is aligned with the first gate portion. In an example of forming the gate, a cavity is etched within a semiconductor layer formed above a substrate. A dielectric layer is formed around at least some of the cavity to define a region of the cavity within which the second gate portion is to be formed in a self-aligned manner with the first gate portion. In this way, the semiconductor device comprises a first gate portion aligned with a second gate portion.
    Type: Grant
    Filed: August 24, 2012
    Date of Patent: April 14, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jean-Pierre Colinge, Kuo-Cheng Ching, Zhiqiang Wu
  • Patent number: 9000516
    Abstract: A super-junction device including a unit region is disclosed. The unit region includes a heavily doped substrate; a first epitaxial layer over the heavily doped substrate; a second epitaxial layer over the first epitaxial layer; a plurality of first trenches in the second epitaxial layer; an oxide film in each of the plurality of first trenches; and a pair of first films on both sides of each of the plurality of first trenches, thereby forming a sandwich structure between every two adjacent ones of the plurality of first trenches, the sandwich structure including two first films and a second film sandwiched therebetween, the second film being formed of a portion of the second epitaxial layer between the two first films of a sandwich structure. A method of forming a super-junction device is also disclosed.
    Type: Grant
    Filed: September 5, 2013
    Date of Patent: April 7, 2015
    Assignee: Shanghai Hua Hong NEC Electronics Co., Ltd.
    Inventor: Shengan Xiao
  • Patent number: 8994101
    Abstract: A method for fabricating a semiconductor device includes forming a plurality of trenches using a first mask. The trenches include source pickup trenches located in outside a termination area and between two adjacent active areas. First and second conductive regions separated by an intermediate dielectric region are formed using a second mask. A first electrical contact to the first conductive region and a second electrical contact to the second conductive region are formed using a third mask and forming a source metal region. Contacts to a gate metal region are formed using a fourth mask. A semiconductor device includes a source pickup contact located outside a termination region and outside an active region of the device.
    Type: Grant
    Filed: April 18, 2013
    Date of Patent: March 31, 2015
    Assignee: Alpha and Omega Semiconductor Incorporated
    Inventors: Hong Chang, Yi Su, Wenjun Li, Limin Weng, Jongoh Kim, John Chen
  • Patent number: 8994100
    Abstract: The present invention provides a semiconductor device designed to prevent an electric field from being concentrated in the vicinity of a groove portion. The semiconductor includes a semiconductor layer, a source region, a drain region, a source offset region, a drain offset region, a groove portion, a gate insulating film, a gate electrode, and an embedded region. The groove portion is provided in at least a position between the source offset region and the drain offset region in the semiconductor layer in a plan view, in a direction from the source offset region to the drain offset region in a plan view. The gate insulating film covers a side and a bottom of the groove portion. The gate electrode is provided only within the groove portion in a plan view, and contacts the gate insulating film.
    Type: Grant
    Filed: February 12, 2013
    Date of Patent: March 31, 2015
    Assignee: Renesas Electronics Corporation
    Inventor: Hiroki Matsumoto
  • Patent number: 8987811
    Abstract: According to example embodiments, a semiconductor device includes a plurality of active pillars protruding from a substrate. Each active pillar includes a channel region between upper and lower doped regions. A contact gate electrode faces the channel region and is connected to a word line. The word line extends in a first direction. A bit line is connected to the lower doped region and extends in a second direction. The semiconductor device further includes a string body connection portion that connects the channel region of at least two adjacent active pillars of the plurality of active pillars.
    Type: Grant
    Filed: August 17, 2012
    Date of Patent: March 24, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hak-soo Yu, Chulwoo Park, Hyun-Woo Chung, Sua Kim, Hyunho Choi, Hongsun Hwang
  • Patent number: 8928065
    Abstract: A termination structure for a power transistor includes a semiconductor substrate having an active region and a termination region. The substrate has a first type of conductivity. A termination trench is located in the termination region and extends from a boundary of the active region to within a certain distance of an edge of the semiconductor substrate. A doped region has a second type of conductivity disposed in the substrate below the termination trench. A MOS gate is formed on a sidewall adjacent the boundary. The doped region extends from below a portion of the MOS gate spaced apart from the boundary toward a remote sidewall of the termination trench. A termination structure oxide layer is formed on the termination trench and covers a portion of the MOS gate and extends toward the edge of the substrate. A first conductive layer is formed on a backside surface of the semiconductor substrate.
    Type: Grant
    Filed: October 21, 2010
    Date of Patent: January 6, 2015
    Assignee: Vishay General Semiconductor LLC
    Inventors: Chih-Wei Hsu, Florin Udrea, Yih-Yin Lin
  • Patent number: 8928057
    Abstract: A method including providing fins etched from a semiconductor substrate and covered by an oxide layer and a nitride layer, the oxide layer being located between the fins and the nitride layer, removing a portion of the fins to form an opening, forming a dielectric spacer on a sidewall of the opening, and filling the opening with a fill material, wherein a top surface of the fill material is substantially flush with a top surface of the nitride layer. The method may further include forming a deep trench capacitor in-line with one of the fins, removing the nitride layer to form a gap between the fins and the fill material, wherein the fill material has re-entrant geometry extending over the gap, and removing the re-entrant geometry and causing the gap between the fins and the fill material to widen.
    Type: Grant
    Filed: November 30, 2012
    Date of Patent: January 6, 2015
    Assignee: International Business Machines Corporation
    Inventors: William Cote, Johnathan E. Faltermeier, Babar A. Khan, Ravikumar Ramachandran, Theodorus E. Standaert, Xinhui Wang
  • Patent number: 8921931
    Abstract: A semiconductor body of a semiconductor device includes a doped layer of a first conductivity type and one or more doped zones of a second conductivity type. The one or more doped zones are formed between the doped layer and the first surface of a semiconductor body. Trench structures extend from one of the first and the second opposing surface into the semiconductor body. The trench structures are arranged between portions of the semiconductor body which are electrically connected to each other. The trench structures may be arranged for mitigating mechanical stress, locally controlling charge carrier mobility, locally controlling a charge carrier recombination rate and/or shaping buried diffusion zones.
    Type: Grant
    Filed: June 4, 2012
    Date of Patent: December 30, 2014
    Assignee: Infineon Technologies Austria AG
    Inventors: Anton Mauder, Franz-Josef Niedernostheide, Hans-Joachim Schulze, Holger Schulze
  • Patent number: 8912596
    Abstract: A transistor used for a semiconductor device for high power application needs to have a channel region for obtaining higher drain current. As an example of such a transistor, a vertical (trench type) transistor has been considered; however, the vertical transistor cannot have a high on/off ratio of drain current and thus cannot have favorable transistor characteristics. Over a substrate having conductivity, an oxide semiconductor layer having a surface having a dotted pattern of a plurality of island-shaped regions with a tapered shape in a cross section is sandwiched between a first electrode formed between the substrate and the oxide semiconductor layer and a second electrode formed over the oxide semiconductor layer, and a conductive layer functioning as a gate electrode is formed on the side surface of the island-shaped region in the oxide semiconductor layer with an insulating layer provided therebetween.
    Type: Grant
    Filed: July 6, 2012
    Date of Patent: December 16, 2014
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Shunpei Yamazaki
  • Patent number: 8907413
    Abstract: A dual trench MOS transistor comprises of the following elements. A plurality of trenches are formed in an n? epitaxial layer on a heavy doped n+ semiconductor substrate and spaced to each other by one mesa. Each the trench has a trench oxide layer formed on a bottom and sidewalls thereof. A first polysilicon layer is formed in the trenches. A plurality of recesses are formed in the mesas and spaced to each other with one sub-mesa. Each the recess has a recess oxide layer formed on a bottom and sidewalls thereof. A second polysilicon layer for serving as a gate is formed in the recesses. The mesas are implanted to have implanted areas at two side of the gate. The implanted areas and the first polysilicon layer are applied to serve as the source. The rear surface of the substrate is served as the drain.
    Type: Grant
    Filed: December 2, 2013
    Date of Patent: December 9, 2014
    Assignee: Chip Integration Tech. Co., Ltd.
    Inventor: Qinhai Jin
  • Patent number: 8900950
    Abstract: A fabrication method of a high cell density trench power MOSFET structure is provided. Form at least a gate trench in a silicon substrate and a gate dielectric layer on the silicon substrate. Form a gate polysilicon structure in the gate trench and cover by a passivation layer. Form a first-conductive-type body region in the silicon substrate and implant impurities with a second conductive type thereof to form a source doped region. Expose the gate polysilicon structure and the source doped region. Form a dielectric spacer having a predetermined thickness on a sidewall of the gate trench. Deposit metal on the gate polysilicon structure and the source doped region. A first and a second self-aligned silicide layer are respectively formed on the gate polysilicon structure and the source doped region. The dielectric spacer forms an appropriate distance between the first and the second self-aligned silicide layer.
    Type: Grant
    Filed: March 20, 2012
    Date of Patent: December 2, 2014
    Assignee: Great Power Semiconductor Corp.
    Inventor: Hsiu-Wen Hsu
  • Publication number: 20140346592
    Abstract: A vertical MOSFET includes: a semiconductor substrate comprising a drain layer, a drift layer, a body layer, and a source layer; and a trench gate penetrating through the source layer and the body layer from an upper surface of the semiconductor substrate and reaching the drift layer. The trench gate includes a gate electrode; a first insulating film disposed on a bottom surface of a trench formed in the semiconductor substrate; a second insulating film disposed at least on a side surface of the trench, and in contact with the body layer; and a third insulating film disposed between the gate electrode and the second insulating film, and formed of a material of which dielectric constant is higher than a dielectric constant of the second insulating film.
    Type: Application
    Filed: December 6, 2012
    Publication date: November 27, 2014
    Applicants: DENSO CORPORATION, TOYOTA JIDOSHA KABUSHIKI KAISHA
    Inventors: Akitaka Soeno, Toshimasa Yamamoto, Yukihiko Watanabe
  • Patent number: 8895394
    Abstract: A high voltage vertical field effect transistor device (101) is fabricated in a substrate (102, 104) using angled implantations (116, 120) into trench sidewalls formed above recessed gate poly layers (114) to form self-aligned N+ regions (123) adjacent to the trenches and along an upper region of an elevated substrate. With a trench fill insulator layer (124) formed over the recessed gate poly layers (114), self-aligned P+ body contact regions (128) are implanted into the elevated substrate without counter-doping the self-aligned N+ regions (123), and a subsequent recess etch removes the elevated substrate, leaving self-aligned N+ source regions (135-142) and P+ body contact regions (130-134).
    Type: Grant
    Filed: June 20, 2012
    Date of Patent: November 25, 2014
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Ganming Qin, Edouard D. de Fr├ęsart, Peilin Wang, Pon S. Ku
  • Patent number: 8890252
    Abstract: A semiconductor device includes a switching element having: a drift layer; a base region; an element-side first impurity region in the base region; an element-side gate electrode sandwiched between the first impurity region and the drift layer; a second impurity region contacting the drift layer; an element-side first electrode coupled with the element-side first impurity region and the base region; and an element-side second electrode coupled with the second impurity region, and a FWD having: a first conductive layer; a second conductive layer; a diode-side first electrode coupled to the second conductive layer; a diode-side second electrode coupled to the first conductive layer; a diode-side first impurity region in the second conductive layer; and a diode-side gate electrode in the second conductive layer sandwiched between first impurity region and the first conductive layer and having a first gate electrode as an excess carrier injection suppression gate.
    Type: Grant
    Filed: July 26, 2011
    Date of Patent: November 18, 2014
    Assignee: DENSO CORPORATION
    Inventors: Hirotaka Saikaku, Tsuyoshi Yamamoto, Shoji Mizuno, Masakiyo Sumitomo, Tetsuo Fujii, Jun Sakakibara, Hitoshi Yamaguchi, Yoshiyuki Hattori, Rie Taguchi, Makoto Kuwahara
  • Patent number: 8866225
    Abstract: A field effect transistor including: a support layer, a plurality of active zones based on a semiconductor, each active zone configured to form a channel and arranged between two gates adjacent to each other and consecutive, the active zones and the gates being arranged on the support layer, each gate including a first face on the side of the support layer and a second face opposite the first face. The second face of a first of the two gates is electrically connected to a first electrical contact made on the second face of the first of the two gates, and the first face of a second of the two gates is electrically connected to a second electrical contact passing through the support layer. The gates of the transistor are not electrically connected to each other.
    Type: Grant
    Filed: June 19, 2008
    Date of Patent: October 21, 2014
    Assignee: Commissariat a l'Energie Atomique
    Inventors: Frederic Mayer, Laurent Clavelier, Thierry Poiroux, Gerard Billiot
  • Patent number: 8860131
    Abstract: An embodiment of a power device comprising and formation of at least one gate region, of at least one buried source region, of at least one body region and of at least one source region; at least one body/source contact and at least one buried source contact; and formation of a source contact region and of a gate contact region through deposition. An embodiment of the method also comprises formation of the at least one gate region and of the at least one buried source region, electrically insulated, through a single deposition of a conductive filling material on an epitaxial layer, on vertical walls of the trench and within the empty region; and through etching of the conductive filling material forming a first spacer and a second spacer, suitable for serving as a gate electrode and forming a buried source electrode within the empty region.
    Type: Grant
    Filed: March 13, 2013
    Date of Patent: October 14, 2014
    Assignee: STMICROELECTRONICS S.r.l.
    Inventor: Fabio Zara
  • Patent number: 8853770
    Abstract: A termination structure is provided for a power transistor. The termination structure includes a semiconductor substrate having an active region and a termination region. The substrate has a first type of conductivity. A termination trench is located in the termination region and extends from a boundary of the active region toward an edge of the semiconductor substrate. A doped region having a second type of conductivity is disposed in the substrate below the termination trench. A MOS gate is formed on a sidewall adjacent the boundary. The doped region extends from below a portion of the MOS gate spaced apart from the boundary toward the edge of the semiconductor substrate. A termination structure oxide layer is formed on the termination trench covering a portion of the MOS gate and extends toward the edge of the substrate.
    Type: Grant
    Filed: March 16, 2010
    Date of Patent: October 7, 2014
    Assignee: Vishay General Semiconductor LLC
    Inventors: Chih-Wei Hsu, Florin Udrea, Yih-Yin Lin
  • Patent number: 8847233
    Abstract: It is an object to provide a semiconductor device in which a short-channel effect is suppressed and miniaturization is achieved, and a manufacturing method thereof. A trench is formed in an insulating layer and impurities are added to an oxide semiconductor film in contact with an upper end corner portion of the trench, whereby a source region and a drain region are formed. With the above structure, miniaturization can be achieved. Further, with the trench, a short-channel effect can be suppressed setting the depth of the trench as appropriate even when a distance between a source electrode layer and a drain electrode layer is shortened.
    Type: Grant
    Filed: May 3, 2012
    Date of Patent: September 30, 2014
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Atsuo Isobe, Toshinari Sasaki, Junichi Koezuka, Shunpei Yamazaki
  • Patent number: 8829620
    Abstract: The first electrode of the transistor may include a first electrically conductive region provided within the semiconductor substrate. The second electrode may include a second electrically conductive region provided within the semiconductor substrate. The first and second regions may be separated by the substrate region, and the control electrode may include a third electrically conductive region provided within the substrate. The third electrically conductive region may be both separated from the substrate region by an insulating region and electrically coupled to the substrate region by a junction diode intended to be reverse-biased.
    Type: Grant
    Filed: March 30, 2012
    Date of Patent: September 9, 2014
    Assignee: STMicroelectronics SA
    Inventors: Philippe Galy, Jean Jimenez
  • Patent number: 8829605
    Abstract: A MOSFET includes: a substrate made of silicon carbide and having a first trench and a second trench formed therein, the first trench having an opening at the main surface side, the second trench having an opening at the main surface side and being shallower than the first trench; a gate insulating film; a gate electrode; and a source electrode disposed on and in contact with a wall surface of the second trench. The substrate includes a source region, a body region, and a drift region. The first trench is formed to extend through the source region and the body region and reach the drift region. The second trench is formed to extend through the source region and reach the body region.
    Type: Grant
    Filed: November 19, 2012
    Date of Patent: September 9, 2014
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Takeyoshi Masuda, Keiji Wada, Toru Hiyoshi, Shinji Matsukawa
  • Patent number: 8823088
    Abstract: A semiconductor device includes a first region and a second region, a buried gate arranged in the first region, and an oxidation prevention barrier surrounding the first region.
    Type: Grant
    Filed: April 8, 2013
    Date of Patent: September 2, 2014
    Assignee: SK Hynix Inc.
    Inventor: Se-Aug Jang
  • Patent number: RE47710
    Abstract: A power semiconductor element having a lightly doped drift and buffer layer is disclosed. One embodiment has, underneath and between deep well regions of a first conductivity type, a lightly doped drift and buffer layer of a second conductivity type. The drift and buffer layer has a minimum vertical extension between a drain contact layer on the adjacent surface of a semiconductor substrate and the bottom of the deepest well region which is at least equal to a minimum lateral distance between the deep well regions. The vertical extension can also be determined such that a total amount of dopant per unit area in the drift and buffer layer is larger than a breakdown charge amount at breakdown voltage.
    Type: Grant
    Filed: February 20, 2015
    Date of Patent: November 5, 2019
    Assignee: Infineon Technologies Austria AG
    Inventors: Markus Zundel, Franz Hirler, Armin Willmeroth