Abstract: A 6F2 memory cell structure and a method of fabricating the same. The memory cell structure includes a plurality of memory cells located in a Si-containing substrate which are arranged in rows and columns. Each memory cell includes a double-gated vertical MOSFET having exposed gate conductor regions and two gates formed on opposing sidewalls of the MOSFETs. The memory cell structure also includes a plurality of wordlines overlaying the double-gated vertical MOSFETs and in contact with the exposed gate conductor regions, and a plurality of bitlines that are orthogonal to the wordlines. Trench isolation regions are located adjacent to the rows of memory cells. The memory cell structure also includes a plurality of punch through stop regions located in the Si-containing substrate and self-aligned to the wordlines and bitlines. A portion of the punch through stop regions overlap each other under the bitlines and each region serves to electrically isolate adjacent buried-strap regions from each other.

Abstract: A metal oxide semiconductor (MOS) device includes a silicon substrate, source and drain regions having a predetermined junction depth (dj) relative to the surface of the silicon substrate, and a gate region having a contoured channel region formed by a locally-oxidized silicon (LOCOS) structure grown to a predetermined thickness. The contoured channel region has a substantially flat surface, extending into the silicon substrate by a predetermined depth (dc), and contoured edges. The depth (dc) of the substantially flat surface of the contoured channel region is greater than or equal to the depth of the junction depth (dj) of the source and drain regions, such that the contoured channel region is lower than or equal to the source and drain regions relative to the surface of the silicon substrate. The lower depth of the contoured channel region relative to the source and drain regions decouples shallow junction requirements from the channel length scaling.

Abstract: A nonvolatile memory cell comprising a pair of spaced apart shallow trench isolation regions formed in a substrate and defining a substrate active region. A tunnel dielectric is formed on the substrate active region. A floating gate is formed on the tunnel dielectric and is self aligned between the spaced apart shallow trench isolation regions. A dielectric layer is formed on the floating gate and a control gate formed on the dielectric layer. A source region and a drain region are formed in the substrate active region on opposite sides of the floating gate.

Abstract: A gate insulating film is provided on a channel region. A gate electrode includes a lower part and an upper part. The lower part has a lower surface and sides, and the upper part has a lower surface. The lower surface of the lower part contacts the gate insulating film. The upper part is longer than the lower part in a lengthwise direction of a gate electrode. The first insulating film is interposed between the lower surface of the upper part of the gate electrode and a semiconductor substrate. The first insulating film surrounds at least the sides of the lower part of the gate electrode, which face drain and source regions, and having parts interposed between the lower surface of the upper part of the gate electrode and the semiconductor substrate and made thicker than the other parts.

Abstract: Divot fill methods of incorporating thin SiO2 spacer and/or annealing caps into a complementary metal oxide semiconductor (CMOS) processing flow are provided. In accordance with the present invention, the divot fill processes provide a means for protecting the exposed surfaces of the thin SiO2 spacer and/or annealing cap such that those surfaces are not capable of being attacked by a subsequent silicide pre-cleaning step. CMOS devices including thin SiO2 spacer and/or annealing caps whose surfaces are protected such that those surfaces are not capable of being attacked by a subsequent silicide pre-cleaning or other process steps are also provided.

Abstract: A semiconductor device comprising a drain region, a body region overlying the drain region and defining an upper surface, source regions extending from adjacent the upper surface of the body region towards the drain region, and a series of indentations extending into and through the body region such that lower side walls of each indentation are defined by portions of the body and drain regions and upper side walls of each indentation are defined by the source region. A lower portion of each indentation is filled with a gate region isolated from the side walls by a first insulating layer and covered by a second insulating layer. A source conductor overlies the upper surface and is electrically connected to the source regions, and a gate conductor is electrically connected to each gate region. The source conductor extends into all upper portion of each indentation to contact portions of the upper side Walls of the indentation which are defined by the source regions.

Abstract: The present invention provides a semiconductor device and a method of manufacture therefor. The semiconductor device includes a semiconductor substrate having a gate formed there over. The semiconductor device further includes an isolation region having at least one source/drain region formed there over.

Abstract: There are provided a vertical MOS transistor in which a high frequency characteristic is improved by reducing a feedback capacitance, and a method of manufacturing the same. When a gate voltage is applied to a gate electrode, a channel is formed in a p− epitaxial growth layer along a trench, and an electron current flows from an n+ drain layer to the p− epitaxial growth layer. In this case, an overlapping area between a gate and the drain layer through a gate oxide film is smaller than prior art, and the capacitance between the gate and the drain layer is smaller than the prior art. Thus, the feedback capacitance becomes small and the high frequency characteristic is improved.

Abstract: A trench DMOS device having improved breakdown characteristics. The trench DMOS device has a gate oxide layer which has a substantially flattened thick portion in the bottom of the trench and which is relatively thinner on the sidewalls. In greater detail, the trench DMOS device comprises a trench formed in a semiconductor substrate, said trench having sidewalls and a bottom, a gate polysilicon layer filled into said trench, and a gate oxide layer formed between said gate polysilicon layer and the sidewalls and bottom of said trench, wherein a bottom part of said gate oxide layer has a thickness greater than both sidewall parts thereof, and a central region of said bottom part is substantially flattened with a thickness greater than boundary regions thereof. Also disclosed is a novel method of fabricating a trench DMOS device.

Abstract: In a memory cell contained in a memory circuit portion of a system LSI, a gate electrode of an N-channel MOS transistor and a cell plate electrode of a capacitor are formed by the same interconnection layer. Thus, the system LSI can be produced using the CMOS logic process alone so that the system LSI including the memory circuit portion having a relatively large capacity can be produced at a low cost.

Abstract: A power MOSFET has a plurality of spaced rows of parallel coextensive trenches. The trenches are lined with a gate oxide and are filled with a single common layer of conductive polysilicon which extends into each trench and overlies the silicon surface which connects adjacent trenches. The source contact is made at a location remote from the trenches and between the rows of trenches. The trenches are 1.8 microns deep, are 0.6 microns wide and are spaced by about 0.6 microns or greater. The trench is from 0.2 to 0.25 microns deeper than the channel region. The device has a very low figure of merit and is useful especially in low voltage circuits.

Abstract: A trench-gate type transistor has a gate insulating film formed on an inner wall of a trench. The gate insulating film is composed of a first portion disposed on a side wall portion of the trench and a second portion disposed on upper and bottom portions of the trench. The first portion is composed of a first oxide film, a nitride film, and a second oxide film. The second portion is composed of only an oxide film and has a thickness thicker than that of the first portion. Accordingly, electric field concentration on upper and lower corner portions of the trench can be mitigated, and a decrease in withstand voltage at that portions can be prevented.

Abstract: There is disclosed a MIS field effect transistor, comprising a silicon substrate, an insulating film formed over the silicon substrate and containing silicon and at least one of nitrogen and oxygen, a metal oxynitride film formed on the insulating film and containing at least one kind of metal atom selected from the group consisting of zirconium, hafnium and a lanthanoide series metal, the metal oxynitride film containing nitrogen atom not bonding with the metal atom without metal-nitrogen bond at the density of higher than 1019/cm3, and a gate electrode formed on the metal oxynitride film.

Abstract: A MIS type semiconductor device comprises a semiconductor layer provided with a recess portion having a side wall with an obtuse angle at least at a portion of the recess portion, a gate electrode formed over a bottom surface of the recess portion, with a gate insulating film interposed, a source region and a drain region formed on sides of the gate electrode with an insulating film interposed, such that boundary planes between the source region and the drain region, on one hand, and the insulating film, on the other hand, are formed in the semiconductor layer at an angle to a surface of the semiconductor layer, and wiring portions for contact with the surface of the semiconductor layer.

Abstract: A semiconductor device with a SOI structure comprises; a SOI substrate having a buried insulating film and a first conductivity type surface semiconductor layer on the buried insulating film; second conductivity type source and drain regions formed in the surface semiconductor layer; and a gate electrode formed over a first conductivity type channel region between the source and drain regions via a gate insulating film, wherein the source and drain regions are thinner than the surface semiconductor layer, and the channel region in the surface semiconductor layer has a first conductivity type high-concentration impurity diffusion region whose first conductivity type impurity concentration is higher than that in a surface of the channel region and which is adjacent to the buried insulating film.

Abstract: A process for fabricating a tapered trench on a silicon substrate. The process comprises the steps of forming an initial trench in the substrate and implanting nitrogen ions on the initial trench side walls. More nitrogen ions are implanted adjacent the exposed surface of the substrate than adjacent the trench bottom. Finally, the initial trench side walls are oxidized to create the tapered shape.

Abstract: The breakdown voltage of a semiconductor device, such as a transistor fabricated in a device region in and abutting the surface of a semiconductor body with a field oxide surrounding the device region, is improved by etching the field oxide abutting the device region to reduce the thickness thereof to about 0.6-1.4 &mgr;m and then forming a field plate in the recessed field oxide which is capacitively coupled to the underlying semiconductor body. The field plate can be floating, connected to a voltage potential, or connected to the semiconductor device.

Abstract: A semiconductor device of the invention integrates a plurality of types of MOSFETs formed on its substrate in such a configuration that a gate insulator film 51 of a core-purpose MOSFET is thinner than a gate insulator film 12 of an I/O-purpose MOSFET and also a poly-silicon film 8 which is to act as a gate electrode of the core-purpose MOSFET is thinner in thickness than a poly-silicon 13 which is to act as a gate electrode of the I/O-purpose MOSFET.

Abstract: A semiconductor device (10) has a substrate (20) with a surface (26) for defining a trench (34). A control electrode (45) is disposed at the surface to activate a conduction path (50) along a sidewall (36) of the trench with a control signal (VGATE). A dielectric layer (32, 35) is formed between the sidewall and the control electrode to have a first width (WGS) adjacent to the surface and a second width (WGC) smaller than the first width adjacent to the conduction path.

Abstract: A device and method for fabricating a gate structure are disclosed. A first conductive material is deposited in a trench formed in a substrate and the first conductive material is recessed to a level below a top surface of the substrate in the trench. A dielectric layer is conformally deposited in contact with the first conductive material in the trench and in contact with sidewalls of the trench. A hole is formed in the dielectric layer to expose the first conductive layer, and the hole is filled with a conductive material. A gate stack is formed over the trench such that an electrical connection is made to the first conductive layer in the trench by employing the conductive material through the dielectric layer.

Abstract: A non-volatile semiconductor memory manufacturing method, according to the present invention, is comprised of the process steps that follow. Device isolating layers are formed on predetermined places in a cell region. A layer of floating gate material is deposited next, all over the substrate. Either all the layer of floating electrode material, deposited on the device isolating layers or a part of it, is removed next, by etching, in order to form ditches. To fill the ditches, a first insulation layer is formed next, all over the cell region. A predetermined part of the first insulation layer is removed next, by etching, so the layer of floating electrode material is exposed. Thereafter, the ditches are filled in, on top of the device isolating oxide layers, with insulation layers. A second insulation layer is formed next, all over the cell region. Thereafter, electrode material layers and are deposited on the surface.

Abstract: A horizontal, insulated gate field effect transistor of the present invention includes a semiconductor substrate of first conductivity. A well region of second conductivity is formed on the surface of the semiconductor substrate. A source region of first conductivity is formed in the well region. A source electrode is connected to the source region. A drain region of first conductivity is formed in the well region. A gate dielectric is formed on the well region and extends over the source region and drain region. A gate electrode is formed on the gate dielectric. The drain electrode is connected to the well region at a position other than the drain region.

Abstract: A field-effect-controllable vertical semiconductor component, and a method for producing the same, include a semiconductor body having at least one drain region of a first conduction type, at least one source region of the first conduction type, at least one body region of a second conduction type between the drain regions and the source regions, and at least one gate electrode insulated from the entire semiconductor body by a gate oxide. A gate terminal and a drain terminal are located on a front side of the wafer, and a source terminal is located on a rear side of the wafer. A monolithically integrated half bridge with a low-side switch and a high-side switch includes the field-effect-controllable vertical semiconductor component and a conventional field-effect-controllable vertical semiconductor component.

Abstract: A cellular trench-gate field-effect transistor comprises a field plate (38) on dielectric material (28) in a perimeter trench (18). The dielectric material (28) forms a thicker dielectric layer than the gate dielectric layer (21) in the array trenches (11). The field plate (38) is connected to the source (3) or trench-gate (31) of the transistor and acts inwardly towards the cellular array rather than outwardly towards the body perimeter (15) because of its presence on the inside wall 18a of the trench (18) without acting on any outside wall (18b). The array and perimeter trenches (11,18) are sufficiently closely spaced, and the intermediate areas (4a, 4b) of the drain drift region (4) are sufficiently lowly doped, that the depletion layer (40) formed in the drain drift region (4) in the blocking state of the transistor depletes the whole of these intermediate areas between neighbouring trenches at a voltage less than the breakdown voltage.

Abstract: An improved trench MOS-gated device comprises a monocrystalline semiconductor substrate on which is disposed a doped upper layer. The upper layer includes at an upper surface a plurality of heavily doped body regions having a first polarity and overlying a drain region. The upper layer further includes at its upper surface a plurality of heavily doped source regions having a second polarity opposite that of the body regions A gate trench extends from the upper surface of the upper layer to the drain region and separates one source region from another. The trench has a floor and sidewalls comprising a layer of dielectric material and contains a conductive gate material filled to a selected level and an isolation layer of dielectric material that overlies the gate material and substantially fills the trench. The upper surface of the overlying layer of dielectric material in the trench is thus substantially coplanar with the upper surface of the upper layer.

Abstract: Described are structures for a device with a controllable dummy layer which can provide a low controllable trigger voltage and can be used as a first triggered device in ESD protection networks. A controllable dummy layer diode is provided which is structured as a butting diode with a dummy polysilicon layer above the butting region. The dummy polysilicon layer functions as an STI block to remove the STI between the n+ and p+ regions of the diode. In one embodiment the diode has the function of a controllable gate with a punchthrough-like-trigger, in which a capacitor-couple circuit couples a portion of the ESD voltage into the gate of the diode to provide a gate voltage. By changing the channel length under the gate of the diode as well as the gate voltage, the reverse-biased voltage of the diode is readily adjusted to a predetermined level. In a second embodiment the p+ region of the diode overlaps the n+ region turning the diode into a zener diode.

Abstract: A non-volatile semiconductor memory manufacturing method, according to the present invention, is comprised of the process steps that follow. Device isolating layers are formed on predetermined places in a cell region. A layer of floating gate material is deposited next, all over the substrate. Either all the layer of floating electrode material, deposited on the device isolating layers or a part of it, is removed next, by etching, in order to form ditches. To fill the ditches, a first insulation layer is formed next, all over the cell region. A predetermined part of the first insulation layer is removed next, by etching, so the layer of floating electrode material is exposed. Thereafter, the ditches are filled in, on top of the device isolating oxide layers, with insulation layers. A second insulation layer is formed next, all over the cell region. Thereafter, electrode material layers and are deposited on the surface.

Abstract: A semiconductor device has a construction in which a gate dielectric film is formed on the surface of a semiconductor substrate having source regions and drain regions, a plurality of FG (Floating Gates) are formed on the gate dielectric film, an intergate dielectric film is formed on the FG, and CG (Control Gates) are formed on the intergate dielectric film. Mounds are formed on both sides of the FG. An interlayer dielectric film is formed between the gate dielectric film and the intergate dielectric film and covering these mounds. The FG are constituted by upper FG and lower FG, and the upper FG are formed to spread toward the areas where the mounds are formed and cover a portion of the interlayer dielectric film. The gate dielectric film is formed in a shape that does not rise in a direction that is substantially perpendicular to the surface of the semiconductor substrate at least above the upper FG.

Abstract: A gate electrode is provided via a gate insulating film formed between the source and drain regions on a semiconductor substrate, wherein the sidewall of the gate electrode excluding the exposed part formed at the upper part thereof facing the source and drain regions is covered with a sidewall insulating film, and an epitaxial film is formed on the exposed part of the sidewall of the gate electrode but not formed on a top surface of the gate electrode. An element isolation region formed on the semiconductor substrate is composed of a first insulating film formed in the semiconductor substrate and a second insulating film which is formed inside the first insulating film and has a lower epitaxial growth rate than that of the first insulating film, and the surface of the source and drain regions is covered with a silicon layer, part of which runs onto the surface of the first insulating film.

Abstract: At an edge portion of an FS gate electrode (10) beneath a side wall oxide film (106), an FS gate oxide film (101) is thicker. Relative to a surface of a silicon substrate (SB) beneath the FS gate oxide film (101), other surface of the silicon substrate (SB) is retracted. Thus, a MOS transistor with field-shield isolation structure and a method for manufacturing the same can be provided with higher reliability of the gate oxide film.

Abstract: In a trenched MOS gate power device having a trenched MOS gate structure, a gate insulating film is formed on the walls of trenches to extend onto a major surface of a semiconductor substrate, and gates are formed so as to fill up the trenches and to extend onto the gate insulating film on the major surface of the semiconductor substrate. The gate insulating film is formed so that the thickness of a portion thereof formed on the major surface of the semiconductor substrate is greater than that of a portion thereof formed on the walls of the trenches to narrow portions of the gates corresponding to the tops of the trenches. Thus, the characteristics of a gate insulating film formed on the walls of trenches are improved.

Abstract: A method for fabricating high voltage semiconductor devices having a gradient doping of a drift region which comprises N-well 1 and N-well 2 with two different doping densities. This method results in the lift in device's current drive capability and as well as its breakdown voltage. The method further comprises forming a buried spacer oxide, serving as a point of exertion for the edges of the buried gate electrode. And finally, the extension in channel length and the placement of both the channel and drift regions change to vertical direction, all of those result in a greater reduction in the occupied chip area. These advantages attribute to the formation of a buried gate electrode by trench etching method.

Abstract: A high-voltage and low on-resistance semiconductor device incorporates a trench structure that provides improved switching characteristics. In a preferred embodiment, a Trench Lateral Power MISFET is provided having a gate, channel and drift regions that are built on the side-walls of the trench. The process used to form the MISFET involves a self-aligned trench bottom contact hole to contact a source provided at the bottom of the trench to achieve minimum pitch and very low on-resistance. An example of a MISFET with 80 V breakdown voltage having a cell pitch of 3.4 microns is disclosed in which an on-resistance of 0.7 m&OHgr;-cm2 is realized. The switching characteristics of the MISFET are twice as good as that of prior MISFET device structures.

Abstract: Lanthanum oxide-based gate dielectrics are provided for integrated circuit field effect transistors. The gate dielectrics may include lanthanum oxide, preferably amorphous lanthanum oxide and/or an alloy of lanthanum oxide and silicon oxide, such as lanthanum silicate (La2SiO5). Lanthanum oxide-based gate dielectrics may be fabricated by evaporating lanthanum on a silicon surface of an integrated circuit substrate. The lanthanum may be evaporated in the presence of oxygen. Lanthanum and silicon may be co-evaporated. An anneal then may be performed. Lanthanum oxide-based dielectrics also may be used for integrated circuit capacitors.

Abstract: There are provided a vertical MOS transistor in which a high frequency characteristic is improved by reducing a feedback capacitance, and a method of manufacturing the same. When a gate voltage is applied to a gate electrode, a channel is formed in a p− epitaxial growth layer along a trench, and an electron current flows from an n+ drain layer to the p− epitaxial growth layer. In this case, an overlapping area between a gate and the drain layer through a gate oxide film is smaller than prior art, and the capacitance between the gate and the drain layer is smaller than the prior art. Thus, the feedback capacitance becomes small and the high frequency characteristic is improved.

Abstract: The present invention aims to provide a semiconductor device in which a satisfactory breakdown voltage can be obtained without increasing its chip size, and a method of manufacturing the same. A first electrode layer and a second electrode layer are formed. An inorganic type silicon oxide film is formed so as to cover first and second electrodes. An organic type silicon oxide film is formed on a surface of inorganic type silicon oxide film above a portion of a surface of first electrode layer. At a region of inorganic type silicon oxide film where organic type silicon oxide film is not formed, a through hole is formed, exposing a portion of a surface of second electrode layer. An interconnection layer is formed so as to be in contact with second electrode layer via through hole and opposing first electrode layer with inorganic and organic type silicon oxide films therebetween.

Abstract: Self-aligned contacts to the source and drain regions of a MOS device are formed by selectively removing portions of sidewall spacers from polysilicon source and drain electrodes. Metal silicide layers are then formed in contact with the exposed polysilicon portions and extending over and in contact with respective source and drain regions formed in a semiconductor substrate surface.

Abstract: A structure for forming a laterally diffused metal-oxide semiconductor is disclosed. The structure will include the following portions. They are a semiconductor layer with a conductivity type, a field insulating region into the semiconductor layer, a gate electrode formed over at least a portion of a channel region and insulated therefrom. The first drain region without an oxide top surface is formed beside one side of the gate electrode into the semiconductor layer. A second drain region is formed in the semiconductor layer. Also, a lightly doped portion borders the channel region and the neighbouring field insulating region. The main portion neighbors the oxide top surface and is spaced from the channel region by the lightly doped portion. The main portion has a second doping concentration that is less than the first doping concentration. The deep portion has a third doping concentration that is less than the second doping concentration.

Abstract: In a trench-gated MOSFET, a lightly doped drift region of the N-type drain lies in the mesa between the trenches. The gate is doped with N-type material so that depletion regions are formed in the drift region when the gate voltage is equal to zero. The depletion regions merge at the center of the mesa, pinching off the flow of current when the device is turned off. This current-pinching effect allows the P-type body region to be made shallower and doped more lightly than usual without creating a punchthrough problem, because the barrier represented by the depletion regions adds to the normal current blocking capability of the PN junction between the body and drain regions. When the device is turned on by biasing the gate to a positive voltage, a low resistance accumulation layer forms in the drift region adjacent the trenches.

Abstract: The resistance to current flow through an MOS-gated semiconductor device is reduced by providing a high conductivity region in the path of current through the drain region, but so positioned relative to the p-n voltage blocking junction of the device so as not to adversely affect the voltage blocking capability of the p-n junction. In one embodiment, the drain region is made of higher than normal electrical conductivity, but a diffused, graded p-n junction is provided for extending the low conductivity portion of the drain region bordering the p-n junction further than usual into the drain region.

Abstract: A method is provided for forming buried source line in semiconductor devices. It is known in the art to form buried contacts on the surface of a semiconductor substrate. The present invention discloses a method of fabricating a semiconductor device, particularly a memory cell, having both the source region and the source line buried within the substrate. The source line is formed in a trench in the substrate over the source region. The trench walls are augmented with voltage anti-punch-through protection. The trench also provides the attendant advantages of extended sidewall area, smaller sheet resistance, and yet smaller cell area, therefore, smaller chip size, and faster access time as claimed in the embodiments of this invention. The buried source disclosed here is integrated with source line which is also buried within the substrate.

Abstract: This invention discloses a DMOS power device supported on a substrate. The DOS power device includes a drain of a first conductivity type disposed at a bottom surface of the substrate. The DMOS power device further includes a gate disposed in a trench opened from a top surface of the substrate, the gate having a polysilicon layer filling the trenches padded by a double gate-oxide structure. The double gate-oxide structure includes a thick-oxide-layer covering walls of the trench below an upper portion of the trench and a thin-gate-oxide covering walls of the upper portion of the trench thus defining a champagne-glass shaped gate in the trench. The DMOS power device further includes a source region of the first conductivity type disposed in the substrate surrounding a top portion of the trench. The DMOS power device further includes a body region of a second conductivity type disposed in the substrate surrounding the trench and encompassing the source region.

Abstract: A method for manufacturing a semiconductor device that includes dual gate oxide layers made of two dielectric layers of varying thickness on a single wafer. In an example embodiment, a semiconductor structure is fabricated by providing a first layer of a dielectric over a semiconductor material and covering the first layer with a protective second dielectric layer adapted to mask the first layer. The first and second layers are then removed over a region of the semiconductor material while the second layer is used to protect the first layer, therein leaving the region of semiconductor material substantially exposed. A third layer of dielectric material is formed over the first and second layers and the adjacent exposed semiconductor material region; a gate material is then formed over the third dielectric layer. Finally, an etching step etches through the gate material and underlying layers to the semiconductor material to form a thick gate region and a thin gate region.

Abstract: A semiconductor device, which can have a uniform film on open ends of trenches by using materials having a different oxidation rate, and a fabrication method thereof are provided. The semiconductor device having trenches configured to have open ends covered with an oxidation film made of a material having an oxidation rate faster than that of a semiconductor substrate and a fabrication method thereof are provided.

Abstract: An ESD protection circuit with buried diffusion and internal overlap coupling capacitance is used to lower trigger voltage and create a compact protection circuit area. This protection circuit can be applied to memory and logic products and can be employed in power bus, input, and output pins to protect against ESD. The manufacturing process of this high-performance protection circuit is compatible with non-volatile memory process without an additional mask layer step.

Abstract: An integrated circuit and a method of making a transistor thereof are provided. In one aspect, the integrated circuit includes a substrate and a plurality of transistors positioned on a plurality of active areas of the substrate. Each of the transistors has a doped region positioned in the substrate, an insulating layer positioned in a tapered trench in the substrate that extends through and sub-divides the doped region into a first source/drain region and a second source/drain region. The insulating layer is channel-shaped with a base, a first upwardly sloping sidewall and a second upwardly sloping sidewall. A gate electrode is positioned on the insulating layer. The channel-shaped gate dielectric layer requires less horizontal substrate area, enabling higher packing density for a given substrate. The sloped sidewalls double as spacers, enabling process simplification.

Abstract: A MOSFET has a buried shield plate under the gate and over the drain with the gate being formed on the periphery of the buried shield plate as a self-aligned structure with minimal or no overlap of the gate over the shield plate. Methods of fabricating the MOSFET are disclosed.

Abstract: A semiconductor device, which is characterized in that a trench (12) is formed in a silicon substrate (11), an element isolation film (1) is formed on an inner surface of said trench (12), and a drain region (7), a channel region (8) and a source region (9) are arranged vertically in a region encircled by said element isolation film (1); and that a gate insulating film (2) is formed inside of these regions (7, 8 and 9) and a gate electrode (4) is formed on an inner side portion of said gate insulating film (2), while a drain electrode (5) or source electrode (13) is formed on an outer side portion of said gate insulating film (2).

Abstract: The semiconductor component has a small forward voltage and a high blocking ability. At least one drift path suitable for taking up voltage is formed in a semiconductor body between two electrodes that are arranged at a distance from one another. At least one semi-insulating layer is provided parallel to the drift path. The semi-insulating layer leads to a linear rise in the potential between the two electrodes when a reverse voltage is applied.

Abstract: Power semiconductor devices having tapered insulating regions include a drift region of first conductivity type therein and first and second trenches in the substrate. The first and second trenches have first and second opposing sidewalls, respectively, that define a mesa therebetween into which the drift region extends. An electrically insulating region having tapered sidewalls is also provided in each of the trenches. The tapered thickness of each of the electrically insulating regions enhances the degree of uniformity of the electric field along the sidewalls of the trenches and in the mesa and allows the power device to support higher blocking voltages despite a high concentration of dopants in the drift region. In particular, an electrically insulating region lines the first sidewall of the first trench and has a nonuniform thickness Tins(y) in a range between about 0.5 and 1.