Abstract: A nonvolatile semiconductor memory device includes a substrate, a central structure, a second gate insulating film, a floating gate, and a control gate. The substrate has a trench. The central structure is formed so as to be embedded in the trench and protruded from the substrate. The second gate insulating film is formed on the substrate so as to be contact with the central structure. The floating gate is formed on the second gate insulating film. The control gate is formed so as to cover the floating gate through a insulating film;. The central structure includes an assistant gate and a first gate insulating film which is formed such that the assistance gate is surrounded with the first gate insulating film. The floating gate is formed in a side wall shape on the side surface of the central structure.

Abstract: Techniques for forming devices, such as transistors, having vertical junction edges. More specifically, shallow trenches are formed in a substrate and filled with an oxide. Cavities may be formed in the oxide and filled with a conductive material, such a heavily doped polysilicon. Vertical junctions are formed between the polysilicon and the exposed substrate at the trench edges such that during a thermal cycle, the heavily doped polysilicon will out-diffuse doping elements into the adjacent single crystal silicon advantageously forming a diode extension having desirable properties.

Abstract: Conventional power MOSFETs enables prevention of an inversion in a surrounding region surrounding the outer periphery of an element region by a wide annular layer and a wide sealed metal. Since, resultantly, the area of the surrounding region is large, increase in the element region has been restrained. A semiconductor device is hereby provided which has an inversion prevention region containing an MIS (MOS) structure. The width of polysilicon for the inversion prevention region is large enough to prevent an inversion since the area of an oxide film can be increased by the depth of the trench. By this, leakage current can be reduced even though the area of the region surrounding the outer periphery of the element region is not enlarged. In addition, since the element region is enlarged, on-state resistance of the MOSFET can be reduced.

Abstract: The present invention relates to a high voltage transistor and method of manufacturing the same.

Abstract: A trench type power semiconductor device includes proud gate electrodes that extend out of the trenches and above the surface of the semiconductor body. These proud gate electrodes allow for making ultra-shallow source regions within the semiconductor body using, for example, a low temperature source drive. In addition, a method for manufacturing the trench type power semiconductor device includes a low temperature process flow once the gate electrodes are formed.

Abstract: In the case of the semiconductor component (1) according to the invention, the source regions (S), the body regions (B) and, if appropriate, the body contact regions (Bk) are in each case arranged in mesa regions (M) of adjacent trenches (30). In the edge region (R) of the cell array (Z) the insulation (GOX, FOX) of the underlying trench structures (30) by an insulating oxide layer (FOX) is comparatively thick and formed in the form of a field oxide (FOX) or thick oxide (FOX).

Abstract: A semiconductor device which includes a laterally extending stack of laterally adjacent conductive semiconductor regions formed over a support surface of a substrate, and a method for fabricating the device.

Abstract: A nonvolatile memory device is provided which includes a floating gate having a lower portion formed in a trench defined in a surface of a substrate and an upper portion protruding above the surface of the substrate from the lower portion. A gate insulating layer is formed along an inner wall of the trench and interposed between the trench and the lower portion of the floating gate. A source region is formed in the substrate adjacent a first sidewall of the trench. A control gate having a first portion is formed over the surface of the substrate adjacent a second sidewall of the trench, and a second portion is formed over the upper portion of the floating gate and extending from the first portion. The first sidewall of the trench is opposite the second sidewall of the trench.

Abstract: A field effect transistor includes a gate that is formed in a channel region of an active region defined on a substrate. A source is formed at a first surface portion of the active region that is adjacently disposed at a first side face of the gate. A drain is formed at a second surface portion of the active region that is opposite to the first surface portion with respect to the gate. The drain has a protruded portion that is protruded from a surface portion of the substrate.

Abstract: In a trench MOSFET, the lower portion of the trench contains a buried source electrode, which is insulated from the epitaxial layer and semiconductor substrate but in electrical contact with the source region. When the MOSFET is in an “off” condition, the bias of the buried source electrode causes the “drift” region of the mesa to become depleted, enhancing the ability of the MOSFET to block current. The doping concentration of the drift region can therefore be increased, reducing the on-resistance of the MOSFET. The buried source electrode also reduces the gate-to-drain capacitance of the MOSFET, improving the ability of the MOSFET to operate at high frequencies. The substrate may advantageously include a plurality of annular trenches separated by annular mesas and a gate metal layer that extends outward from a central region in a plurality of gate metal legs separated by source metal regions.

Abstract: A method of manufacturing an insulating layer that ensures reproducibility across like manufacturing apparatus. The insulating layer is formed on the substrate by (a) flowing an oxidizing gas at an oxidizing gas flow rate, (b) flowing a first carrier gas at a first carrier gas flow rate while carrying a first impurity including boron flowing at a first impurity flow rate, (c) flowing a second carrier gas at a second carrier gas flow rate while carrying a second impurity including phosphorus flowing at a second impurity flow rate, and (d) flowing a silicon source material at a silicon source flow rate. The second carrier gas flow rate is greater than the first carrier gas flow rate.

Abstract: A semiconductor device includes a substrate including a semiconductor and a trench, and an electrically rewritable semiconductor memory cell on the substrate, the semiconductor memory cell comprising a charge storage layer including an upper surface and a lower surface, an area of the lower surface being smaller than an area of the upper surface, and at least a part of the charge storage layer being provided in the trench, first insulating layer between the lower surface of the charge storage layer and a bottom surface of the trench, second insulating layer between a side surface of the trench and a side surface of the charge storage layer and between the side surface of the trench and a side surface of the first insulating layer, third insulating layer on the charge storage layer, and a control gate electrode on the third insulating layer.

Abstract: The present invention provides a thin-film transistor that is formed by using a patterning method capable of forming a semiconductor channel layer in sub-micron order and a method for manufacturing thereof that provides a thin-film transistor with a larger area, and suitable for mass production. These objects are achieved by a thin-film transistor formed on a substrate 1 with a finely processed concavoconvex surface 2, in which a source electrode and a drain electrode are formed on adjacent convex portions of the concavoconvex surface 2, with a channel and a gate being formed on a concave area between the convex portions. A gate electrode 5, a gate insulating film 6 and a semiconductor channel layer 7 are laminated in this order on the concave area from the bottom surface of the concave portion toward the top surface.

Abstract: A trench-structure semiconductor device is highly reliable and has an increased resistance to hydrofluoric acid cleaning or other cleaning of an insulation film between a gate electrode, which is embedded in a trench, and source electrode. In a trench-structure semiconductor device, a silicon nitride film is over the gate electrode and embedded up to a point close to the open edge on the inside of trench. A source electrode is formed in contact with the surface of the silicon nitride film and the surface of the source region.

Abstract: A multi-level memory cell including a substrate, a tunneling dielectric layer, a charge-trapping layer, a top dielectric layer, a gate and a pair of source/drain regions is provided. The tunneling dielectric layer, the charge-trapping layer and the top dielectric layer are sequentially formed between the substrate and the gate. The top dielectric layer has at least two portions, and the top dielectric layer in each portion has a different thickness. The source/drain regions are disposed in the substrate on each side of the gate. Since the thickness of the top dielectric layer in each portion is different, the electric field strength between the gate and the substrate when a voltage is applied to the memory cell are different in each portion. With the number of charges trapped within the charge-trapping layer different in each portion, a multiple of data bits can be stored within each memory cell.

Abstract: A trench IGBT is disclosed which meets the specifications for turn-on losses and radiation noise. It includes a p-type base layer divided into different p-type base regions by trenches. N-type source regions are formed in only some of the p-type base regions. There is a gate runner in the active region of the trench IGBT. Contact holes formed in the vicinities of the terminal ends of the trenches and on both sides of the gate runner electrically connect some of the p-type base regions that do not include source regions to an emitter electrode. The number N1 of p-type base regions that are connected electrically to the emitter electrode and the number N2 of p-type base regions that are insulated from the emitter electrode are related with each other by the expression 25?{N1/(N1+N2)}×100?75.

Abstract: An object of the present invention is to provide a MOS transistor of a new structure and a method of manufacturing the same that is capable of easily fabricating a high integration density device by overcoming photolithography limitations. The object of the present invention is accomplished by a MOS transistor, including a semiconductor substrate having a projection in which the width of an upper portion thereof is larger than that of a lower portion thereof; an isolating layer formed in the middle of substrate of the projection; first and second drain regions formed within the surface of the substrate of the projection; first and second source regions formed within the surface of the substrate on both sides of the projection; a gate insulating layer formed on the entire surface of the substrate; and first and second gates formed on the gate insulating layer on both sides of the substrate of the projection.

Abstract: A semiconductor device includes a semiconductor substrate, a cell region in a surface portion of the substrate for operating as a transistor, a gate lead wiring region having a gate lead pattern on the substrate, a trench in the surface portion of the substrate extending from the cell region to the gate lead wiring region, an oxide film on an inner surface of the trench, and a gate electrode in the trench insulated with at least the oxide film from the substrate. A speed of formation of a main portion of the sidewalls of the trench at the gate lead wiring region is greater than that of a main portion of the sidewalls of the trench at the cell region, so that a thickness of the oxide film at the gate lead wiring region is greater than that at the cell region.

Abstract: Embodiments of the invention relate to a fabrication method of an electronic device, more particularly to a fabrication method of a power device in which an oxide layer at the bottom of the trench is provided to reduce Miller capacitance and further reduce RC delay. In one embodiment, a method for forming an oxide layer at the bottom of a trench comprises providing a first substrate with at least one trench therein; forming a first oxide layer on the bottom and sidewalls of the trench; removing the first oxide layer at the bottom of the trench; and forming a second oxide layer at the bottom of the trench.

Abstract: In one embodiment of the invention, a semiconductor device set includes at least one trench-typed MOSFET and a trench-typed termination structure. The trench-typed MOSFET has a trench profile and includes a gate oxide layer in the trench profile, and a polysilicon layer on the gate oxide layer. The trench-typed termination structure has a trench profile and includes an oxide layer in the trench profile. A termination polysilicon layer with discrete features separates the termination polysilicon layer. An isolation layer covers the termination polysilicon layer and filling the discrete features. The trench-typed MOSFET and the trench-typed termination structure may be formed on a DMOS device including an N+ silicon substrate, an N epitaxial layer on the N+ silicon substrate, and a P epitaxial layer on the N epitaxial layer. The trench profiles of the trench-typed MOSFET and of the trench-typed termination structure may penetrate through the P epitaxial layer into the N epitaxial layer.

Abstract: In a trench-gated MOSFET including an epitaxial layer over a substrate of like conductivity and trenches containing thick bottom oxide, sidewall gate oxide, and conductive gates, body regions of the complementary conductivity are shallower than the gates, and clamp regions are deeper and more heavily doped than the body regions but shallower than the trenches. Zener junctions clamp a drain-source voltage lower than the FPI breakdown of body junctions near the trenches, but the zener junctions, being shallower than the trenches, avoid undue degradation of the maximum drain-source voltage. The epitaxial layer may have a dopant concentration that increases step-wise or continuously with depth. Chained implants of the body and clamp regions permits accurate control of dopant concentrations and of junction depth and position. Alternative fabrication processes permit implantation of the body and clamp regions before gate bus formation or through the gate bus after gate bus formation.

Abstract: A DMOS device having a trench bus structure thereof is introduced. The trench bus structure comprises a field oxide layer formed on a P substrate, and a trench extending from an top surface of the field oxide layer down to a lower portion of the P substrate. A gate oxide layer and a polysilicon bus are formed to fill the trench as a main portion of the bus structure. In addition, an isolation layer and a metal line are formed atop the polysilicon bus and the field oxide layer. An opening is formed in the isolation layer to form connections between the polysilicon bus and the metal line. In specific embodiments, the bus trench and the gate trenches of the DMOS device are formed simultaneously, and the polysilicon bus and the gate electrode are formed simultaneously as well. Therefore, the bus structure is able to form the DMOS transistor without demanding any lithographic step for defining the position of the polysilicon bus.

Abstract: A vertical MOSFET includes a base region formed on a drain region and a source region formed in the base region. A trench is formed to extend from the surface of the source region and penetrate the source region and has depth to reach a portion near the drain region. A gate insulating film is formed on the side walls and bottom portion of the trench and the gate electrode is formed in the trench. The impurity concentration profile of the base region has a first peak in a portion near the interface between the source region and the base region and a second peak which is formed in a portion near the interface between the base region and the drain region and is lower than the first peak. The threshold voltage is determined based on the first peak and the dose amount is determined based on the second peak.

Abstract: A semiconductor device comprises: a first semiconductor layer of a first conductivity type; a second semiconductor layer of a second conductivity type; a trench; a thick gate insulating film; a thin gate insulating film; a gate electrode; and a semiconductor region of a second conductivity type. The second semiconductor layer is provided on the first semiconductor layer. The trench penetrates the second semiconductor layer and intrudes into the first semiconductor layer. The thick gate insulating film is provided on a inner wall of the trench below an upper surface of the first semiconductor layer. The thin gate insulating film is provided on the inner wall of the trench at a part upper than the thick gate insulating film. The gate electrode fills the trench. The semiconductor region of a second conductivity type is selectively formed to adjoin the trench and to project from a bottom surface of the second semiconductor layer into the first semiconductor layer.

Abstract: A trench MIS device is formed in a P-epitaxial layer that overlies an N-epitaxial layer and an N+ substrate. In one embodiment, the device includes an N-type drain-drift region that extends from the bottom of the trench to the N-epitaxial layer. Preferably, the drain-drift region is formed at least in part by fabricating spacers on the sidewalls of the trench and implanting an N-type dopant between the sidewall spacers and through the bottom of the trench. The drain-drift region can be doped more heavily than the conventional “drift region” that is formed in an N-epitaxial layer. Thus, the device has a low on-resistance. The device can be terminated by a plurality of polysilicon-filled termination trenches located near the edge of the die, with the polysilicon in each termination trench being connected to the mesa adjacent the termination trench. The polysilicon material in each termination trenches.

Abstract: A trench type power MOSgated device has a plurality of spaced trenches lined with oxide and filled with conductive polysilicon. The tops of the polysilicon fillers are below the top silicon surface and are capped with a deposited oxide the top of which is flush with the top of the silicon. Source regions of short lateral extent extend into the trench walls to a depth below the top of the polysilicon. A trench termination is formed having an insulation oxide liner covered by a polysilicon layer, covered in turn by a deposited oxide.

Abstract: A semiconductor device is provided that can be manufactured by a simpler process than a conventional lateral trench power MOSFET for use with an 80V breakdown voltage, and which has a lower device pitch and lower on-state resistance per unit area than a conventional lateral power MOSFET for use with a lower breakdown voltage than 80V. A gate oxide film is formed thinly along the lateral surfaces of a trench at a uniform thickness. Then, a gate oxide film is formed along the bottom surface of the trench by selective oxidation so as to be thicker than the gate oxide film on the lateral surfaces of the trench and so as to become progressively thicker from the edge of the bottom surface of the trench toward drain polysilicon.

Abstract: A method and apparatus for providing a meshed power and signal bus system on an array type integrated circuit that minimizes the size of the circuit. In a departure from the art, through-holes for the mesh system are placed in the cell array, as well as the peripheral circuits. The power and signal buses of the mesh system run in both vertical and horizontal directions across the array such that all the vertical buses lie in one metal layer, and all the horizontal buses lie in another metal layer. The buses of one layer are connected to the appropriate bus(es) of the other layer using through-holes located in the array. Once connected, the buses extend to the appropriate sense amplifier drivers. The method and apparatus are facilitated by an improved subdecoder circuit implementing a hierarchical word line structure.

Abstract: An improved n-channel integrated lateral DMOS (10) in which a buried body region (30), beneath and self-aligned to the source (18) and normal body diffusions, provides a low impedance path for holes emitted at the drain region (16). This greatly reduces secondary electron generation, and accordingly reduces the gain of the parasitic PNP bipolar device. The reduced regeneration in turn raises the critical field value, and hence the safe operating area.

Abstract: A semiconductor device having a memory region in which a memory cell array is formed of non-volatile memory devices arranged in a matrix of a plurality of rows and columns. Each of the non-volatile memory devices has: a word gate formed above a semiconductor layer with a gate insulating layer interposed; an impurity layer formed in the semiconductor layer; and control gates in the form of side walls formed along both side surfaces of the word gate. Each of the control gates consists of a first control gate and a second control gate adjacent to each other; the first control gate is formed on a first insulating layer which is a stack of a first silicon oxide film, a silicon nitride film, and a second silicon oxide film; and the second control gate is formed on a second insulating layer formed of a silicon oxide film.

Abstract: The invention provides a semiconductor memory device comprising a plurality of word lines, a plurality of bit lines, and a plurality of static memory cells each having a first, second, third, fourth, fifth, and sixth transistors. While each of channels of the first, second, third, and fourth transistors are formed vertical against a substrate of the semiconductor memory device. Each of semiconductor regions forming a source or a drain of the fifth and sixth transistors forms a PN junction against the substrate. According to another aspect of the invention, the SRAM device of the invention has a plurality of SRAM cells, at least one of which is a vertical SRAM cell comprising at least four vertical transistors onto a substrate, and each vertical transistor includes a source, a drain, and a channel therebetween aligning in one aligning line which penetrates into the substrate surface at an angle greater than zero degree.

Abstract: An improved NAND-type memory cell structure having improved reliability and endurance. Since a high risk area for oxide breakdown and/or current leakage exists in the tunnel oxide layer, source/drain overlap region, the present invention provides a NAND-type memory cell fabricated using controlled formation of the tunnel oxide layer.

Abstract: A gate electrode is provided via a gate insulating film formed between the source and drain regions on a semiconductor substrate, wherein the sidewall of the gate electrode excluding the exposed part formed at the upper part thereof facing the source and drain regions is covered with a sidewall insulating film, and an epitaxial film is formed on the exposed part of the sidewall of the gate electrode but not formed on a top surface of the gate electrode. An element isolation region formed on the semiconductor substrate is composed of a first insulating film formed in the semiconductor substrate and a second insulating film which is formed inside the first insulating film and has a lower epitaxial growth rate than that of the first insulating film, and the surface of the source and drain regions is covered with a silicon layer, part of which runs onto the surface of the first insulating film.

Abstract: A MOS transistor suitable for microscopic applications and a fabrication method thereof are disclosed. The fabrication method includes forming a trench by selectively etching a semiconductor substrate; forming a channel region consisting of a silicon layer with a predetermined width in the bottom of the trench and forming a gate oxide film on the channel region; forming a SiGe film on the gate oxide film and within the trench and burying the trench; forming a gate groove with a predetermined width to expose the gate oxide film by selectively etching the SiGe film; and forming a gate electrode by forming a silicon layer on the exposed gate oxide film such that the gate groove is buried.

Abstract: A method for making a power MOSFET includes forming a trench in a semiconductor layer, forming a gate dielectric layer lining the trench, forming a gate conducting layer in a lower portion of the trench, and forming a dielectric layer to fill an upper portion of the trench. Portions of the semiconductor layer laterally adjacent the dielectric layer are removed so that an upper portion thereof extends outwardly from the semiconductor layer. Spacers are formed laterally adjacent the outwardly extending upper portion of the dielectric layer, the spacers are used as a self-aligned mask for defining source/body contact regions.

Abstract: The present invention is a semiconductor device comprising a semiconductor body having a top surface and laterally opposite sidewalls formed on a substrate. A gate dielectric layer is formed on the top surface of the semiconductor body and on the laterally opposite sidewalls of the semiconductor body. A gate electrode is formed on the gate dielectric on the top surface of the semiconductor body and adjacent to the gate dielectric on the laterally opposite sidewalls of the semiconductor body.

Abstract: An LDMOS transistor and a bipolar transistor with LDMOS structures are disclosed for suitable use in high withstand voltage device applications, among others. The LDMOS transistor includes a drain well region 21 formed in P-type substrate 1, and also formed therein spatially separated one another are a channel well region 23 and a medium concentration drain region 24 having an impurity concentration larger than that of drain well region 21, which are simultaneously formed having a large diffusion depth through thermal processing. A source 11s is formed in channel well region 23, while a drain 11d is formed in drain region 24 having an impurity concentration larger than that of drain region 24. In addition, a gate electrode 11g is formed over the well region, overlying the partially overlapped portions with well region 23 and drain region 24 and being separated from drain 11d.

Abstract: It is an object to obtain a semiconductor device comprising a channel stop structure which is excellent in an effect of stabilizing a breakdown voltage and a method of manufacturing the semiconductor device. A silicon oxide film (2) is formed on an upper surface of an N?-type silicon substrate (1). An N+-type impurity implantation region (4) is formed in an upper surface (3) of the N?-type silicon substrate (1) in a portion exposed from the silicon oxide film (2). A deeper trench (5) than the N+-type impurity implantation region (4) is formed in the upper surface (3) of the N?-type silicon substrate (1). A silicon oxide film (6) is formed on an inner wall of the trench (5). A polysilicon film (7) is formed to fill in the trench (5). An aluminum electrode (8) is formed on the upper surface (3) of the N?-type silicon substrate (1). The aluminum electrode (8) is provided in contact with an upper surface of the polysilicon film (7) and the upper surface (3) of the N?-type silicon substrate (1).

Abstract: A lateral semiconductor device (20) such as LDMOS, a LIGBT, a lateral diode, a lateral GTO, a lateral JFET or a lateral BJT, comprising a drift region (12) having a first surface (22) and a first conductivity type, first and second conductive (4, 8) extending into the drift region from the first surface. The lateral semiconductor device further comprises an additional region (24) or several additional regions, having a second conductivity type, between the first and second semiconductor regions (4, 8), the additional region extending into the drift region from the first surface (22), wherein the additional region forms a junction dividing the electric field between the first and second semiconductor regions when a current path is established between the first and second semiconductor regions. This allows the doping concentration of the drift region to be increased, thereby lowering the on-resistance of the device.

Abstract: The a trench semiconductor device such as a power MOSFET the high electric field at the corner of the trench is diminished by increasing the thickness of the gate oxide layer at the bottom of the trench. Several processes for manufacturing such devices are described. In one group of processes a directional deposition of silicon oxide is performed after the trench has been etched, yielding a thick oxide layer at the bottom of the trench. Any oxide which deposits on the walls of the trench is removed before a thin gate oxide layer is grown on the walls. The trench is then filled with polysilicon in or more stages. In a variation of the process a small amount of photoresist is deposited on the oxide at the bottom of the trench before the walls of the trench are etched. Alternatively, polysilicon can be deposited in the trench and etched back until only a portion remains at the bottom of the trench. The polysilicon is then oxidized and the trench is refilled with polysilicon.

Abstract: A multilayer L-shaped spacer is formed of a lower portion comprising a CVD organic material or amorphous carbon, and an upper portion comprised of a protective material. The upper portion is patterned using a photoresist mask. During that patterning, the underlying substrate is protected by a layer of CVD organic material or amorphous carbon. The CVD organic material or amorphous carbon is then patterned using the patterned protective material as a mask. The chemistry used to pattern the CVD organic material or amorphous carbon is relatively harmless to the underlying substrate. Alternatively, an L-shaped spacer is patterned without using a photoresist mask by forming an amorphous carbon spacer around a gate that is covered with a conformal layer of a conventional spacer material. The conventional spacer material is patterned using the amorphous carbon spacer as an etch mask.

Abstract: A semiconductor memory device comprising: a source diffusion layer formed on a semiconductor substrate and connected to a fixed potential line; a plurality of columnar semiconductor layers arranged in a matrix form and formed on the source diffusion layer and each having one end connected to the source diffusion layer commonly, the columnar semiconductor layer taking a first data state with a first threshold voltage that excessive majority carriers are accumulated in the columnar semiconductor layer, and a second data state with a second threshold voltage that excessive majority carriers are discharged from the columnar semiconductor layer; a plurality of drain diffusion layers each formed at the other end of the columnar semiconductor layer; a plurality of gate electrodes each opposed to the columnar semiconductor layer via a gate insulating film, and connected to the word line; a plurality of word lines each connected to corresponding the gate electrodes; and a plurality of bit lines each connected to corre

Abstract: After a MOS type transistor is formed on the surface of a semiconductor substrate, an interlayer insulating film covering the transistor is formed. The insulating film includes a silicon oxide film made of hydrogen silsesquioxane resin in a ceramic state. After a wiring layer is formed on the insulating film, a silicon oxide film as a surface protection film is formed on the insulating film, covering the wiring layer. In order to reduce process damages, heat treatment is performed 30 minutes at 400° C. in a nitrogen gas atmosphere. With this heat treatment, hydrogen in the silicon oxide film is released and diffuses into the channel region of the transistor to lower interfacial energy levels. Since the silicon nitride film does not transmit hydrogen, it is not necessary for the heat treatment atmosphere to contain hydrogen. A variation in threshold voltages of MOS type transistors can be easily lowered.

Abstract: In order to obtain an on resistance that is as low as possible, it is proposed, in the case of a MOS transistor device, to form the avalanche breakdown region in an end region of a trench structure. As an alternative or in addition, it is proposed to form a region of local maximum dopant concentration of a first conductivity type in the region between a source and a drain in proximity to the gate insulation in a manner remote from the gate electrode.

Abstract: A semiconductor component has a minimal size and area requirement. The semiconductor component is formed in a trench with wall regions and a bottom region. Terminal regions for the electrical connection of first and second contact regions (S, B) are formed at least partly within the trench (30).

Abstract: A power MOSFET comprises, between source and drain electrodes, a low resistive semiconductor substrate of a first conductivity type, a drift layer of the first conductivity type formed on the semiconductor substrate, a high resistive epitaxial layer of the first conductivity type formed on the drift layer, trenches formed to extend from a surface of the epitaxial layer into the drift layer, gate electrodes buried in the trenches with gate insulating films interposed between the gate electrodes and walls of the trenches, low resistive source layers of the first conductivity type formed in a surface region of the epitaxial layer adjacent to the gate insulating films, and a base layer of a second conductivity type formed in the surface region of the epitaxial layer, wherein the epitaxial layer intervening between the trenches is depleted in a case where 0 volt is applied between the source electrode and the gate electrodes.

Abstract: A drain-extended MOS transistor in a semiconductor wafer (300) of a first conductivity type comprises a first well (315) of the first conductivity type, operable as the extension of the transistor drain (305) of the first conductivity type, and covered by a first insulator (312) having a first thickness, and further a second well (302) of the opposite conductivity type, intended to contain the transistor source (304) of the first conductivity type, and covered by a second insulator (311) thinner than said first insulator (312). First and second wells form a junction (330) that terminates (320, 321) at the second insulator. The first well has a region (360) in the proximity of the junction termination, which has a higher doping concentration than the remainder of the first well and extends not deeper than the first insulator thickness.

Abstract: A method of driving a dual-gated MOSFET having a Miller capacitance between the MOSFET gate and drain includes preparing the MOSFET to switch from a blocking mode to a conduction mode by applying to the MOSFET shielding gate a first voltage signal having a first voltage level. The first voltage level is selected to charge the Miller capacitance and thereby reduce switching losses. A second voltage signal is applied to the switching gate to switch the MOSFET from the blocking to the conduction mode. The first voltage signal is then changed to a level selected to reduce the conduction mode drain-to-source resistance and thereby reduce conduction losses. The first voltage signal is returned to the first voltage level to prepare the MOSFET for being switched from the conduction mode to the blocking mode.

Abstract: A structure of a Trapezoid-Triple-Gate Field Effect Transistor (FET) includes a plurality of trapezoid pillars being transversely formed on an crystalline substrate or Silicon-On-Insulator (SOI) wafer. The trapezoid pillars can juxtapose with both ends connected each other. Each trapezoid pillar has a source, a channel region, and a drain aligned in longitudinal direction and a gate latitudinally superposes the channel region of the trapezoid pillar. The triple gate field effect transistor comprises a dielectric layer formed between the channel region and the conductive gate structure.

Abstract: A circuit structure has at least two etching trenches disposed at sidewalls of a silicon block left behind during the etching of the structure. The etching trenches are disposed at angles with respect to one another that are prescribed by the form of the silicon block left behind. Semiconductor layer structures which can interact with one another diagonally across are in each case accommodated in the etching trenches. In this case, the function of the entire circuit structure results from the interaction of the layer structures disposed in the various etching trenches.