In Integrated Circuit Structure Patents (Class 257/334)
  • Patent number: 10666140
    Abstract: In some examples, a device comprises an integrated circuit comprising a first transistor and a second transistor. The device further comprises an inductor comprising a first inductor terminal and a second inductor terminal, wherein the first inductor terminal is electrically connected to the first transistor and the second transistor. The device further comprises at least five electrical connections on a first side of the device.
    Type: Grant
    Filed: August 22, 2016
    Date of Patent: May 26, 2020
    Assignee: Infineon Technologies Americas Corp.
    Inventor: Eung San Cho
  • Patent number: 10658514
    Abstract: A gate-all around fin double diffused metal oxide semiconductor (DMOS) devices and methods of manufacture are disclosed. The method includes forming a plurality of fin structures from a substrate. The method further includes forming a well of a first conductivity type and a second conductivity type within the substrate and corresponding fin structures of the plurality of fin structures. The method further includes forming a source contact on an exposed portion of a first fin structure. The method further comprises forming drain contacts on exposed portions of adjacent fin structures to the first fin structure. The method further includes forming a gate structure in a dielectric fill material about the first fin structure and extending over the well of the first conductivity type.
    Type: Grant
    Filed: February 7, 2018
    Date of Patent: May 19, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: John B. Campi, Jr., Robert J. Gauthier, Jr., Rahul Mishra, Souvick Mitra, Mujahid Muhammad
  • Patent number: 10644104
    Abstract: A fin field effect transistor device with air gaps, including a source/drain layer on a substrate, one or more vertical fin(s) in contact with source/drain layer, a gate metal fill that forms a portion of a gate structure on each of the one or more vertical fin(s), and a bottom void space between the source/drain layer and the gate metal fill.
    Type: Grant
    Filed: September 25, 2018
    Date of Patent: May 5, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Hari V. Mallela, Robert R. Robison, Reinaldo A. Vega, Rajasekhar Venigalla
  • Patent number: 10622445
    Abstract: This invention discloses a metal oxide semiconductor field effect transistor (MOSFET) device. The MOSFET device has a semiconductor substrate that supports an epitaxial layer thereon. The epitaxial layer comprises at least three layers of different dopant concentrations and wherein a middle epitaxial layer having a varying dopant concentration profile along an upward vertical direction.
    Type: Grant
    Filed: August 22, 2018
    Date of Patent: April 14, 2020
    Assignee: HUNTECK SEMICONDUCTOR (SHANGHAI) CO. Ltd.
    Inventor: Jun Hu
  • Patent number: 10615263
    Abstract: A semiconductor device and methods for forming the same are provided. The method includes providing a substrate having a first conductive type, forming an epitaxial layer having the first conductive type on the substrate, forming a trench in the epitaxial layer, forming a first insulating layer in the trench and on the top surface of the epitaxial layer, forming a shield electrode and a mask layer on the first insulating layer in order, using the mask layer to remove a portion of the first insulating layer, wherein the top surface of the first insulating layer is higher than the top surface of the shield electrode after removing the portion of the first insulating layer, removing the mask layer, forming a second insulating layer on the first insulating layer and the shield electrode, and forming a gate electrode on the second insulating layer.
    Type: Grant
    Filed: June 11, 2018
    Date of Patent: April 7, 2020
    Assignee: VANGUARD INTERNATIONAL SEMICONDUCTOR CORPORATION
    Inventors: Tsung-Yeh Chen, Sheng-Wei Fu, Chung-Yeh Lee
  • Patent number: 10593813
    Abstract: A new semiconductor rectifier structure. In general, a MOS-transistor-like structure is located above a JFET-like deeper structure. The present application teaches ways to combine and optimize these two structures in a merged device so that the resulting combined structure achieves both a low forward voltage and a high reverse breakdown voltage in a relatively small area. In one class of innovative implementations, an insulated (or partially insulated) trench is used to define a vertical channel in a body region along the sidewall of a trench, so that majority carriers from a “source” region (typically n+) can flow through the channel. An added “pocket” diffusion, of the same conductivity type as the body region (p-type in this example), provides an intermediate region around the bottom of the trench. This intermediate diffusion, and an additional deep region of the same conductivity type, define a deep JFET-like device which is in series with the MOS channel portion of the diode.
    Type: Grant
    Filed: June 22, 2018
    Date of Patent: March 17, 2020
    Assignee: MaxPower Semiconductor Inc.
    Inventors: Richard A. Blanchard, Mohamed N. Darwish, Jun Zeng
  • Patent number: 10586845
    Abstract: According to an embodiment of a semiconductor device, the device includes gate trenches formed in a SiC substrate and extending lengthwise in parallel in a first direction. Rows of source regions of a first conductivity type are formed in the SiC substrate and extend lengthwise in parallel in a second direction which is transverse to the first direction. Rows of body regions of a second conductivity type opposite the first conductivity type are formed in the SiC substrate below the rows of source regions. Rows of body contact regions of the second conductivity type are formed in the SiC substrate. The rows of body contact regions extend lengthwise in parallel in the second direction. First shielding regions of the second conductivity type are formed deeper in the SiC substrate than the rows of body regions.
    Type: Grant
    Filed: November 16, 2018
    Date of Patent: March 10, 2020
    Assignee: Infineon Technologies AG
    Inventors: Thomas Aichinger, Wolfgang Bergner, Paul Ellinghaus, Rudolf Elpelt, Romain Esteve, Florian Grasse, Caspar Leendertz, Shiqin Niu, Dethard Peters, Ralf Siemieniec, Bernd Zippelius
  • Patent number: 10573654
    Abstract: Some embodiments include an integrated assembly having a paired-memory-cell-region within a memory-array-region. The paired-memory-cell-region includes a bitline-contact-structure between a first charge-storage-device-contact-structure and a second charge-storage-device-contact-structure. A first insulative region is between the bitline-contact-structure and the first charge-storage-device-contact-structure. A second insulative region is between the bitline-contact-structure and the second charge-storage-device-contact-structure. The first and second insulative regions both include a first semiconductor material which is in a nonconductive configuration. A transistor gate is over a peripheral region proximate the memory-array-region. The transistor gate has a second semiconductor material which is a same semiconductor composition and thickness as the first semiconductor material, but which is in a conductive configuration. Some embodiments include methods of forming integrated assemblies.
    Type: Grant
    Filed: June 18, 2018
    Date of Patent: February 25, 2020
    Assignee: Micron Technology, Inc.
    Inventor: Tsuyoshi Tomoyama
  • Patent number: 10535761
    Abstract: A semiconductor device including: a semiconductor substrate; a first gate trench portion and a dummy trench portion provided from an upper surface of the semiconductor substrate to a drift region, extending in the extending direction; a first transistor mesa portion sandwiched by the first gate trench portion and dummy trench portion; a base region contacting with the first gate trench portion above the drift region; an emitter region contacting with the same on the semiconductor substrate upper surface; and a second conductivity type region exposed on the semiconductor substrate upper surface, wherein the emitter region and second conductivity type region are arranged alternately in the extending direction; and the emitter region width in the extending direction contacting with the first gate trench portion is greater than the second conductivity type region width in the extending direction contacting with the same, will be provided.
    Type: Grant
    Filed: July 25, 2018
    Date of Patent: January 14, 2020
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventor: Tatsuya Naito
  • Patent number: 10529811
    Abstract: According to an embodiment of a power semiconductor device, the device includes a semiconductor body coupled to a first load terminal and a second load terminal and configured to conduct a load current between the first load terminal and the second load terminal. A trench extends into the semiconductor body along an extension direction and includes an insulator. A first electrode structure included in the trench is configured to control the load current. A second electrode structure included in the trench is arranged separately and electrically insulated from the first electrode structure. The first electrode structure and the second electrode structure are spatially displaced from each other along the extension direction such that they do not have a common extension range along the extension direction. Each of the first electrode structure and the second electrode structure is made of a metal.
    Type: Grant
    Filed: January 18, 2019
    Date of Patent: January 7, 2020
    Assignee: Infineon Technologies Austria AG
    Inventors: Thomas Feil, Michael Hutzler
  • Patent number: 10529845
    Abstract: In an embodiment, a semiconductor device includes a semiconductor body having a field effect transistor device with an active region and an edge termination region that surrounds the active region on all sides. The active region includes a first serpentine trench in the semiconductor body, a first field plate in the first serpentine trench, a second serpentine trench in the semiconductor body, and a second field plate in the second serpentine trench. The first serpentine trench is separate and laterally spaced apart from the second serpentine trench.
    Type: Grant
    Filed: March 9, 2018
    Date of Patent: January 7, 2020
    Assignee: Infineon Technologies Austria AG
    Inventors: Ashita Mirchandani, Thomas Feil, Maximilian Roesch, Britta Wutte
  • Patent number: 10490632
    Abstract: An integrated circuit includes a substrate and at least one component unfavorably sensitive to compressive stress which is arranged at least partially within an active region of the substrate limited by an insulating region. To address compressive stress in the active region, the circuit further includes at least one electrically inactive trench located at least in the insulating region and containing an internal area configured to reduce compressive stress in the active region. The internal area is filled with polysilicon. The polysilicon filled trench may further extend through the insulating region and into the substrate.
    Type: Grant
    Filed: January 7, 2019
    Date of Patent: November 26, 2019
    Assignee: STMicroelectronics (Rousset) SAS
    Inventors: Guilhem Bouton, Pascal Fornara, Christian Rivero
  • Patent number: 10446557
    Abstract: Provided are a semiconductor device having a gate and a method of forming the same. The method includes forming a gate dielectric, forming a first conductive material layer on the gate dielectric, forming a source material layer on the first conductive material layer, and diffusing a first element included in the source material layer into the first conductive material layer by performing a thermal treatment process to form a doped material layer.
    Type: Grant
    Filed: July 7, 2016
    Date of Patent: October 15, 2019
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Dongjin Lee, Ji-Eun Lee, Kyoung-Ho Jung, Satoru Yamada, Moonyoung Jeong
  • Patent number: 10424516
    Abstract: One embodiment provides a method of integrating a planar field-effect transistor (FET) with a vertical FET. The method comprises masking and etching a semiconductor of the vertical FET to form a fin, and providing additional masking, additional etching, doping and depositions to isolate a bottom source/drain (S/D) region. A dielectric is formed on the bottom S/D region to form a spacer. The method further comprises depositing gate metals, etching a vertical gate for the vertical FET and a planar gate for the planar FET using a shared gate mask, depositing dielectric, etching the dielectric to expose one or more portions of the fin, growing epitaxy on a top S/D region, masking and etching S/D contact openings for the bottom S/D region, forming silicide regions in S/D regions, depositing contact metal in the silicide regions to form contacts, and planarizing the contacts.
    Type: Grant
    Filed: March 28, 2018
    Date of Patent: September 24, 2019
    Assignee: International Business Machines Corporation
    Inventors: Brent A. Anderson, Edward J. Nowak
  • Patent number: 10411093
    Abstract: An active cell region, an edge termination region surrounding the active cell region and an intermediate region located at an intermediate position between these regions are provided, the active cell region has a trench gate type MOS structure on a top side, and a vertical structure on a bottom side includes a p-collector layer, an n-buffer layer on the p-collector layer, and an n-drift layer on the n-buffer layer, the n-buffer layer has a first buffer portion provided on the p-collector layer side, and a second buffer portion provided on the n-drift layer side, the peak impurity concentration of the first buffer portion is higher than the peak impurity concentration of the second buffer portion, and the impurity concentration gradient on the n-drift layer side of the second buffer portion is gentler than the impurity concentration gradient on the n-drift layer side of the first buffer portion.
    Type: Grant
    Filed: December 28, 2015
    Date of Patent: September 10, 2019
    Assignee: Mitsubishi Electric Corporation
    Inventors: Katsumi Nakamura, Tatsuo Harada, Noritsugu Nomura
  • Patent number: 10388724
    Abstract: An electronic chip includes a doped semiconductor substrate of a first conductivity type, a doped buried layer of a second conductivity type overlying the substrate, and a first doped well of the first conductivity type overlying the buried layer. Circuit components can be formed at a top surface of the first doped well and separated from the buried layer. A current detector is coupled to the buried layer and configured detect a bias current flowing into or out of the buried layer.
    Type: Grant
    Filed: October 16, 2018
    Date of Patent: August 20, 2019
    Assignee: STMICROELECTRONICS (ROUSSET) SAS
    Inventors: Clement Champeix, Nicolas Borrel, Alexandre Sarafianos
  • Patent number: 10366995
    Abstract: A semiconductor structure includes a substrate, and first isolation structures, at least one buried word line and at least one second isolation structure which are disposed in the substrate. The buried word line intersects the first isolation structures. The second isolation structure intersects the first isolation structures. A material of at least a portion of the second isolation structure is different from a material of the first isolation structures.
    Type: Grant
    Filed: May 15, 2018
    Date of Patent: July 30, 2019
    Assignee: Winbond Electronics Corp.
    Inventors: Wei-Che Chang, Yoshinori Tanaka
  • Patent number: 10355127
    Abstract: The present technique relates to a semiconductor device including a current sensor, which can improve the electrostatic discharge ruggedness. The semiconductor device includes: a first switching element through which a main current flows; and a second switching element through which a sense current flows. The first switching element includes a first gate oxide film formed in contact with a first base layer sandwiched between a first source layer and a drift layer. The second switching element includes a second gate oxide film formed in contact with a second base layer sandwiched between a second source layer and the drift layer. A part of the second gate oxide film including a portion covering the second base layer is thicker than the first gate oxide film.
    Type: Grant
    Filed: July 2, 2015
    Date of Patent: July 16, 2019
    Assignee: Mitsubishi Electric Corporation
    Inventor: Eisuke Suekawa
  • Patent number: 10347729
    Abstract: Devices and methods of fabricating integrated circuit devices for increasing performance through gate cut last processes are provided. One method includes, for instance: obtaining an intermediate semiconductor device having a substrate including a plurality of fins, an STI layer, an oxide layer, and a gate material over the oxide layer, the fins extending into the gate material; removing the gate material and the oxide layer; depositing a high k material on a top surface of the STI layer, surrounding the fins; depositing a gate stack over the high k material; filling the top of the device with a gate contact metal; etching a portion of the gate contact metal, the metal gate stack, and the high k material; and filling the portion with an inter-layer dielectric. Also disclosed is an intermediate device formed by the method.
    Type: Grant
    Filed: May 9, 2017
    Date of Patent: July 9, 2019
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Xusheng Wu, Haigou Huang
  • Patent number: 10312343
    Abstract: A device includes a vertical semiconductor switch including (i) a gate terminal and a first terminal provided on a substrate and (ii) a second terminal provided on the substrate, where the vertical semiconductor switch is configured to electrically connect or disconnect the first terminal and the second terminal, a first insulative film provided on the substrate, a second insulative film provided on the substrate, where the second insulative film is in contact with the first insulative film and thinner than the first insulative film, and a zener diode formed on the first insulative film and the second insulative film, where the zener diode includes a first portion that is formed on the first insulative film and connected to the first surface of the substrate and a second portion that is formed on the second insulative film and connected to the gate terminal.
    Type: Grant
    Filed: July 26, 2016
    Date of Patent: June 4, 2019
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventor: Shigemi Miyazawa
  • Patent number: 10249717
    Abstract: According to one embodiment, a semiconductor device includes a first electrode, a second electrode, first to fourth semiconductor regions and a first insulating film. The second electrode includes first, second, and third electrode regions. The first semiconductor region includes first, second, third, fourth, and fifth partial regions. The first partial region is separated from the first electrode. The second partial region is separated from the first electrode region. The fourth partial region is separated from the second electrode region. The second semiconductor region includes sixth, seventh, eighth and ninth partial regions. The third semiconductor region is connected to the second semiconductor region. The fourth semiconductor region is electrically connected to the second electrode. The fourth semiconductor region includes tenth, eleventh, and twelfth partial regions. The first insulating film is provided between the first, third, and fourth semiconductor regions.
    Type: Grant
    Filed: January 30, 2018
    Date of Patent: April 2, 2019
    Assignees: Kabushiki Kaisha Toshiba, Fuji Electric Co., Ltd.
    Inventors: Keiko Ariyoshi, Ryosuke Iijima, Shinya Kyogoku, Shinsuke Harada, Yusuke Kobayashi
  • Patent number: 10249628
    Abstract: A semiconductor device includes a device isolation region defining an active region in a substrate, and gate structures buried in the active region of the substrate. At least one of the gate structures includes a gate trench, a gate insulating layer conformally formed on an inner wall of the gate trench, a gate barrier pattern conformally formed on the gate insulating layer disposed on a lower portion of the gate trench, a gate electrode pattern formed on the gate barrier pattern and filling the lower portion of the gate trench, an electrode protection layer conformally formed on the gate insulating layer disposed on an upper portion of the gate trench to be in contact with the gate barrier pattern and the gate electrode pattern, a buffer oxide layer conformally formed on the electrode protection layer, and a gate capping insulating layer formed on the buffer oxide layer to fill the upper portion of the gate trench.
    Type: Grant
    Filed: January 9, 2018
    Date of Patent: April 2, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventor: Min-Hee Cho
  • Patent number: 10236340
    Abstract: In a general aspect, a power semiconductor device can include a first trench shield electrode and a second trench shield electrode defined in a semiconductor region, the first and second trench shield electrodes each having a first portion disposed in an active region and a second portion disposed in a termination region. A trench of the first trench shield electrode and a trench of the second trench shield electrode can define a mesa of the semiconductor region therebetween. The device can further include an implant enrichment region disposed in the termination region, the implant enrichment region can be intersected by the first trench shield electrode and the second trench shield electrode, and can have a portion disposed in the mesa of the semiconductor region, the portion extending from the trench of the first trench shield electrode to the trench of the second trench shield electrode.
    Type: Grant
    Filed: April 28, 2017
    Date of Patent: March 19, 2019
    Assignee: Semiconductor Components Industries, LLC
    Inventors: Joseph Yedinak, Xiaoli Wu
  • Patent number: 10204896
    Abstract: A vertical double diffusion metal-oxide-semiconductor power device with thermal sensitivity unit includes a vertical double diffusion metal-oxide-semiconductor power transistor and at least one thermal sensitivity unit. The vertical double diffusion metal-oxide-semiconductor power transistor includes a first metal layer, a substrate layer, an epitaxy layer, a second metal layer, and a plurality of first polysilicon layers, wherein each first polysilicon layer of the plurality of first polysilicon layers corresponds to a first oxide layer, a first doping well and a second doping well with second conductivity type, a first doped region and a second doped region with first conductivity type, and a second oxide layer.
    Type: Grant
    Filed: December 14, 2017
    Date of Patent: February 12, 2019
    Assignee: Leadtrend Technology Corp.
    Inventors: Jen-Hao Yeh, Chiung-Feng Chou
  • Patent number: 10192962
    Abstract: A semiconductor device including, a semiconductor layer including a plurality of first trenches formed therein and a second trench formed in a region between the first trenches, channel regions formed in regions between the first and second trenches in a surface layer portion of the semiconductor layer, field plate electrodes embedded at bottom portion sides of the respective first trenches, first gate electrodes embedded at opening portion sides of the respective first trenches so as to face the channel regions across first gate insulating films above the field plate electrodes, second insulating films interposed between the field plate electrodes and the first gate electrodes, an embedded insulating film embedded to an intermediate portion of the second trench, and a second gate electrode embedded in the second trench so as to face the channel regions across a second gate insulating film above the embedded insulating film.
    Type: Grant
    Filed: April 4, 2017
    Date of Patent: January 29, 2019
    Assignee: ROHM CO., LTD.
    Inventor: Yuto Osawa
  • Patent number: 10181519
    Abstract: The present invention provides a semiconductor device comprising a substrate including an active region and an edge region and containing a semiconductor doped with impurities having a first conductivity type; an insulating film disposed on the edge region of the substrate; a field plate pattern disposed on the insulating film; and at least one first doped region having a second conductivity type buried in the edge region of the substrate and extending in a direction having a vector component parallel to an upper surface of the substrate.
    Type: Grant
    Filed: June 20, 2017
    Date of Patent: January 15, 2019
    Assignee: HYUNDAI AUTRON CO., LTD.
    Inventors: Young Joon Kim, Hyuk Woo, Tae Yeop Kim, Han Sin Cho, Tae Young Park, Ju Hwan Lee
  • Patent number: 10177232
    Abstract: A Schottky device includes a plurality of mesa structures where one or more of the mesa structures includes a doped region having a multi-concentration dopant profile. In accordance with an embodiment, the Schottky device is formed from a semiconductor material of a first conductivity type. Trenches having sidewalls and floors are formed in the semiconductor material to form a plurality of mesa structures. A doped region having a multi-concentration impurity profile is formed between two trenches, where the impurity materials of the doped region having the multi-concentration impurity profile are of a second conductivity type. A Schottky contact is formed to at least one of the mesa structures having the doped region with the multi-concentration impurity profile.
    Type: Grant
    Filed: July 24, 2017
    Date of Patent: January 8, 2019
    Assignee: Semiconductor Components Industries, LLC
    Inventors: Mohammed Tanvir Quddus, Mihir Mudholkar, Mingjiao Liu, Michael Thomason
  • Patent number: 10160334
    Abstract: Provided is a power conversion device capable of selectively suppressing harmonic noise in a frequency band and a machine equipped with the power conversion device. The power conversion device includes a switching element (13), a switching signal generation unit (23, 24) for generating a switching control signal for controlling the turning on/off of the switching element (13), and a control unit (18), and is characterized in that the switching control signal generation unit (23, 24) generates the switching control signal including a combination of a pair of symmetrical pulse waveforms having on and off periods that are interchanged with respect to a repeated cycle.
    Type: Grant
    Filed: December 8, 2014
    Date of Patent: December 25, 2018
    Assignee: Hitachi, Ltd.
    Inventors: Isao Houda, Masayoshi Takahashi, Hiroki Funato, Hitoshi Akiyama
  • Patent number: 10164025
    Abstract: A semiconductor device comprises a semiconductor substrate structure comprising a cell region and an edge termination region surrounding the cell region. Further it comprises a plurality of needle-shaped cell trenches within the cell region reaching from a surface of the semiconductor substrate structure into the substrate structure and an edge termination trench within the edge termination region surrounding the cell region at the surface of the semiconductor substrate structure.
    Type: Grant
    Filed: January 11, 2018
    Date of Patent: December 25, 2018
    Assignee: INFINEON TECHNOLOGIES AUSTRIA AG
    Inventors: Oliver Blank, Franz Hirler, Ralf Siemieniec, Li Juin Yip
  • Patent number: 10153350
    Abstract: The bottom surface of the trench is provided so that a center part of the bottom surface protrudes upward with respect to a peripheral part of the bottom surface in a short direction. A thickness of the gate insulating film covering the peripheral part is thicker than a thickness of the gate insulating film covering the center part.
    Type: Grant
    Filed: August 3, 2015
    Date of Patent: December 11, 2018
    Assignee: TOYOTA JIDOSHA KABUSHIKI KAISHA
    Inventors: Jun Saito, Tatsuji Nagaoka, Sachiko Aoi, Yukihiko Watanabe, Shinichiro Miyahara, Takashi Kanemura
  • Patent number: 10121892
    Abstract: A semiconductor device includes a first semiconductor region of a first conductivity type, a second semiconductor region of a second conductivity type on the first semiconductor region, a third semiconductor region of the first conductivity type on the second semiconductor region, a first electrode surrounded by the first semiconductor region, a first insulating portion between a first part of the first electrode and the first semiconductor region, a second insulating portion having a higher dielectric constant than the first insulating portion, between a second part of the first electrode and the first semiconductor region, a gate electrode above the first electrode, and a gate insulating portion between the second semiconductor region and the gate electrode.
    Type: Grant
    Filed: August 30, 2016
    Date of Patent: November 6, 2018
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Tatsuya Nishiwaki
  • Patent number: 10103257
    Abstract: A plurality of trench stripes are disposed in parallel in an epitaxial layer on a drain and extends from a top region to a bottom region of a first surface of the semiconductor. A first polysilicon layer is in each of the trench stripes. The first polysilicon layer extends between the drain and the first surface proximal to the top region and the bottom region, and between the drain and a level below the first surface in a middle region between the top region and the bottom region. A second polysilicon layer is over the first polysilicon layer in the middle region, wherein the first poly silicon layer forms a shield, and the second polysilicon layer forms a gate. A source is in a silicon mesa stripe surrounding the first trench stripe.
    Type: Grant
    Filed: November 10, 2017
    Date of Patent: October 16, 2018
    Assignee: NXP USA, Inc.
    Inventors: Ganming Qin, Vishnu Khemka, Ljubo Radic, Bernhard Grote, Tanuj Saxena, Moaniss Zitouni
  • Patent number: 10102907
    Abstract: A method for fabricating a semiconductor memory device is disclosed. A semiconductor substrate having a main surface is prepared. At least a first dielectric layer is formed on the main surface of the semiconductor substrate. A first OS FET device and a second OS FET device are formed on the first dielectric layer. At least a second dielectric layer is formed to cover the first dielectric layer, the first OS FET device, and the second OS FET device. A first MIM capacitor and a second MIM capacitor are formed on the second dielectric layer. The first MIM capacitor is electrically coupled to the first OS FET device, thereby constituting a DOSRAM cell. The second MIM capacitor is electrically coupled to the second OS FET device, thereby constituting a NOSRAM cell.
    Type: Grant
    Filed: December 19, 2016
    Date of Patent: October 16, 2018
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Zhibiao Zhou, Chen-Bin Lin, Chi-Fa Ku, Shao-Hui Wu
  • Patent number: 10056461
    Abstract: Aspects of the present disclosure discloses a method for fabricating a trench MOSFET device comprising simultaneously forming a narrow trench and a wide trench into a semiconductor substrate using a mask to defines the narrow trench and the wide trench, forming an insulating layer over the semiconductor substrate with a first portion that fills up the narrow trench and a second portion that partially fills the wide trench, removing the second portion from the wide trench completely and leaving the narrow trench filled with the first portion, forming a gate electrode, forming a body region in a top portion of the semiconductor substrate, forming a source region in a portion of the body region, removing the first portion of nitride from the narrow trench, and forming a contact plug by filling a second conductive material in the narrow trench.
    Type: Grant
    Filed: September 30, 2016
    Date of Patent: August 21, 2018
    Assignee: ALPHA AND OMEGA SEMICONDUCTOR INCORPORATED
    Inventors: Sik Lui, Hong Chang
  • Patent number: 10038089
    Abstract: A semiconductor power device includes a plurality of power transistor cells each having a trenched gate disposed in a gate trench opened in a semiconductor substrate wherein a plurality of the trenched gates further include a shielded bottom electrode disposed in a bottom portion of the gate trench electrically insulated from a top gate electrode disposed at a top portion of the gate trench by an inter-electrode insulation layer. At least one of the shielded bottom electrode is connected a source metal and at least one of the top electrodes in the gate trench is connected to a source metal of the power device.
    Type: Grant
    Filed: December 2, 2015
    Date of Patent: July 31, 2018
    Assignee: HUNTECK SEMICONDUCTOR (SHANGHAI) CO., Ltd
    Inventors: Jun Hu, Zhiyun Luo, Fei Wang, Mengyu Pan
  • Patent number: 10002870
    Abstract: Disclosed examples include semiconductor devices and fabrication methods to fabricate semiconductor wafers and integrated circuits, including forming a first epitaxial semiconductor layer of a first conductivity type on a first side of a semiconductor substrate of the first conductivity type, forming a nitride or oxide protection layer on a top side of the first epitaxial semiconductor layer, forming a second epitaxial semiconductor layer of the first conductivity type on the second side of the semiconductor substrate, and removing the protection layer from the first epitaxial semiconductor layer. The wafer can be used to fabricate an integrated circuit by forming a plurality of transistors at least partially on the first epitaxial semiconductor layer.
    Type: Grant
    Filed: August 16, 2016
    Date of Patent: June 19, 2018
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: James Fred Salzman, Bradley David Sucher
  • Patent number: 10002874
    Abstract: A method of forming conductive material of a buried transistor gate line includes adhering a precursor comprising tungsten and chlorine to material within a substrate trench. The precursor is reduced with hydrogen to form elemental-form tungsten material over the material within the substrate trench from the precursor.
    Type: Grant
    Filed: July 3, 2017
    Date of Patent: June 19, 2018
    Assignee: Micron Technologies, Inc.
    Inventor: Hidekazu Nobuto
  • Patent number: 9954096
    Abstract: A switching device includes a semiconductor substrate; a trench; a conductor layer extending in a longitudinal direction of the trench so as to be in contact with a bottom surface of the trench; a bottom insulating layer covering an upper surface of the conductor layer; a gate insulating layer covering a side surface of the trench; and a gate electrode disposed in the trench. The semiconductor substrate includes a first semiconductor region of a first conductivity type, a body region of a second conductivity type, a second semiconductor region of the first conductivity type, a bottom semiconductor region of the second conductivity type extending in the longitudinal direction so as to be in contact with the conductor layer, and a connection semiconductor region of the second conductivity type connected to the body region and to the bottom semiconductor region.
    Type: Grant
    Filed: July 31, 2017
    Date of Patent: April 24, 2018
    Assignee: TOYOTA JIDOSHA KABUSHIKI KAISHA
    Inventors: Hirokazu Fujiwara, Yuichi Takeuchi, Narumasa Soejima
  • Patent number: 9929285
    Abstract: The present invention relates to the field of semiconductor technology, particularly to a super-junction schottky diode. According to the present invention, the effective area of schottky junction is increased by forming the schottky junction in the trench located in the body of the device. Therefore, the current capacity of this novel schottky diode can be greatly improved. In addition, a super-junction structure is used to improve the device's reverse breakdown voltage and reduce the reverse leakage current. The super-junction schottky diode provided in the present invention can achieve a larger forward current, a lower on-resistance and a better reverse breakdown characteristic.
    Type: Grant
    Filed: May 23, 2017
    Date of Patent: March 27, 2018
    Assignee: UNIVERSITY OF ELECTRONIC SCIENCE AND TECHNOLOGY OF CHINA
    Inventors: Min Ren, Yuci Lin, Huiping Bao, Lei Luo, Zehong Li, Bo Zhang
  • Patent number: 9899343
    Abstract: Apparatus and associated methods relate to a bonding pad structure for a trench-based semiconductor device. The bonding pad structure reduces a peak magnitude of the electric field between a metal bonding pad and the underlying semiconductor. The bonding pad structure includes a plurality of trenches vertically extending from a top surface of a semiconductor. Each of the plurality of trenches has dielectric sidewalls and a dielectric bottom, the dielectric sidewalls and dielectric bottom electrically isolating a conductive core within each of the trenches from a region of semiconductor outside of and adjacent to each of the plurality of trenches. The bonding pad structure includes a metal bonding pad disposed above the plurality of trenches, the metal bonding pad electrically isolated from the region of semiconductor outside of the trenches. The conductive core can be biased to reduce the magnitude of the field between adjacent trenches.
    Type: Grant
    Filed: March 9, 2016
    Date of Patent: February 20, 2018
    Assignees: Polar Semiconductor, LLC, SANKEN ELECTRIC CO., LTD.
    Inventors: Peter West, Steven Kosier, Tatsuya Kamimura, Don Rankila
  • Patent number: 9893069
    Abstract: A semiconductor device includes a device isolation region defining an active region in a substrate, and gate structures buried in the active region of the substrate. At least one of the gate structures includes a gate trench, a gate insulating layer conformally formed on an inner wall of the gate trench, a gate barrier pattern conformally formed on the gate insulating layer disposed on a lower portion of the gate trench, a gate electrode pattern formed on the gate barrier pattern and filling the lower portion of the gate trench, an electrode protection layer conformally formed on the gate insulating layer disposed on an upper portion of the gate trench to be in contact with the gate barrier pattern and the gate electrode pattern, a buffer oxide layer conformally formed on the electrode protection layer, and a gate capping insulating layer formed on the buffer oxide layer to fill the upper portion of the gate trench.
    Type: Grant
    Filed: August 5, 2016
    Date of Patent: February 13, 2018
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventor: Min-Hee Cho
  • Patent number: 9871119
    Abstract: Representative implementations of devices and techniques provide a termination arrangement for a transistor structure. The periphery of a transistor structure may include a recessed area having features arranged to improve performance of the transistor at or near breakdown.
    Type: Grant
    Filed: November 24, 2014
    Date of Patent: January 16, 2018
    Assignee: Infineon Technologies Austria AG
    Inventors: Andrew Wood, Markus Zundel
  • Patent number: 9859447
    Abstract: A diode device and manufacturing method thereof are provided. The diode device includes a substrate, an epitaxial layer, a trench gate structure, a Schottky diode structure and a termination structure. An active region and a termination region are defined in the epitaxial layer. The Schottky diode structure and the trench gate structure are located in the active region and the termination structure is located in the termination region. The termination structure includes a termination trench formed in the epitaxial layer, a termination insulating layer, a first spacer, a second spacer and a first doped region. The termination insulating layer is conformingly formed on inner walls of the termination trench. The first and second spacers are disposed on two sidewalls of the termination trench. The first doped region formed beneath the termination trench has a conductive type reverse to that of the epitaxial layer.
    Type: Grant
    Filed: April 5, 2016
    Date of Patent: January 2, 2018
    Assignee: LITE-ON SEMICONDUCTOR CORP.
    Inventors: Shih-Han Yu, Sung-Ying Tsai, Yu-Hung Chang, Ju-Hsu Chuang, Chih-Wei Hsu
  • Patent number: 9859448
    Abstract: Under one aspect, a power Schottky diode includes a cathode; a semiconductor disposed over the cathode, the semiconductor including at least a first region and a second region, the second region defining a guard ring; an anode disposed over the first region and at least a portion of the guard ring, the anode including a metal, a junction between the anode and the first region defining a Schottky barrier; and an oxide disposed over the guard ring. Additionally, the power Schottky diode can include a resistive material disposed over at least a portion of the guard ring and at least a portion of the oxide. The resistive material can inhibit a flow of holes from the guard ring to the anode following a heavy ion strike to the guard ring. The anode further can be disposed over at least a portion of, or the entirety of, the resistive material.
    Type: Grant
    Filed: May 6, 2016
    Date of Patent: January 2, 2018
    Assignee: The Aerospace Corporation
    Inventor: John R. Scarpulla
  • Patent number: 9812554
    Abstract: According to one embodiment, a method for manufacturing a semiconductor device comprises making a first opening, ion-implanting an impurity of a second conductivity type, and forming a third semiconductor layer of the second conductivity type. The first opening is made in a second semiconductor layer. The second semiconductor layer is provided on a first semiconductor layer. The first opening extends in a second direction. A dimension in a third direction of an upper part of the first opening is longer than a dimension in the third direction of a lower part of the first opening. The third direction is perpendicular to the first direction and the second direction. The impurity of the second conductivity type is ion-implanted into a side surface of the lower part of the first opening. The third semiconductor layer of the second conductivity type is formed in an interior of the first opening.
    Type: Grant
    Filed: January 19, 2016
    Date of Patent: November 7, 2017
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Tomoyuki Sakuma, Shinya Sato, Noboru Yokoyama, Akihiro Shimada
  • Patent number: 9806274
    Abstract: An N-type thin film transistor includes an insulating substrate, a first MgO layer, a semiconductor carbon nanotube layer, a second MgO layer, a functional dielectric layer, a gate electrode, a source electrode and a drain electrode. The first MgO layer is located on the insulating substrate. The semiconductor carbon nanotube layer is located on the first MgO layer. The source electrode and the drain electrode are electrically connected to the semiconductor carbon nanotube layer, wherein the source electrode and the drain electrode are spaced from each other, and a channel is defined in the semiconductor carbon nanotube layer and between the source electrode and the drain electrode. The second MgO layer is located on the semiconductor carbon nanotube layer. The functional dielectric layer covering the second MgO layer. The gate electrode on the functional dielectric layer.
    Type: Grant
    Filed: January 19, 2017
    Date of Patent: October 31, 2017
    Assignees: Tsinghua University, HON HAI PRECISION INDUSTRY CO., LTD.
    Inventors: Guan-Hong Li, Qun-Qing Li, Yuan-Hao Jin, Shou-Shan Fan
  • Patent number: 9793387
    Abstract: A semiconductor device includes a drift region extending from a first surface into a semiconductor portion. A body region between two portions of the drift region forms a first pn junction with the drift region. A source region forms a second pn junction with the body region. The pn junctions include sections perpendicular to the first surface. Gate structures extend into the body regions and include a gate electrode. Field plate structures extend into the drift region and include a field electrode separated from the gate electrode. A gate shielding structure is configured to reduce a capacitive coupling between the gate structures and a backplate electrode directly adjoining a second surface.
    Type: Grant
    Filed: August 17, 2016
    Date of Patent: October 17, 2017
    Assignee: Infineon Technologies Austria AG
    Inventors: Michael Hutzler, Georg Ehrentraut, Matthias Kuenle, Ralf Siemieniec
  • Patent number: 9786854
    Abstract: An N-type thin film transistor includes an insulating substrate, a gate electrode, an insulating layer, a first MgO layer, a semiconductor carbon nanotube layer, a second MgO layer, a functional dielectric layer, a source electrode and a drain electrode. The gate electrode is located on a surface of the insulating substrate. The insulating layer is located on the gate electrode. The first MgO layer is located on the insulating layer. The semiconductor carbon nanotube layer is located on the first MgO layer. The source electrode and the drain electrode are electrically connected to the semiconductor carbon nanotube layer, wherein the source electrode and the drain electrode are spaced from each other. The second MgO layer is located on the semiconductor carbon nanotube layer. The functional dielectric layer is located on the second MgO layer.
    Type: Grant
    Filed: January 19, 2017
    Date of Patent: October 10, 2017
    Assignees: Tsinghua University, HON HAI PRECISION INDUSTRY CO., LTD.
    Inventors: Guan-Hong Li, Qun-Qing Li, Yuan-Hao Jin, Shou-Shan Fan
  • Patent number: 9768177
    Abstract: A method of forming conductive material of a buried transistor gate line includes adhering a precursor comprising tungsten and chlorine to material within a substrate trench. The precursor is reduced with hydrogen to form elemental-form tungsten material over the material within the substrate trench from the precursor.
    Type: Grant
    Filed: August 4, 2015
    Date of Patent: September 19, 2017
    Assignee: Micron Technology, Inc.
    Inventor: Hidekazu Nobuto
  • Patent number: 9755058
    Abstract: A semiconductor device comprises a vertical power device, such as a superjunction MOSFET, an IGBT, a diode, and the like, and a surface device that comprises one or more lateral devices that are electrically active along a top surface of the semiconductor device.
    Type: Grant
    Filed: February 26, 2016
    Date of Patent: September 5, 2017
    Assignee: D3 Semiconductor LLC
    Inventors: Thomas E. Harrington, III, Zhijun Qu