In Integrated Circuit Structure Patents (Class 257/334)
  • Patent number: 11916116
    Abstract: A semiconductor device according to one or more embodiments may include: on a semiconductor substrate, a high voltage circuit region; a transistor element region; an isolation region that elementally isolates the transistor element region from the high voltage circuit region; and a capacitively coupled field plate including plural lines of conductors, wherein the capacitively coupled field plate is provided to extend circumferentially along an outer circumferential portion of the high voltage circuit region and across the transistor element region, in a plan view of the semiconductor device, and one or more dividing sections divides at least one of the plural lines of conductors in the capacitively coupled field plate to make the at least one line discontinuous.
    Type: Grant
    Filed: March 31, 2022
    Date of Patent: February 27, 2024
    Assignee: SANKEN ELECTRIC CO., LTD.
    Inventor: Hironori Aoki
  • Patent number: 11901294
    Abstract: A semiconductor device includes a substrate, one or more transistors, a metal layer, one or more buried power rails, and at least one wall-via structure. The transistors and the metal layer are manufactured above a top surface of the substrate. The buried power rails are in one or more corresponding trenches in the substrate below the top surface of the substrate. At least one wall-via structure extends between the first buried power rail and the metal layer and electrically connects the first buried power rail to the metal layer. The wall-via structure includes a plurality of intermediate metal layers sandwiched between the first buried power rail and the metal layer. Alternatively, the wall-via structure includes a length that is greater than or equal to four times a basic length unit for components in layers between the first buried power rail and the metal layer for the semiconductor device.
    Type: Grant
    Filed: November 8, 2021
    Date of Patent: February 13, 2024
    Inventor: Vasisht M. Vadi
  • Patent number: 11901381
    Abstract: The present disclosure concerns an image sensor including a plurality of pixels, each including: a doped photosensitive region of a first conductivity type extending vertically in a semiconductor substrate; a charge collection region more heavily doped with the first conductivity type than the photosensitive region, extending vertically in the substrate from an upper surface of the substrate and being arranged above the photosensitive region; and a vertical stack including a vertical transfer gate and a vertical electric insulation wall, the stack crossing the substrate and being in contact with the charge collection region, the gate being arranged on the upper surface side of the substrate and penetrating into the substrate deeper than the charge collection region.
    Type: Grant
    Filed: July 9, 2020
    Date of Patent: February 13, 2024
    Assignee: STMicroelectronics (Crolles 2) SAS
    Inventors: Francois Roy, Andrej Suler
  • Patent number: 11903213
    Abstract: A memory device includes transistor structures and memory arc wall structures. The memory arc wall structures are embedded in the transistor structures. The transistor structure includes a dielectric column, a source electrode and a drain electrode, a gate electrode layer and a channel wall structure. The source electrode and the drain electrode are located on opposite sides of the dielectric column. The gate electrode layer is around the dielectric column, the source electrode, and the drain electrode. The channel wall structure is extended from the source electrode to the drain electrode and surrounds the dielectric column. The channel wall structure is disposed between the gate electrode layer and the source electrode, between the gate electrode layer, and the drain electrode, and between the gate electrode layer and the dielectric column. The memory arc wall structure is extended on and throughout the channel wall structure.
    Type: Grant
    Filed: March 3, 2021
    Date of Patent: February 13, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yu-Wei Jiang, Hung-Chang Sun, Sheng-Chih Lai, Kuo-Chang Chiang, Tsuching Yang
  • Patent number: 11903184
    Abstract: A semiconductor memory device in which performance and reliability are improved, and a method for fabricating the same are provided. The semiconductor memory device includes a conductive line extending in a first direction on a substrate, an interlayer insulation film that includes a cell trench extending in a second direction intersecting the first direction, on the substrate, a first gate electrode and a second gate electrode that are spaced apart from each other in the first direction and each extend in the second direction, inside the cell trench, a channel layer that is inside the cell trench and is electrically connected to the conductive line, on the first gate electrode and the second gate electrode, and a gate insulation layer interposed between the first gate electrode and the channel layer, and between the second gate electrode and the channel layer.
    Type: Grant
    Filed: August 3, 2021
    Date of Patent: February 13, 2024
    Inventors: Kyung Hwan Lee, Yong Seok Kim, Il Gweon Kim, Hui-Jung Kim, Min Hee Cho, Jae Ho Hong
  • Patent number: 11894428
    Abstract: The present invention relates to a silicon carbide semiconductor device that includes a Schottky barrier diode in a field-effect transistor and includes a first trench provided through first and second semiconductor regions in a thickness direction and reaches inside a semiconductor layer, a second trench provided through the second semiconductor region in the thickness direction and reaches inside the semiconductor layer, a gate electrode embedded in the first trench via a gate insulating film, a Schottky barrier diode electrode embedded in the second trench, a first low-resistance layer having contact with a trench side wall of the first trench, and a second low-resistance layer having contact with a trench side wall of the second trench. The second low-resistance layer has an impurity concentration that is higher than the impurity concentration in the semiconductor layer and lower than the impurity concentration in the first low-resistance layer.
    Type: Grant
    Filed: March 18, 2019
    Date of Patent: February 6, 2024
    Assignee: MITSUBISHI ELECTRIC CORPORATION
    Inventors: Hideyuki Hatta, Rina Tanaka, Katsutoshi Sugawara, Yutaka Fukui
  • Patent number: 11888061
    Abstract: A power semiconductor device includes: a semiconductor body; a control electrode at least partially on or inside the semiconductor body; elevated source regions in the semiconductor body adjacent to the control electrode; recessed body regions adjacent to the elevated source regions; and a dielectric layer arranged on a portion of a surface of the semiconductor body and defining a contact hole. The contact hole is at least partially filled with a conductive material establishing an electrical contact with at least a portion of the elevated source regions and at least a portion of the recessed body regions. At least one first contact surface between at least one elevated source region and the dielectric layer extends in a first horizontal plane. At least one second contact surface between at least one recessed body region and the dielectric layer extends in a second horizontal plane located vertically below the first horizontal plane.
    Type: Grant
    Filed: January 17, 2022
    Date of Patent: January 30, 2024
    Assignee: Infineon Technologies Dresden GmbH & Co. KG
    Inventors: Erich Griebl, Markus Beninger-Bina, Matteo Dainese, Ingo Dirnstorfer
  • Patent number: 11888058
    Abstract: The semiconductor device of the present invention includes a semiconductor layer which includes an active portion and a gate finger portion, an MIS transistor which is formed at the active portion and includes a gate trench as well as a source region, a channel region and a drain region sequentially along a side surface of the gate trench, a plurality of first gate finger trenches arranged by an extended portion of the gate trench at the gate finger portion, a gate electrode embedded each in the gate trench and the first gate finger trench, a second conductive-type first bottom-portion impurity region formed at least at a bottom portion of the first gate finger trench, a gate finger which crosses the plurality of first gate finger trenches and is electrically connected to the gate electrode, and a second conductive-type electric field relaxation region which is formed more deeply than the bottom portion of the first gate finger trench between the mutually adjacent first gate finger trenches.
    Type: Grant
    Filed: April 13, 2021
    Date of Patent: January 30, 2024
    Assignee: ROHM CO., LTD.
    Inventor: Yuki Nakano
  • Patent number: 11882683
    Abstract: A method of forming a semiconductor memory device, the semiconductor memory device includes a plurality of active areas, a shallow trench isolation, a plurality of trenches and a plurality of gates. The active areas are defined on a semiconductor substrate, and surrounded by the shallow trench isolation. The trenches are disposed in the semiconductor substrate, penetrating through the active areas and the shallow trench isolation, wherein each of the trenches includes a bottom surface and a saddle portion protruded therefrom in each active areas. The gates are disposed in the trenches respectively.
    Type: Grant
    Filed: December 23, 2021
    Date of Patent: January 23, 2024
    Assignees: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.
    Inventors: Chien-Ming Lu, Fu-Che Lee, Chien-Cheng Tsai, Chiu-Fang Hsu
  • Patent number: 11876093
    Abstract: A power device which is formed on a semiconductor substrate includes: plural lateral insulated gate bipolar transistors (LIGBTs) and a forward conductive unit. The plural LIGBTs are connected in parallel to each other. The forward conductive unit is connected in parallel to the plural LIGBTs. The forward conductive unit consists of a PN diode and a Schottky diode connected in parallel to each other. The PN diode and the Schottky diode share a same N-type region, a reverse terminal, an N-type extension region, an field oxide region, a gate, and a P-type well in an epitaxial layer. The N-type region and the P-type well form a PN junction, wherein the PN junction has a staggered comb-teeth interface from top view. A metal line extends on the staggered comb-teeth interface and alternatingly contacts the N-type region and the P-type well.
    Type: Grant
    Filed: January 5, 2021
    Date of Patent: January 16, 2024
    Assignee: RICHTEK TECHNOLOGY CORPORATION
    Inventors: Chih-Feng Huang, Lung-Sheng Lin
  • Patent number: 11869948
    Abstract: Strategic placement and patterning of electrodes, vias, and metal runners can significantly reduce strain in a power semiconductor die. By modifying the path defining electrodes, vias, and metal runners, as well as patterning the material layers thereof, strain can be better managed to increase reliability of a power semiconductor die.
    Type: Grant
    Filed: February 17, 2021
    Date of Patent: January 9, 2024
    Assignee: Wolfspeed, Inc.
    Inventors: Daniel Jenner Lichtenwalner, Edward Robert Van Brunt, Thomas E. Harrington, III, Shadi Sabri, Brett Hull, Brice McPherson, Joe W. McPherson
  • Patent number: 11871559
    Abstract: A semiconductor device includes a substrate comprising a plurality of active regions extending in a first direction and a device isolation region electrically isolating the plurality of active regions, a gate trench extending across the plurality of active regions and the device isolation region, a gate structure extending in the gate trench of each of and along opposite sidewalls of the plurality of active regions, a gate dielectric film formed between the gate trench and the gate structure in each of the plurality of active regions, and an insulating barrier film provided in each of the plurality of active regions under the gate trench spaced apart from a lower surface of the gate trench and extending in an extension direction of the gate trench.
    Type: Grant
    Filed: July 20, 2021
    Date of Patent: January 9, 2024
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventor: Hyeoung-won Seo
  • Patent number: 11864373
    Abstract: A method for manufacturing a semiconductor structure and a semiconductor structure are provided. The method includes the following operations. A substrate is provided, includes a core region and a peripheral region. A preset barrier layer is formed on the substrate, and covers the core region and the peripheral region. At least a part of the preset barrier layer corresponding to the peripheral region is removed to expose a part of the substrate, and to take a reserved part of the preset barrier layer as a first barrier layer. A dielectric layer and a first conductive layer are successively formed on the first barrier layer and the substrate. A part of the dielectric layer and the first conductive layer on the first barrier layer are removed, to reserve a part of the dielectric layer and the first conductive layer on the first barrier layer closer to the peripheral region.
    Type: Grant
    Filed: January 20, 2022
    Date of Patent: January 2, 2024
    Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventors: Mengmeng Yang, Jie Bai
  • Patent number: 11856752
    Abstract: A semiconductor device includes an active region in a substrate, an isolation film defining the active region in the substrate, a gate trench extending across the active region and the isolation film and including a first trench in the active region and a second trench in the isolation film, a gate electrode including a main gate electrode and a pass gate electrode, the main gate electrode filling a lower part of the first trench, and the pass gate electrode filling a lower part of the second trench, a support structure on the pass gate electrode, the support structure filling an upper part of the second trench, a gate insulating film interposed between the isolation film and the pass gate electrode and between the support structure and the pass gate electrode.
    Type: Grant
    Filed: May 3, 2021
    Date of Patent: December 26, 2023
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventor: Ki-Hyung Nam
  • Patent number: 11810961
    Abstract: In an embodiment, a device includes: a p-type transistor including: a first channel region; a first gate dielectric layer on the first channel region; a tungsten-containing work function tuning layer on the first gate dielectric layer; and a first fill layer on the tungsten-containing work function tuning layer; and an n-type transistor including: a second channel region; a second gate dielectric layer on the second channel region; a tungsten-free work function tuning layer on the second gate dielectric layer; and a second fill layer on the tungsten-free work function tuning layer.
    Type: Grant
    Filed: April 1, 2021
    Date of Patent: November 7, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Hsin-Yi Lee, Weng Chang, Chi On Chui
  • Patent number: 11804524
    Abstract: A Metal Oxide Semiconductor (MOS) cell design has traditional planar cells extending in a first dimension, and trenches with their length extending in a third dimension, orthogonal to the first dimension in a top view. The manufacturing process includes forming a horizontal channel, and a plurality of trenches discontinued in the planar cell regions. Horizontal planar channels are formed in the mesa of the orthogonal trenches. A series connected horizontal planar channel and a vertical trench channel are formed along the trench regions surrounded by the first base. The lack of a traditional vertical channel is important to avoid significant reliability issues (shifts in threshold voltage Vth). The planar cell design offers a range of advantages both in terms of performance and processability. Manufacture of the planar cell is based on a self-aligned process with minimum number of masks, with the potential of applying additional layers or structures.
    Type: Grant
    Filed: August 7, 2020
    Date of Patent: October 31, 2023
    Assignee: MQSEMI AG
    Inventors: Munaf Rahimo, Iulian Nistor
  • Patent number: 11799024
    Abstract: A preparation method for semiconductor device, comprising: forming a body region (110) in the drift region (100), forming a first doped region (111) and a second doped region (112) in the body region (110); forming a first trench (171) penetrating the first doped region (111) and the body region (110) and extending to the drift region (100); forming an extension region (150) with a conductivity type opposite to that of the drift region (100) and surrounding the bottom wall of the first trench (171); filling the first trench (171) with a dielectric layer (130) formed on the sidewall of the trench, a first conductive structure (141) located at the bottom of the trench and a second conductive structure (142) located at the top of the trench; forming a second trench (172) penetrating the body region (110) and extending into the drift region (100); filling the second trench (172) with a third conductive structure (143) and a dielectric layer (130) formed on the inner wall of the trench.
    Type: Grant
    Filed: December 28, 2020
    Date of Patent: October 24, 2023
    Assignee: CHINA RESOURCES MICROELECTRONICS (CHONGQING) CO., LTD.
    Inventors: Dong Fang, Kui Xiao, Zheng Bian, Jinjie Hu
  • Patent number: 11791390
    Abstract: Disclosed is a semiconductor device for improving a gate induced drain leakage and a method for fabricating the same, and the method may include forming a trench in a substrate, lining a surface of the trench with an initial gate dielectric layer, forming a gate electrode to partially fill the lined trench, forming a sacrificial material spaced apart from a top surface of the gate electrode and to selectively cover a top corner of the lined trench, removing a part of the initial gate dielectric layer of the lined trench which is exposed by the sacrificial material in order to form an air gap, and forming a capping layer to cap a side surface of the air gap, over the gate electrode.
    Type: Grant
    Filed: November 18, 2021
    Date of Patent: October 17, 2023
    Assignee: SK hynix Inc.
    Inventors: Se-Han Kwon, Dong-Soo Kim
  • Patent number: 11785763
    Abstract: A semiconductor device includes a substrate including a cell area having a first active region and a peripheral circuit area having a second active region, a direct contact contacting the first active region in the cell area, a bit line structure disposed on the direct contact, a capacitor structure electrically connected to the first active region, a gate structure disposed on the second active region in the peripheral circuit area, lower wiring layers disposed adjacent to the gate structure and electrically connected to the second active region, upper wiring layers disposed on the lower wiring layers, a wiring insulating layer disposed between the lower wiring layers and the upper wiring layers, and upper contact plugs connected to at least one of the lower wiring layers and the upper wiring layers and extending through the wiring insulating layer.
    Type: Grant
    Filed: January 4, 2022
    Date of Patent: October 10, 2023
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Wooyoung Choi, Juseong Oh, Yoosang Hwang
  • Patent number: 11742348
    Abstract: A semiconductor device includes a substrate, a first gate structure and a second gate structure, a first gate spacer and a second gate spacer. The first gate spacer includes a first layer, a second layer over the first layer, a third layer over the second layer, a fourth layer over the third layer, and a fifth layer of the fourth layer, in which the first layer, the third layer, and the fifth layer of the first gate spacer are made of a same material. The second gate spacer includes a first layer, a second layer over the first layer, and a third layer over the second layer, in which the first layer and the third layer of the second gate spacer are made of a same material, and in which a lateral width of the first gate spacer is greater than a lateral width of the second gate spacer.
    Type: Grant
    Filed: February 24, 2021
    Date of Patent: August 29, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Li-Feng Teng, Wei-Cheng Wu, Harry-Hak-Lay Chuang, Li-Jung Liu
  • Patent number: 11728174
    Abstract: The present application discloses a method for fabricating a semiconductor device using a tilted etch process. The method includes forming an etching stop layer on a substrate, forming a target layer on the etching stop layer, forming a first hard mask layer on the target layer, forming second hard mask layers on the first hard mask layer, performing a first tilted etch process on the first hard mask layer to form first openings along the first hard mask layer and adjacent to first sides of the second hard mask layers, and performing a second tilted etch process on the first hard mask layer to form second openings along the first hard mask layer and adjacent to second sides of the second hard mask layers.
    Type: Grant
    Filed: January 11, 2022
    Date of Patent: August 15, 2023
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventor: Huan-Yung Yeh
  • Patent number: 11709533
    Abstract: A power chip includes: a first power switch, formed in a wafer region and having a first and a second metal electrodes; a second power switch, formed in the wafer region and having a third and a fourth metal electrodes, wherein the first and second power switches respectively constitute an upper bridge arm and a lower bridge arm of a bridge circuit, and the first and second power switches are alternately arranged; and a metal region, at least including a first metal layer and a second metal layer that are stacked, each metal layer including a first to a third electrodes, and electrodes with the same voltage potential in the metal layers are electrically coupled.
    Type: Grant
    Filed: November 18, 2020
    Date of Patent: July 25, 2023
    Assignee: Delta Electronics (Shanghai) CO., LTD
    Inventors: Le Liang, Xiaoni Xin
  • Patent number: 11699766
    Abstract: An object of the present invention is to provide a Schottky barrier diode which is less likely to cause dielectric breakdown due to concentration of an electric field. A Schottky barrier diode includes a semiconductor substrate 20 made of gallium oxide, a drift layer 30 made of gallium oxide and provided on the semiconductor substrate 20, an anode electrode 40 brought into Schottky contact with the drift layer 30, and a cathode electrode 50 brought into ohmic contact with the semiconductor substrate 20. The drift layer 30 has an outer peripheral trench 10 formed at a position surrounding the anode electrode 40 in a plan view. An electric field is dispersed by the presence of the outer peripheral trench 10 formed in the drift layer 30. This alleviates concentration of the electric field on the corner of the anode electrode 40, making it unlikely to cause dielectric breakdown.
    Type: Grant
    Filed: August 30, 2018
    Date of Patent: July 11, 2023
    Assignee: TDK CORPORATION
    Inventors: Jun Arima, Jun Hirabayashi, Minoru Fujita, Katsumi Kawasaki, Daisuke Inokuchi
  • Patent number: 11694927
    Abstract: A structure and a formation method of a semiconductor device are provided. The method includes forming a first source/drain structure and a second source/drain structure over a semiconductor substrate. The method also includes forming a dielectric layer over the first source/drain structure and the second source/drain structure and forming a conductive contact on the first source/drain structure. The method further includes forming a first conductive via over the conductive contact, and the first conductive via is misaligned with the first source/drain structure. In addition, the method includes forming a second conductive via directly above the second source/drain structure, and the second conductive via is longer than the first conductive via.
    Type: Grant
    Filed: September 2, 2021
    Date of Patent: July 4, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yi-Hsiung Lin, Yi-Hsun Chiu, Shang-Wen Chang
  • Patent number: 11683941
    Abstract: A semiconductor structure may include two vertical transport field effect transistors comprising a top source drain, a bottom source drain, and an epitaxial channel and a resistive random access memory between the two vertical transport field effect transistors, the resistive random access memory may include an oxide layer, a top electrode, and a bottom electrode, wherein the oxide layer may contact the top source drain of the two vertical field effect transistor. The top source drain may function as the bottom electrode of the resistive random access memory. The semiconductor structure may include a shallow trench isolation between the two vertical transport field effect transistors, the shallow trench isolation may be embedded in a first spacer, a doped source, and a portion of a substrate.
    Type: Grant
    Filed: December 3, 2019
    Date of Patent: June 20, 2023
    Assignee: International Business Machines Corporation
    Inventors: Alexander Reznicek, Karthik Balakrishnan, Bahman Hekmatshoartabari, Takashi Ando
  • Patent number: 11682696
    Abstract: A semiconductor device includes a layer stack with first and second semiconductor layers of complementary doping types are arranged alternatingly between first and second surfaces of the layer stack. A first semiconductor region adjoins the first semiconductor layers and has a first end arranged in a first device region and extends from the first end into a second device region. Second semiconductor regions adjoin at least one of the second semiconductor layers. A third semiconductor region adjoins the first semiconductor layers. The first semiconductor region extends from the first device region into the second device region and is spaced apart from the third semiconductor region. The second semiconductor regions are arranged between, and spaced apart from, the third and first semiconductor regions.
    Type: Grant
    Filed: May 26, 2021
    Date of Patent: June 20, 2023
    Assignee: Infineon Technologies Dresden GmbH & Co. KG
    Inventors: Ahmed Mahmoud, Franz Hirler, Marco Mueller, Rolf Weis
  • Patent number: 11682695
    Abstract: A semiconductor device includes a layer stack with first semiconductor layers and second semiconductor layers of opposite doping types arranged alternatingly. A first semiconductor region of a first semiconductor device adjoins the first semiconductor layers, and has a first end arranged in a first region of the first semiconductor device and extends from the first end into a second region of the first semiconductor device. Second semiconductor regions of the first semiconductor device adjoin at least one of the second semiconductor layers. A third semiconductor region of the first semiconductor device adjoins the first semiconductor layers. The first semiconductor region extends from the first region into the second region and is spaced apart from the third semiconductor region. The second semiconductor regions are arranged between, and spaced apart from, the third and first semiconductor regions.
    Type: Grant
    Filed: May 26, 2021
    Date of Patent: June 20, 2023
    Assignee: Infineon Technologies Dresden GmbH & Co. KG
    Inventors: Ahmed Mahmoud, Franz Hirler, Marco Mueller, Rolf Weis
  • Patent number: 11670706
    Abstract: In a general aspect, method of producing an insulated-gate bipolar transistor (IGBT) device can include forming a termination structure in an inactive region. The inactive region at least partial surround an active region. The method can also include forming a trench extending along a longitudinal axis in the active region. A first mesa can define a first sidewall of the trench, and a second mesa can define a second sidewall of the trench. The first mesa and the second mesa can be parallel with the trench. The method can further include forming, in at least a portion of the first mesa, an active segment of the IGBT device, and, forming, in at least a portion of the second mesa, an inactive segment of the IGBT device.
    Type: Grant
    Filed: July 17, 2020
    Date of Patent: June 6, 2023
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Meng-Chia Lee, Ralph N. Wall, Mingjiao Liu, Shamsul Arefin Khan, Gordon M. Grivna
  • Patent number: 11658237
    Abstract: A trench-gate power MOSFET with optimized layout, comprising: a substrate; a first semiconductor region formed on the substrate, having a first doping type; mutually separated trench isolation gate structure, formed on the first semiconductor region, the trench isolation gate structure includes an gate oxide layer and a gate electrode; a second semiconductor region and a third semiconductor region formed between any two adjacent structures of mutually separated trench isolation gate structures; and a first shielding region, formed under each of the third semiconductor regions, connecting simultaneously with multiple mutually separated trench isolation structures.
    Type: Grant
    Filed: September 13, 2022
    Date of Patent: May 23, 2023
    Assignee: ZJU-Hangzhou Global Scientific and Technological Innovation Center
    Inventors: Na Ren, Kuang Sheng, Zhengyun Zhu, Hu Chen
  • Patent number: 11626480
    Abstract: Disclosed is a method for manufacturing a semiconductor super-junction device. The method includes: a p-type column is formed through an epitaxial process, and then a gate is formed in a self-alignment manner.
    Type: Grant
    Filed: September 22, 2020
    Date of Patent: April 11, 2023
    Assignee: SUZHOU ORIENTAL SEMICONDUCTOR CO., LTD.
    Inventors: Wei Liu, Yuanlin Yuan, Zhenyi Xu, Yi Gong
  • Patent number: 11626317
    Abstract: A semiconductor device has a first trench and a second trench of a trench structure located in a substrate. The second trench is separated from the first trench by a trench space that is less than a first trench width of the first trench and less than a second trench width of the second trench. The trench structure includes a doped sheath having a first conductivity type, contacting and laterally surrounding the first trench and the second trench. The doped sheath extends from the top surface to an isolation layer and from the first trench to the second trench across the trench space. The semiconductor device includes a first region and a second region, both located in the semiconductor layer, having a second, opposite, conductivity type. The first region and the second region are separated by the first trench, the second trench, and the doped sheath.
    Type: Grant
    Filed: October 24, 2020
    Date of Patent: April 11, 2023
    Assignee: Texas Instruments Incorporated
    Inventors: Binghua Hu, Ye Shao, John K Arch
  • Patent number: 11626522
    Abstract: A Schottky barrier diode includes a semiconductor substrate made of gallium oxide, a drift layer made of gallium oxide and provided on the semiconductor substrate, an anode electrode brought into Schottky contact with the drift layer, and a cathode electrode brought into ohmic contact with the semiconductor substrate. The drift layer has a plurality of trenches formed in a position overlapping the anode electrode in a plan view. Among the plurality of trenches, a trench positioned at the end portion has a selectively increased width. Thus, the curvature radius of the bottom portion of the trench is increased, or an edge part constituted by the bottom portion as viewed in a cross section is divided into two parts. As a result, an electric field to be applied to the bottom portion of the trench positioned at the end portion is mitigated, making dielectric breakdown less likely to occur.
    Type: Grant
    Filed: September 26, 2018
    Date of Patent: April 11, 2023
    Assignees: TDK CORPORATION, TAMURA CORPORATION, NOVEL CRYSTAL TECHNOLOGY, INC.
    Inventors: Jun Arima, Jun Hirabayashi, Minoru Fujita, Kohei Sasaki
  • Patent number: 11621279
    Abstract: A semiconductor device includes a semiconductor layer, a transistor cell portion, formed in the semiconductor layer, a first trench, formed in the semiconductor layer, a diode, electrically separated from the transistor cell portion and having a first conductivity type portion and a second conductivity type portion disposed inside the first trench, a second trench, formed in the semiconductor layer, and a bidirectional Zener diode, electrically connected to the transistor cell portion and having a pair of first conductivity type portions, disposed inside the second trench, and at least one second conductivity type portion, formed between the pair of first conductivity type portion.
    Type: Grant
    Filed: May 29, 2019
    Date of Patent: April 4, 2023
    Assignee: ROHM CO., LTD.
    Inventor: Ryuta Yaginuma
  • Patent number: 11600725
    Abstract: A semiconductor power device having shielded gate structure in an active area and trench field plate termination surrounding the active area is disclosed. A Zener diode connected between drain metal and source metal or gate metal for functioning as a SD or GD clamp diode. Trench field plate termination surrounding active area wherein only cell array located will not cause BV degradation when SD or GD poly clamped diode integrated.
    Type: Grant
    Filed: April 8, 2022
    Date of Patent: March 7, 2023
    Assignee: NAMI MOS CO., LTD.
    Inventor: Fu-Yuan Hsieh
  • Patent number: 11600309
    Abstract: Structures for 3D sense amplifiers for 3D memories are disclosed. A first embodiment uses one type of vertical transistors in constructing 3D sense amplifiers. A second embodiment uses both n- and p-type transistors for 3D sense amplifiers. Either or both of n- and p-type transistors are vertical transistors. The n- and p-type transistors may reside on different levels, or on the same level above a substrate if both are vertical transistors. In any embodiment, different options are available for gate contact formation. In any embodiments and options or alternatives thereof, one or more sense-enable circuits may be used. Sense amplifiers for several bit lines may be staggered on one or both sides of a memory array. Column multiplexers may be used to couple particular bit lines to data outputs. Bit-line multiplexers may be used to couple certain bit lines to shared 3D sense amplifiers.
    Type: Grant
    Filed: December 15, 2020
    Date of Patent: March 7, 2023
    Assignee: BESANG, INC.
    Inventor: Sang-Yun Lee
  • Patent number: 11581409
    Abstract: Disclosed is a transistor device which includes a semiconductor body having a first surface, a source region, a drift region, a body region being arranged between the source region and the drift region, a gate electrode adjacent the body region and dielectrically insulated from the body region by a gate dielectric, and a field electrode adjacent the drift region and dielectrically insulated from the drift region by a field electrode dielectric, wherein the field electrode comprises a first layer and a second layer, wherein the first layer has a lower electrical resistance than the second layer, wherein a portion of the second layer is disposed above and directly contacts a portion of the first layer.
    Type: Grant
    Filed: February 16, 2021
    Date of Patent: February 14, 2023
    Assignee: Infineon Technologies Austria AG
    Inventor: Thomas Feil
  • Patent number: 11575041
    Abstract: A method of current detection includes providing a transistor arrangement which comprises a drift and drain region arranged in a semiconductor body and each connected to a drain node, a plurality of load transistor cells each having a source region integrated in a first region of the semiconductor body, a plurality of sense transistor cells each having a source region integrated in a second region of the semiconductor body, a first source node electrically connected to the source region of each of the plurality of the load transistor cells via a first source conductor, and a second source node electrically connected to the source region of each of the plurality of the sense transistor cells via a second source conductor; and detecting a first current flowing between the drain node and the first source node of the transistor arrangement, wherein detecting the first current includes measuring a second current flowing between the drain node and the second source node of the transistor arrangement.
    Type: Grant
    Filed: November 25, 2020
    Date of Patent: February 7, 2023
    Assignee: Infineon Technologies Austria AG
    Inventor: Gerhard Noebauer
  • Patent number: 11569377
    Abstract: A semiconductor device according to an embodiment includes: a first electrode; and a substrate including a first surface in contact with the first electrode and a second surface provided opposite to the first surface, the first surface including a first groove including a first length and a second length shorter than the first length, the first length in a first direction parallel to the first surface, the second length in a second direction parallel to the first surface, the second direction intersecting with the direction, wherein the substrate includes a semiconductor layer having first conductive type, a first semiconductor region provided between the semiconductor layer and the second surface, the first semiconductor region having second conductive type, a second semiconductor region provided between the first semiconductor region and the second surface, the second semiconductor region having first conductive type higher than an impurity concentration of the semiconductor layer, and a second electrode pr
    Type: Grant
    Filed: February 26, 2021
    Date of Patent: January 31, 2023
    Assignees: KABUSHIKI KAISHA TOSHIBA, TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION
    Inventor: Hideharu Kojima
  • Patent number: 11552164
    Abstract: A semiconductor device comprises: a substrate; a well region provided in the substrate, having a second conductivity type; source regions having a first conductivity type; body tile regions having the second conductivity type, the source regions and the body tie regions being alternately arranged in a conductive channel width direction so as to form a first region extending along the conductive channel width direction, and a boundary where the edges of the source regions and the edges of the body tie regions are alternately arranged being formed on two sides of the first region; and a conductive auxiliary region having the first conductivity type, provided on at least one side of the first region, and directly contacting the boundary, a contact part comprising the edge of at least one source region on the boundary and the edge of at least one body tie region on the boundary.
    Type: Grant
    Filed: August 9, 2019
    Date of Patent: January 10, 2023
    Assignee: CSMC TECHNOLOGIES FAB2 CO., LTD.
    Inventors: Huajun Jin, Guipeng Sun
  • Patent number: 11551979
    Abstract: A method for manufacturing a semiconductor structure includes etching trenches in a semiconductor substrate to form a semiconductor fin between the trenches; converting sidewalls of the semiconductor fin into hydrogen-terminated surfaces each having silicon-to-hydrogen (S—H) bonds; after converting the sidewalls of the semiconductor fin into the hydrogen-terminated surfaces, depositing a dielectric material overfilling the trenches; and etching back the dielectric material to fall below a top surface of the semiconductor fin.
    Type: Grant
    Filed: October 23, 2020
    Date of Patent: January 10, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chen-Cheng Chou, Shiu-Ko Jangjian, Cheng-Ta Wu
  • Patent number: 11538932
    Abstract: The present application relates to a semiconductor transistor device that includes a Schottky diode electrically connected in parallel to a body diode formed between a body region and a drift region. A diode junction of the Schottky diode is formed adjacent to the drift region and is arranged vertically above a lower end of the body region.
    Type: Grant
    Filed: April 15, 2020
    Date of Patent: December 27, 2022
    Assignee: Infineon Technologies Austria AG
    Inventor: Ling Ma
  • Patent number: 11538914
    Abstract: A semiconductor device includes a semiconductor substrate, a gate dielectric, a gate electrode, and a pair of source/drain regions. The gate dielectric is disposed in the semiconductor substrate having an upper boundary lower than an upper surface of the semiconductor substrate, and an upper surface flush with the upper surface of the semiconductor substrate. The gate electrode is disposed over the gate dielectric having a first section over the upper boundary of the gate dielectric and a second section over the upper surface of the gate dielectric. The second section partially covers and partially exposes the upper surface of the gate dielectric. The pair of source/drain regions are disposed on opposing sides of the gate dielectric.
    Type: Grant
    Filed: April 7, 2021
    Date of Patent: December 27, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company Ltd.
    Inventors: Ta-Yuan Kung, Ruey-Hsin Liu, Chen-Liang Chu, Chih-Wen Yao, Ming-Ta Lei
  • Patent number: 11502084
    Abstract: A three-dimensional semiconductor memory device includes first semiconductor patterns, which are vertically spaced apart from each other on a substrate, each of which includes first and second end portions spaced apart from each other, and first and second side surfaces spaced apart from each other to connect the first and second end portions, first and second source/drain regions disposed in each of the first semiconductor patterns and adjacent to the first and second end portions, respectively, a channel region in each of the first semiconductor patterns and between the first and second source/drain regions, a first word line adjacent to the first side surfaces and the channel regions and vertically extended, and a gate insulating layer interposed between the first word line and the first side surfaces. The gate insulating layer may be extended to be interposed between the first source/drain regions.
    Type: Grant
    Filed: August 6, 2020
    Date of Patent: November 15, 2022
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Joongchan Shin, Changkyu Kim, Hui-Jung Kim, Iljae Shin, Taehyun An, Kiseok Lee, Eunju Cho, Hyungeun Choi, Sung-Min Park, Ahram Lee, Sangyeon Han, Yoosang Hwang
  • Patent number: 11488964
    Abstract: A method of manufacturing a semiconductor structure includes: receiving a substrate having an active region and a non-active region adjacent to the active region; forming an etch stop layer over the non-active region of the substrate, in which the etch stop layer is oxide-free; forming an isolation over the etch stop layer; removing a portion of the active region and a portion of the isolation to form a first trench in the active region and a second trench over the etch stop layer, respectively, in which a thickness of the etch stop layer beneath the second trench is greater than a depth difference between the first trench and the second trench; forming a dielectric layer in the first trench; and filling a conductive material on the dielectric layer in the first trench and in the second trench. A semiconductor structure is also provided.
    Type: Grant
    Filed: July 9, 2021
    Date of Patent: November 1, 2022
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventors: Ching-Chia Huang, Wei-Ming Liao
  • Patent number: 11482601
    Abstract: A vertical trench shield device can include a plurality of gate structures and a termination structure surrounding the plurality of gate structures. The plurality of gate structures can include a plurality of gate regions and a corresponding plurality of gate shield regions. The plurality of gate structures can be disposed between the plurality of source regions, and extending through the plurality of body regions to the drift region. The plurality of gate structures can be separated from each other by a first predetermined spacing in a core area. A first set of the plurality of gate structures can extend fully to the termination structure. The ends of a second set of the plurality of gate structures can be separated from the termination structure by a second predetermined spacing. The first and second spacings can be configured to balance charge in the core area and the termination area in a reverse bias condition.
    Type: Grant
    Filed: March 16, 2021
    Date of Patent: October 25, 2022
    Assignee: Vishay-Siliconix, LLC
    Inventors: Jun Hu, M. Ayman Shibib, Misbah Azam, Kyle Terrill
  • Patent number: 11467567
    Abstract: A method and a system for developing semiconductor device fabrication processes are provided. The developments of vertical and lateral semiconductor device fabrication processes can be integrated in the system. First, according to a target semiconductor device and a specification thereof, an initial target model and a general database are captured. The initial target model and the general database are compared to obtain a corresponding relationship. According to the corresponding relationship, multiple fixed fabrication parameters of the general database are applied to the initial target model, such that at least one adjustable parameter is defined. Thereafter, the parameter is set according to a setting instruction received through a user interface to produce a target model to be simulated. A simulation test is performed with the target model, and the adjustable parameter is modified until the simulation result of the target model satisfies a standard result.
    Type: Grant
    Filed: June 28, 2021
    Date of Patent: October 11, 2022
    Assignee: AICP TECHNOLOGY CORPORATION
    Inventor: Kei-Kang Hung
  • Patent number: 11462638
    Abstract: A SiC SJ trench MOSFET having first and second type gate trenches for formation of gate electrodes and super junction regions is disclosed. The gate electrodes are disposed into the first type gate trenches having a thick oxide layer on trench bottom. The super junction regions are formed surrounding the second type gate trenches filled up with the thick oxide layer. The device further comprises gate oxide electric field reducing regions adjoining lower surfaces of body regions and space apart from the gate trenches.
    Type: Grant
    Filed: October 19, 2020
    Date of Patent: October 4, 2022
    Assignee: NAMI MOS CO., LTD.
    Inventor: Fu-Yuan Hsieh
  • Patent number: 11456299
    Abstract: Some embodiments include an integrated assembly with a semiconductor-material-structure having a first source/drain region, a second source/drain region, and a channel region between the first and second source/drain regions. The semiconductor-material-structure has a first side and an opposing second side. A first conductive structure is adjacent to the first side and is operatively proximate the channel region to gatedly control coupling of the first and second source/drain regions through the channel region. A second conductive structure is adjacent to the second side and is spaced from the second side by an intervening region which includes a void. Some embodiments include methods of forming integrated assemblies.
    Type: Grant
    Filed: May 12, 2021
    Date of Patent: September 27, 2022
    Assignee: Micron Technology, Inc.
    Inventor: Sanh D. Tang
  • Patent number: 11430792
    Abstract: Provided is a DRAM including a substrate, first bit line structures, second bit line structures, and word line structures. The substrate has active regions each including pillar structures arranged along a first direction. Two first bit line structures extended along the first direction and buried in the substrate are disposed between the active regions arranged along a second direction. Each second bit line structure is located between the pillar structures and extended through the active regions along the second direction to be disposed on the first bit line structures and electrically connected to the first bit line structures. The word line structures are disposed on and spaced apart from the second bit line structures. Each word line structure extended along the second direction is located between the pillar structures and passes through the active regions arranged along the second direction. A manufacturing method of the DRAM is also provided.
    Type: Grant
    Filed: July 9, 2020
    Date of Patent: August 30, 2022
    Assignee: Winbond Electronics Corp.
    Inventors: Kai Jen, Hao-Chuan Chang
  • Patent number: 11410995
    Abstract: A semiconductor structure and a method for forming a semiconductor structure are provided. The semiconductor structure includes a well region extending in a first direction; a gate electrode disposed within the substrate and overlapping the well region; a gate dielectric layer disposed within the substrate and laterally surrounding the gate electrode; a plurality of first protection structures disposed over the gate electrode; a second protection structure extending in a second direction different from the first direction over the gate dielectric layer; and an insulating layer extending in the second direction between the second protection structure and the gate dielectric layer.
    Type: Grant
    Filed: May 14, 2021
    Date of Patent: August 9, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Jhu-Min Song, Chien-Chih Chou, Kong-Beng Thei, Fu-Jier Fan