In Integrated Circuit Structure Patents (Class 257/334)
  • Patent number: 11121250
    Abstract: In an element region and a non-element region, a silicon carbide semiconductor device includes a drift layer having a first conductivity type provided on a silicon carbide semiconductor substrate. In the element region, the silicon carbide semiconductor device includes a first trench that reaches the drift layer, and a gate electrode provided in the first trench through a gate insulation film and electrically connected to a gate pad electrode. In the non-element region, the silicon carbide semiconductor device includes a second trench whose bottom surface reaches the drift layer, a second relaxation region having a second conductivity type disposed below the second trench, an inner-surface insulation film provided on a side surface and on the bottom surface of the second trench, and a low-resistance region provided in the second trench through the inner-surface insulation film and electrically insulated from the gate pad electrode.
    Type: Grant
    Filed: February 19, 2018
    Date of Patent: September 14, 2021
    Assignee: MITSUBISHI ELECTRIC CORPORATION
    Inventor: Takaaki Tominaga
  • Patent number: 11114558
    Abstract: An integrated circuit comprising a surrounding gate transistor (SGT) MOSFET and a super barrier rectifier (SBR) is disclosed. The SBR horizontally disposed in different areas to the SGT MOSFET on single chip creates a low potential barrier for majority carrier in MOS channel, therefore has lower forward voltage and reverse leakage current than conventional Schottky Barrier Rectifier. Moreover, in some preferred embodiment, a multiple stepped oxide (MSO) structure is applied to the shielded gate structure to further reduce the on-resistance.
    Type: Grant
    Filed: October 18, 2019
    Date of Patent: September 7, 2021
    Assignee: NAMI MOS CO., LTD.
    Inventor: Fu-Yuan Hsieh
  • Patent number: 11101187
    Abstract: A semiconductor device includes a semiconductor layer of first-conductivity-type that has a main surface and that includes a boundary region set in a region between an active region and a current detection region at the main surface, a first body region of second-conductivity-type formed in a surface layer portion of the main surface at the active region, a first trench gate structure formed in the main surface at the active region, a second body region of the second-conductivity-type formed in the surface layer portion of the main surface at the current detection region, a second trench gate structure formed in the main surface at the current detection region, a well region of the second-conductivity-type formed in the surface layer portion of the main surface at the boundary region, and a dummy trench gate structure formed in an electrically floating state in the main surface at the boundary region.
    Type: Grant
    Filed: October 4, 2019
    Date of Patent: August 24, 2021
    Assignee: ROHM CO., LTD.
    Inventor: Jun Takaoka
  • Patent number: 11101346
    Abstract: This invention discloses a semiconductor power device formed on a semiconductor substrate comprises an active cell area and a termination area disposed near edges of the semiconductor substrate. The termination area comprises a plurality of duplicated units wherein each unit includes at least two trenches filled with a conductive trench material having a mesa area between adjacent trenches wherein the trenches and the mesa areas within each of the duplicated units are electrically shunt together. In the termination area each of the trenches in the duplicated units has a buried guard ring dopant region disposed below a bottom surface of the trenches.
    Type: Grant
    Filed: March 21, 2016
    Date of Patent: August 24, 2021
    Assignee: HUNTECH SEMICONDUCTOR (SHANGHAI) CO. LTD
    Inventors: Jun Hu, Zhiyun Luo, Fei Wang
  • Patent number: 11088142
    Abstract: Some embodiments include an integrated assembly with a semiconductor-material-structure having a first source/drain region, a second source/drain region, and a channel region between the first and second source/drain regions. The semiconductor-material-structure has a first side and an opposing second side. A first conductive structure is adjacent to the first side and is operatively proximate the channel region to gatedly control coupling of the first and second source/drain regions through the channel region. A second conductive structure is adjacent to the second side and is spaced from the second side by an intervening region which includes a void. Some embodiments include methods of forming integrated assemblies.
    Type: Grant
    Filed: December 26, 2019
    Date of Patent: August 10, 2021
    Assignee: Micron Technology, Inc.
    Inventor: Sanh D. Tang
  • Patent number: 11075274
    Abstract: A method of forming a conductive line construction comprises forming a structure comprising polysilicon-comprising material. Elemental titanium is directly against the polysilicon of the polysilicon-comprising material. Silicon nitride is directly against the elemental titanium. Elemental tungsten is directly against the silicon nitride. The structure is annealed to form a conductive line construction comprising the polysilicon-comprising material, titanium silicide directly against the polysilicon-comprising material, elemental tungsten, TiSixNy between the elemental tungsten and the titanium silicide, and one of (a) or (b), with (a) being the TiSixNy is directly against the titanium silicide, and (b) being titanium nitride is between the TiSixNy and the titanium silicide, with the TiSixNy being directly against the titanium nitride and the titanium nitride being directly against the titanium silicide. Structure independent of method is disclosed.
    Type: Grant
    Filed: January 18, 2019
    Date of Patent: July 27, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Kenichi Kusumoto, Yasutaka Iuchi, Akie Shimamura
  • Patent number: 11063146
    Abstract: Back-to-back power field-effect transistors with associated current sensors are disclosed. An example apparatus includes a first power field-effect transistor (FET) having a first source, and a second power FET having a second source. The first and second power FETs share a common drain. The first and second sources positioned on a first side of a substrate and the common drain positioned on a second side of the substrate opposite the first side. The example apparatus includes a current sensing FET positioned between a first portion of the first source of the first power FET and a second portion of the first source of the first power FET. The current sensing FET senses a current passing through the first and second power FETs.
    Type: Grant
    Filed: March 28, 2019
    Date of Patent: July 13, 2021
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventor: Indumini Ranmuthu
  • Patent number: 11038050
    Abstract: A wide band gap semiconductor device includes a semiconductor layer, a trench formed in the semiconductor layer, first, second, and third regions having particular conductivity types and defining sides of the trench, and a first electrode embedded inside an insulating film in the trench. The second region integrally includes a first portion arranged closer to a first surface of the semiconductor layer than to a bottom surface of the trench, and a second portion projecting from the first portion toward a second surface of the semiconductor layer to a depth below a bottom surface of the trench. The second portion of the second region defines a boundary surface with the third region, the boundary region being at an incline with respect to the first surface of the semiconductor layer.
    Type: Grant
    Filed: August 11, 2020
    Date of Patent: June 15, 2021
    Assignee: ROHM CO., LTD.
    Inventor: Kengo Omori
  • Patent number: 11018244
    Abstract: A method of manufacturing a semiconductor device includes: forming a trench in a first side of a semiconductor layer, the semiconductor layer including a drift zone of a first conductivity; forming a drain region of the first conductivity type in the first side of the semiconductor layer and laterally adjoining the drift zone; forming a body region of a second conductivity type opposite the first conductivity type and laterally adjoining the drift zone at a side of the drift zone opposite the drain region; and forming source regions of the first conductivity type and body contact regions of the second conductivity type in a sidewall of the trench and arranged in an alternating manner along a length of the trench, using a dopant diffusion process which includes diffusing dopants of both conductivity types from oppositely-doped dopant source layers which are in contact with different regions of the sidewall.
    Type: Grant
    Filed: October 18, 2019
    Date of Patent: May 25, 2021
    Assignee: Infineon Technologies Dresden GmbH & Co. KG
    Inventors: Andreas Meiser, Till Schloesser
  • Patent number: 10985242
    Abstract: In one embodiment, a power semiconductor device may include a semiconductor substrate, wherein the semiconductor substrate comprises an active device region and a junction termination region. The power semiconductor device may also include a polysilicon layer, disposed over the semiconductor substrate. The polysilicon layer may include an active device portion, disposed over the active device region, and defining at least one semiconductor device; and a junction termination portion, disposed over the junction termination region, the junction termination portion defining a ring structure.
    Type: Grant
    Filed: March 6, 2019
    Date of Patent: April 20, 2021
    Assignee: Littelfuse, Inc.
    Inventor: Kyoung Wook Seok
  • Patent number: 10950606
    Abstract: Dual fin endcaps for self-aligned gate edge architectures, and methods of fabricating dual fin endcaps for self-aligned gate edge architectures, are described. In an example, a semiconductor structure includes an I/O device having a first plurality of semiconductor fins disposed above a substrate and protruding through an uppermost surface of a trench isolation layer. A logic device having a second plurality of semiconductor fins is disposed above the substrate and protrudes through the uppermost surface of the trench isolation layer. A gate edge isolation structure is disposed between the I/O device and the logic device. A semiconductor fin of the first plurality of semiconductor fins closest to the gate edge isolation structure is spaced farther from the gate edge isolation structure than a semiconductor fin of the second plurality of semiconductor fins closest to the gate edge isolation structure.
    Type: Grant
    Filed: September 30, 2016
    Date of Patent: March 16, 2021
    Assignee: Intel Corporation
    Inventors: Walid M. Hafez, Roman W. Olac-Vaw, Chia-Hong Jan
  • Patent number: 10944012
    Abstract: An inverter that includes an n-type field effect transistor (nFET) and a p-type field effect transistor (pFET) vertically stacked one atop the other and containing a buried metal semiconductor alloy strap that connects a drain region of the nFET to a drain region of the pFET is provided. Also, provided is a cross-coupled inverter pair with nFETs and pFETs stacked vertically.
    Type: Grant
    Filed: January 2, 2019
    Date of Patent: March 9, 2021
    Assignee: International Business Machines Corporation
    Inventors: Alexander Reznicek, Kangguo Cheng, Karthik Balakrishnan, Pouya Hashemi
  • Patent number: 10943896
    Abstract: Power MOS device, in which a power MOS transistor has a drain terminal that is coupled to a power supply node, a gate terminal that is coupled to a drive node and a source terminal that is coupled to a load node. A detection MOS transistor has a drain terminal that is coupled to a detection node, a gate terminal that is coupled to the drive node and a source terminal that is coupled to the load node. A detection resistor has a first terminal coupled to the power supply node and a second terminal coupled to the detection node.
    Type: Grant
    Filed: April 27, 2018
    Date of Patent: March 9, 2021
    Assignee: STMicroelectronics S.r.l.
    Inventor: Davide Giuseppe Patti
  • Patent number: 10937899
    Abstract: A semiconductor device include a semiconductor substrate, a first trench electrode formed in the semiconductor substrate and having a first portion, a second trench electrode formed in the semiconductor substrate having a second portion facing the first portion, a floating layer of a first conductivity type formed around the first and second trench electrodes, a drift layer of a second conductivity type connected to the floating layer of the first conductivity type and formed between the first and second trench electrodes, an impurity layer of the first conductivity type connected to the drift layer of the second conductivity type and formed between the first and second trench electrodes, and a floating layer control gate having a portion located at least above the impurity layer of the first conductivity type.
    Type: Grant
    Filed: February 7, 2020
    Date of Patent: March 2, 2021
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventor: Nao Nagata
  • Patent number: 10923588
    Abstract: A semiconductor power device includes a plurality of power transistor cells each having a trenched gate disposed in a gate trench opened in a semiconductor substrate wherein a plurality of the trenched gates further include a shielded bottom electrode disposed in a bottom portion of the gate trench electrically insulated from a top gate electrode disposed at a top portion of the gate trench by an inter-electrode insulation layer. At least one of the shielded bottom electrode is connected a source metal and at least one of the top electrodes in the gate trench is connected to a source metal of the power device.
    Type: Grant
    Filed: July 29, 2018
    Date of Patent: February 16, 2021
    Assignee: HUNTECK SEMICONDUCTOR (SHANGHAI) CO. LTD
    Inventors: Jun Hu, Zhiyun Luo, Fei Wang, Mengyu Pan
  • Patent number: 10910492
    Abstract: A semiconductor device which can secure a high breakdown voltage and to which a simplified manufacturing process is applicable and a method for manufacturing the semiconductor device are provided. An n+ buried region has a floating potential. An n-type body region is located on a first surface side of the n+ buried region. A p+ source region is located in the first surface and forms a p-n junction with the n-type body region. A p+ drain region is located in the first surface spacedly from the p+ source region. A p-type impurity region PIR is located between the n+ buried region and the n-type body region and isolates the n+ buried region and the n-type body region from each other.
    Type: Grant
    Filed: July 16, 2018
    Date of Patent: February 2, 2021
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Hiroki Fujii, Atsushi Sakai, Takahiro Mori
  • Patent number: 10903322
    Abstract: Embodiments of SiC devices and corresponding methods of manufacture are provided. In some embodiments, the SiC device has shielding regions at the bottom of some gate trenches and non-linear junctions formed with the SiC material at the bottom of other gate trenches. In other embodiments, the SiC device has the shielding regions at the bottom of the gate trenches and arranged in rows which run in a direction transverse to a lengthwise extension of the trenches. In still other embodiments, the SiC device has the shielding regions and the non-linear junctions, and wherein the shielding regions are arranged in rows which run in a direction transverse to a lengthwise extension of the trenches.
    Type: Grant
    Filed: November 16, 2018
    Date of Patent: January 26, 2021
    Assignee: Infineon Technologies AG
    Inventors: Andreas Meiser, Caspar Leendertz, Anton Mauder
  • Patent number: 10886274
    Abstract: The present invention discloses a two-terminal vertical 1T-DRAM and a method of fabricating the same. According to one embodiment of the present invention, the two-terminal vertical 1T-DRAM includes a cathode layer formed of a first-type high-concentration semiconductor layer; a base region including a second-type low-concentration semiconductor layer formed on the cathode layer and a first-type low-concentration semiconductor layer formed on the second-type low-concentration semiconductor layer; and an anode layer formed of a second-type high-concentration semiconductor layer on the first-type low-concentration semiconductor layer.
    Type: Grant
    Filed: November 30, 2017
    Date of Patent: January 5, 2021
    Assignee: Industry-University Cooperation Foundation Hanyang University
    Inventors: Jea Gun Park, Seung Hyun Song, Min Won Kim
  • Patent number: 10872976
    Abstract: A transistor arrangement and a method are disclosed. The transistor arrangement includes: a drift and drain region arranged in a semiconductor body and connected to a drain node; a plurality of load transistor cells each including a source region integrated in a first region of the semiconductor body; a plurality of sense transistor cells each including a source region integrated in a second region of the semiconductor body; a first source node electrically connected to the source region of each load transistor cell via a first source conductor having a first area specific resistance; and a second source node electrically connected to the source region of each sense transistor cell via a second source conductor having a second area specific resistance. The area specific resistance of the second source conductor is greater than the area specific resistance of the first source conductor.
    Type: Grant
    Filed: January 15, 2019
    Date of Patent: December 22, 2020
    Assignee: Infineon Technologies Austria AG
    Inventor: Gerhard Noebauer
  • Patent number: 10868146
    Abstract: The disclosure relates to a method for producing a semiconductor device. The method includes providing a semiconductor body having first dopants of a first conductivity type and second dopants of a second conductivity type. The method also includes forming a first trench in the semiconductor body via a first mask, and filling the first trench with a semiconductor filling material. The method further includes forming a superjunction structure by introducing a portion of the first dopants from a region of the semiconductor body into the semiconductor filling material, forming a second trench in the semiconductor body via a second mask, which is formed in a manner self-aligned with respect to the first mask, and forming a trench structure in the second trench.
    Type: Grant
    Filed: May 10, 2019
    Date of Patent: December 15, 2020
    Assignee: Infineon Technologies AG
    Inventors: Andreas Meiser, Till Schloesser
  • Patent number: 10840362
    Abstract: A power semiconductor device includes an active cell region with a drift region, and IGBT cells at least partially arranged within the active cell region. Each IGBT cell includes at least one trench extending into the drift region along a vertical direction, an edge termination region surrounding the active cell region, and a transition region arranged between the active cell region and the edge termination region. The transition region has a width along a lateral direction from the active cell region towards the edge termination region. At least some of the IGBT cells are arranged within, or, respectively, extend into the transition region. An electrically floating barrier region of each IGBT cell is arranged within the active cell region and in contact with at least some of the trenches of the IGBT cells. The electrically floating barrier region does not extend into the transition region.
    Type: Grant
    Filed: October 23, 2018
    Date of Patent: November 17, 2020
    Assignee: Infineon Technologies AG
    Inventors: Alexander Philippou, Markus Bina, Matteo Dainese, Christian Jaeger, Johannes Georg Laven, Francisco Javier Santos Rodriguez, Antonio Vellei, Caspar Leendertz, Christian Philipp Sandow
  • Patent number: 10833081
    Abstract: Structures and methods that facilitate forming isolated contacts in stacked vertical transport field effect transistors (VTFETs). A pair of stacked VTFETs are formed on a substrate and isolated from each other. A via or hole is formed to extend to a drain of the second VTFET and a source of the first VTFET. The via is filled with a metal below the first VTFET to form the second contact. The second contact is capped with a non-conductive material and the remaining portion of the via is filled with metal to form the first contact. Alternatively, a via or hole is formed to extend to a source of the second VTFET and a source of the first VTFET. The second contact may serve as a local interconnect, a ground, or a voltage source connection.
    Type: Grant
    Filed: April 9, 2019
    Date of Patent: November 10, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Chen Zhang, Heng Wu, Joshua M. Rubin, Tenko Yamashita
  • Patent number: 10770549
    Abstract: A semiconductor device according to an embodiment includes a silicon carbide layer having a first and second plane, first and second trench extending in first direction, and in the silicon carbide layer, n-type first region, p-type second region between the n-type first region and the first plane and between the first and second trench, p-type fifth region covering bottom of the first trench, p-type sixth region covering bottom of the second trench, n-type seventh region between the fifth region and the second region, n-type eighth region between the sixth and second regions, p-type ninth regions contacting the fifth and second regions, and p-type tenth regions contacting the sixth region and the second region, the ninth and tenth regions repeatedly disposed in the first direction, and a line segment connecting the ninth region and the tenth region is oblique with respect to second direction perpendicular to the first direction.
    Type: Grant
    Filed: February 27, 2019
    Date of Patent: September 8, 2020
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Toshiyuki Oshima, Shinya Kyogoku, Ryosuke Iijima, Tatsuo Shimizu
  • Patent number: 10748905
    Abstract: Semiconductor devices are provided. A semiconductor device includes a substrate, and a source/drain region in the substrate. Moreover, the semiconductor device includes a gate structure in a recess in the substrate. The gate structure includes a liner that includes a first portion and a second portion on the first portion. The second portion is closer, than the first portion, to the source/drain region. The second portion includes a metal alloy. Methods of forming a semiconductor device are also provided.
    Type: Grant
    Filed: July 12, 2018
    Date of Patent: August 18, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Dong-jin Lee, Sang-kwan Kim, Ji-eun Lee, Sung-hak Cho, Seok-hyang Kim, So-yeon Shin
  • Patent number: 10727271
    Abstract: Memory devices include an array of memory cells including magnetic tunnel junction regions. The array of memory cells includes access lines extending in a first direction and data lines extending in a second direction transverse to the first direction. A common source includes first linear portions and second linear portions extending at an acute angle to each of the first direction and the second direction. Electronic systems include such a memory device operably coupled to a processor, to which at least one input device and at least one output device is operably coupled. Methods of forming such an array of memory cells including a common source.
    Type: Grant
    Filed: May 17, 2018
    Date of Patent: July 28, 2020
    Assignee: Micron Trechnology, Inc.
    Inventor: Shigeru Sugioka
  • Patent number: 10700191
    Abstract: A MOSFET used in a power conversion circuit including a reactor, a power source, the MOSFET, and a rectifier element, includes a semiconductor base substrate having an n-type column region and a p-type column region, the n-type column region and the p-type column region forming a super junction structure, the n-type column region and the p-type column region are formed such that a total amount of a dopant in the p-type column region is set higher than a total amount of a dopant in the n-type column region, and the MOSFET is configured to be operated in response to turning on of the MOSFET such that at a center of the n-type column region as viewed in a plan view, a low electric field region having lower field intensity than areas of the n-type column region other than the center of the n-type column region appears.
    Type: Grant
    Filed: September 16, 2016
    Date of Patent: June 30, 2020
    Assignee: SHINDENGEN ELECTRIC MANUFACTURING CO., LTD.
    Inventors: Daisuke Arai, Shigeru Hisada, Mizue Kitada, Takeshi Asada
  • Patent number: 10692979
    Abstract: A method of manufacturing a semiconductor device includes providing a silicon carbide (SiC) substrate, forming a SiC layer on a front surface of the SiC substrate, selectively forming a first region in the SiC layer at a surface thereof, forming a source region and a contact region in the first region, forming a gate insulating film on the SiC layer and on a portion of the first region between the SiC layer and the source region, forming a gate electrode on the gate insulating film above the portion of the first region, forming an interlayer insulating film covering the gate electrode, forming a source electrode electrically connected to the source region and the contact region, forming a drain electrode on a back surface of the SiC substrate, forming a barrier film on and covering the interlayer insulating film, and forming a metal electrode on the source electrode and the barrier film.
    Type: Grant
    Filed: July 25, 2019
    Date of Patent: June 23, 2020
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Yuichi Harada, Yasuyuki Hoshi, Akimasa Kinoshita, Yasuhiko Oonishi
  • Patent number: 10666140
    Abstract: In some examples, a device comprises an integrated circuit comprising a first transistor and a second transistor. The device further comprises an inductor comprising a first inductor terminal and a second inductor terminal, wherein the first inductor terminal is electrically connected to the first transistor and the second transistor. The device further comprises at least five electrical connections on a first side of the device.
    Type: Grant
    Filed: August 22, 2016
    Date of Patent: May 26, 2020
    Assignee: Infineon Technologies Americas Corp.
    Inventor: Eung San Cho
  • Patent number: 10658514
    Abstract: A gate-all around fin double diffused metal oxide semiconductor (DMOS) devices and methods of manufacture are disclosed. The method includes forming a plurality of fin structures from a substrate. The method further includes forming a well of a first conductivity type and a second conductivity type within the substrate and corresponding fin structures of the plurality of fin structures. The method further includes forming a source contact on an exposed portion of a first fin structure. The method further comprises forming drain contacts on exposed portions of adjacent fin structures to the first fin structure. The method further includes forming a gate structure in a dielectric fill material about the first fin structure and extending over the well of the first conductivity type.
    Type: Grant
    Filed: February 7, 2018
    Date of Patent: May 19, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: John B. Campi, Jr., Robert J. Gauthier, Jr., Rahul Mishra, Souvick Mitra, Mujahid Muhammad
  • Patent number: 10644104
    Abstract: A fin field effect transistor device with air gaps, including a source/drain layer on a substrate, one or more vertical fin(s) in contact with source/drain layer, a gate metal fill that forms a portion of a gate structure on each of the one or more vertical fin(s), and a bottom void space between the source/drain layer and the gate metal fill.
    Type: Grant
    Filed: September 25, 2018
    Date of Patent: May 5, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Hari V. Mallela, Robert R. Robison, Reinaldo A. Vega, Rajasekhar Venigalla
  • Patent number: 10622445
    Abstract: This invention discloses a metal oxide semiconductor field effect transistor (MOSFET) device. The MOSFET device has a semiconductor substrate that supports an epitaxial layer thereon. The epitaxial layer comprises at least three layers of different dopant concentrations and wherein a middle epitaxial layer having a varying dopant concentration profile along an upward vertical direction.
    Type: Grant
    Filed: August 22, 2018
    Date of Patent: April 14, 2020
    Assignee: HUNTECK SEMICONDUCTOR (SHANGHAI) CO. Ltd.
    Inventor: Jun Hu
  • Patent number: 10615263
    Abstract: A semiconductor device and methods for forming the same are provided. The method includes providing a substrate having a first conductive type, forming an epitaxial layer having the first conductive type on the substrate, forming a trench in the epitaxial layer, forming a first insulating layer in the trench and on the top surface of the epitaxial layer, forming a shield electrode and a mask layer on the first insulating layer in order, using the mask layer to remove a portion of the first insulating layer, wherein the top surface of the first insulating layer is higher than the top surface of the shield electrode after removing the portion of the first insulating layer, removing the mask layer, forming a second insulating layer on the first insulating layer and the shield electrode, and forming a gate electrode on the second insulating layer.
    Type: Grant
    Filed: June 11, 2018
    Date of Patent: April 7, 2020
    Assignee: VANGUARD INTERNATIONAL SEMICONDUCTOR CORPORATION
    Inventors: Tsung-Yeh Chen, Sheng-Wei Fu, Chung-Yeh Lee
  • Patent number: 10593813
    Abstract: A new semiconductor rectifier structure. In general, a MOS-transistor-like structure is located above a JFET-like deeper structure. The present application teaches ways to combine and optimize these two structures in a merged device so that the resulting combined structure achieves both a low forward voltage and a high reverse breakdown voltage in a relatively small area. In one class of innovative implementations, an insulated (or partially insulated) trench is used to define a vertical channel in a body region along the sidewall of a trench, so that majority carriers from a “source” region (typically n+) can flow through the channel. An added “pocket” diffusion, of the same conductivity type as the body region (p-type in this example), provides an intermediate region around the bottom of the trench. This intermediate diffusion, and an additional deep region of the same conductivity type, define a deep JFET-like device which is in series with the MOS channel portion of the diode.
    Type: Grant
    Filed: June 22, 2018
    Date of Patent: March 17, 2020
    Assignee: MaxPower Semiconductor Inc.
    Inventors: Richard A. Blanchard, Mohamed N. Darwish, Jun Zeng
  • Patent number: 10586845
    Abstract: According to an embodiment of a semiconductor device, the device includes gate trenches formed in a SiC substrate and extending lengthwise in parallel in a first direction. Rows of source regions of a first conductivity type are formed in the SiC substrate and extend lengthwise in parallel in a second direction which is transverse to the first direction. Rows of body regions of a second conductivity type opposite the first conductivity type are formed in the SiC substrate below the rows of source regions. Rows of body contact regions of the second conductivity type are formed in the SiC substrate. The rows of body contact regions extend lengthwise in parallel in the second direction. First shielding regions of the second conductivity type are formed deeper in the SiC substrate than the rows of body regions.
    Type: Grant
    Filed: November 16, 2018
    Date of Patent: March 10, 2020
    Assignee: Infineon Technologies AG
    Inventors: Thomas Aichinger, Wolfgang Bergner, Paul Ellinghaus, Rudolf Elpelt, Romain Esteve, Florian Grasse, Caspar Leendertz, Shiqin Niu, Dethard Peters, Ralf Siemieniec, Bernd Zippelius
  • Patent number: 10573654
    Abstract: Some embodiments include an integrated assembly having a paired-memory-cell-region within a memory-array-region. The paired-memory-cell-region includes a bitline-contact-structure between a first charge-storage-device-contact-structure and a second charge-storage-device-contact-structure. A first insulative region is between the bitline-contact-structure and the first charge-storage-device-contact-structure. A second insulative region is between the bitline-contact-structure and the second charge-storage-device-contact-structure. The first and second insulative regions both include a first semiconductor material which is in a nonconductive configuration. A transistor gate is over a peripheral region proximate the memory-array-region. The transistor gate has a second semiconductor material which is a same semiconductor composition and thickness as the first semiconductor material, but which is in a conductive configuration. Some embodiments include methods of forming integrated assemblies.
    Type: Grant
    Filed: June 18, 2018
    Date of Patent: February 25, 2020
    Assignee: Micron Technology, Inc.
    Inventor: Tsuyoshi Tomoyama
  • Patent number: 10535761
    Abstract: A semiconductor device including: a semiconductor substrate; a first gate trench portion and a dummy trench portion provided from an upper surface of the semiconductor substrate to a drift region, extending in the extending direction; a first transistor mesa portion sandwiched by the first gate trench portion and dummy trench portion; a base region contacting with the first gate trench portion above the drift region; an emitter region contacting with the same on the semiconductor substrate upper surface; and a second conductivity type region exposed on the semiconductor substrate upper surface, wherein the emitter region and second conductivity type region are arranged alternately in the extending direction; and the emitter region width in the extending direction contacting with the first gate trench portion is greater than the second conductivity type region width in the extending direction contacting with the same, will be provided.
    Type: Grant
    Filed: July 25, 2018
    Date of Patent: January 14, 2020
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventor: Tatsuya Naito
  • Patent number: 10529811
    Abstract: According to an embodiment of a power semiconductor device, the device includes a semiconductor body coupled to a first load terminal and a second load terminal and configured to conduct a load current between the first load terminal and the second load terminal. A trench extends into the semiconductor body along an extension direction and includes an insulator. A first electrode structure included in the trench is configured to control the load current. A second electrode structure included in the trench is arranged separately and electrically insulated from the first electrode structure. The first electrode structure and the second electrode structure are spatially displaced from each other along the extension direction such that they do not have a common extension range along the extension direction. Each of the first electrode structure and the second electrode structure is made of a metal.
    Type: Grant
    Filed: January 18, 2019
    Date of Patent: January 7, 2020
    Assignee: Infineon Technologies Austria AG
    Inventors: Thomas Feil, Michael Hutzler
  • Patent number: 10529845
    Abstract: In an embodiment, a semiconductor device includes a semiconductor body having a field effect transistor device with an active region and an edge termination region that surrounds the active region on all sides. The active region includes a first serpentine trench in the semiconductor body, a first field plate in the first serpentine trench, a second serpentine trench in the semiconductor body, and a second field plate in the second serpentine trench. The first serpentine trench is separate and laterally spaced apart from the second serpentine trench.
    Type: Grant
    Filed: March 9, 2018
    Date of Patent: January 7, 2020
    Assignee: Infineon Technologies Austria AG
    Inventors: Ashita Mirchandani, Thomas Feil, Maximilian Roesch, Britta Wutte
  • Patent number: 10490632
    Abstract: An integrated circuit includes a substrate and at least one component unfavorably sensitive to compressive stress which is arranged at least partially within an active region of the substrate limited by an insulating region. To address compressive stress in the active region, the circuit further includes at least one electrically inactive trench located at least in the insulating region and containing an internal area configured to reduce compressive stress in the active region. The internal area is filled with polysilicon. The polysilicon filled trench may further extend through the insulating region and into the substrate.
    Type: Grant
    Filed: January 7, 2019
    Date of Patent: November 26, 2019
    Assignee: STMicroelectronics (Rousset) SAS
    Inventors: Guilhem Bouton, Pascal Fornara, Christian Rivero
  • Patent number: 10446557
    Abstract: Provided are a semiconductor device having a gate and a method of forming the same. The method includes forming a gate dielectric, forming a first conductive material layer on the gate dielectric, forming a source material layer on the first conductive material layer, and diffusing a first element included in the source material layer into the first conductive material layer by performing a thermal treatment process to form a doped material layer.
    Type: Grant
    Filed: July 7, 2016
    Date of Patent: October 15, 2019
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Dongjin Lee, Ji-Eun Lee, Kyoung-Ho Jung, Satoru Yamada, Moonyoung Jeong
  • Patent number: 10424516
    Abstract: One embodiment provides a method of integrating a planar field-effect transistor (FET) with a vertical FET. The method comprises masking and etching a semiconductor of the vertical FET to form a fin, and providing additional masking, additional etching, doping and depositions to isolate a bottom source/drain (S/D) region. A dielectric is formed on the bottom S/D region to form a spacer. The method further comprises depositing gate metals, etching a vertical gate for the vertical FET and a planar gate for the planar FET using a shared gate mask, depositing dielectric, etching the dielectric to expose one or more portions of the fin, growing epitaxy on a top S/D region, masking and etching S/D contact openings for the bottom S/D region, forming silicide regions in S/D regions, depositing contact metal in the silicide regions to form contacts, and planarizing the contacts.
    Type: Grant
    Filed: March 28, 2018
    Date of Patent: September 24, 2019
    Assignee: International Business Machines Corporation
    Inventors: Brent A. Anderson, Edward J. Nowak
  • Patent number: 10411093
    Abstract: An active cell region, an edge termination region surrounding the active cell region and an intermediate region located at an intermediate position between these regions are provided, the active cell region has a trench gate type MOS structure on a top side, and a vertical structure on a bottom side includes a p-collector layer, an n-buffer layer on the p-collector layer, and an n-drift layer on the n-buffer layer, the n-buffer layer has a first buffer portion provided on the p-collector layer side, and a second buffer portion provided on the n-drift layer side, the peak impurity concentration of the first buffer portion is higher than the peak impurity concentration of the second buffer portion, and the impurity concentration gradient on the n-drift layer side of the second buffer portion is gentler than the impurity concentration gradient on the n-drift layer side of the first buffer portion.
    Type: Grant
    Filed: December 28, 2015
    Date of Patent: September 10, 2019
    Assignee: Mitsubishi Electric Corporation
    Inventors: Katsumi Nakamura, Tatsuo Harada, Noritsugu Nomura
  • Patent number: 10388724
    Abstract: An electronic chip includes a doped semiconductor substrate of a first conductivity type, a doped buried layer of a second conductivity type overlying the substrate, and a first doped well of the first conductivity type overlying the buried layer. Circuit components can be formed at a top surface of the first doped well and separated from the buried layer. A current detector is coupled to the buried layer and configured detect a bias current flowing into or out of the buried layer.
    Type: Grant
    Filed: October 16, 2018
    Date of Patent: August 20, 2019
    Assignee: STMICROELECTRONICS (ROUSSET) SAS
    Inventors: Clement Champeix, Nicolas Borrel, Alexandre Sarafianos
  • Patent number: 10366995
    Abstract: A semiconductor structure includes a substrate, and first isolation structures, at least one buried word line and at least one second isolation structure which are disposed in the substrate. The buried word line intersects the first isolation structures. The second isolation structure intersects the first isolation structures. A material of at least a portion of the second isolation structure is different from a material of the first isolation structures.
    Type: Grant
    Filed: May 15, 2018
    Date of Patent: July 30, 2019
    Assignee: Winbond Electronics Corp.
    Inventors: Wei-Che Chang, Yoshinori Tanaka
  • Patent number: 10355127
    Abstract: The present technique relates to a semiconductor device including a current sensor, which can improve the electrostatic discharge ruggedness. The semiconductor device includes: a first switching element through which a main current flows; and a second switching element through which a sense current flows. The first switching element includes a first gate oxide film formed in contact with a first base layer sandwiched between a first source layer and a drift layer. The second switching element includes a second gate oxide film formed in contact with a second base layer sandwiched between a second source layer and the drift layer. A part of the second gate oxide film including a portion covering the second base layer is thicker than the first gate oxide film.
    Type: Grant
    Filed: July 2, 2015
    Date of Patent: July 16, 2019
    Assignee: Mitsubishi Electric Corporation
    Inventor: Eisuke Suekawa
  • Patent number: 10347729
    Abstract: Devices and methods of fabricating integrated circuit devices for increasing performance through gate cut last processes are provided. One method includes, for instance: obtaining an intermediate semiconductor device having a substrate including a plurality of fins, an STI layer, an oxide layer, and a gate material over the oxide layer, the fins extending into the gate material; removing the gate material and the oxide layer; depositing a high k material on a top surface of the STI layer, surrounding the fins; depositing a gate stack over the high k material; filling the top of the device with a gate contact metal; etching a portion of the gate contact metal, the metal gate stack, and the high k material; and filling the portion with an inter-layer dielectric. Also disclosed is an intermediate device formed by the method.
    Type: Grant
    Filed: May 9, 2017
    Date of Patent: July 9, 2019
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Xusheng Wu, Haigou Huang
  • Patent number: 10312343
    Abstract: A device includes a vertical semiconductor switch including (i) a gate terminal and a first terminal provided on a substrate and (ii) a second terminal provided on the substrate, where the vertical semiconductor switch is configured to electrically connect or disconnect the first terminal and the second terminal, a first insulative film provided on the substrate, a second insulative film provided on the substrate, where the second insulative film is in contact with the first insulative film and thinner than the first insulative film, and a zener diode formed on the first insulative film and the second insulative film, where the zener diode includes a first portion that is formed on the first insulative film and connected to the first surface of the substrate and a second portion that is formed on the second insulative film and connected to the gate terminal.
    Type: Grant
    Filed: July 26, 2016
    Date of Patent: June 4, 2019
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventor: Shigemi Miyazawa
  • Patent number: 10249628
    Abstract: A semiconductor device includes a device isolation region defining an active region in a substrate, and gate structures buried in the active region of the substrate. At least one of the gate structures includes a gate trench, a gate insulating layer conformally formed on an inner wall of the gate trench, a gate barrier pattern conformally formed on the gate insulating layer disposed on a lower portion of the gate trench, a gate electrode pattern formed on the gate barrier pattern and filling the lower portion of the gate trench, an electrode protection layer conformally formed on the gate insulating layer disposed on an upper portion of the gate trench to be in contact with the gate barrier pattern and the gate electrode pattern, a buffer oxide layer conformally formed on the electrode protection layer, and a gate capping insulating layer formed on the buffer oxide layer to fill the upper portion of the gate trench.
    Type: Grant
    Filed: January 9, 2018
    Date of Patent: April 2, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventor: Min-Hee Cho
  • Patent number: 10249717
    Abstract: According to one embodiment, a semiconductor device includes a first electrode, a second electrode, first to fourth semiconductor regions and a first insulating film. The second electrode includes first, second, and third electrode regions. The first semiconductor region includes first, second, third, fourth, and fifth partial regions. The first partial region is separated from the first electrode. The second partial region is separated from the first electrode region. The fourth partial region is separated from the second electrode region. The second semiconductor region includes sixth, seventh, eighth and ninth partial regions. The third semiconductor region is connected to the second semiconductor region. The fourth semiconductor region is electrically connected to the second electrode. The fourth semiconductor region includes tenth, eleventh, and twelfth partial regions. The first insulating film is provided between the first, third, and fourth semiconductor regions.
    Type: Grant
    Filed: January 30, 2018
    Date of Patent: April 2, 2019
    Assignees: Kabushiki Kaisha Toshiba, Fuji Electric Co., Ltd.
    Inventors: Keiko Ariyoshi, Ryosuke Iijima, Shinya Kyogoku, Shinsuke Harada, Yusuke Kobayashi
  • Patent number: 10236340
    Abstract: In a general aspect, a power semiconductor device can include a first trench shield electrode and a second trench shield electrode defined in a semiconductor region, the first and second trench shield electrodes each having a first portion disposed in an active region and a second portion disposed in a termination region. A trench of the first trench shield electrode and a trench of the second trench shield electrode can define a mesa of the semiconductor region therebetween. The device can further include an implant enrichment region disposed in the termination region, the implant enrichment region can be intersected by the first trench shield electrode and the second trench shield electrode, and can have a portion disposed in the mesa of the semiconductor region, the portion extending from the trench of the first trench shield electrode to the trench of the second trench shield electrode.
    Type: Grant
    Filed: April 28, 2017
    Date of Patent: March 19, 2019
    Assignee: Semiconductor Components Industries, LLC
    Inventors: Joseph Yedinak, Xiaoli Wu