In Integrated Circuit Structure Patents (Class 257/334)
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Publication number: 20150054069Abstract: A semiconductor device for use in a power supply circuit has first and second MOSFETS. The source-drain path of one of the MOSFETS are coupled to the source-drain path of the other, and a load element is coupled to a connection node of the source-drain paths. The second MOSFET is formed on a semiconductor substrate with a Schottky barrier diode. First gate electrodes of the second MOSFET are formed in trenches in a first region of the semiconductor substrate, while second gate electrodes of the second MOSFET are formed in trenches in a second region of the semiconductor substrate. The first and second gate electrodes are electrically connected together. Portions of the Schottky barrier diode are formed between adjacent ones of the second gate electrodes. A center-to-center spacing between adjacent first gate electrodes is smaller than a center-to-center spacing between adjacent second gate electrodes.Type: ApplicationFiled: October 30, 2014Publication date: February 26, 2015Inventors: Nobuyuki SHIRAI, Nobuyoshi MATSUURA, Yoshito NAKAZAWA
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Patent number: 8963236Abstract: Provided are data storage devices and methods of manufacturing the same. The device may include a plurality of cell selection parts formed in a substrate, a plate conductive pattern covering the cell selection parts and electrically connected to first terminals of the cell selection parts, a plurality of through-pillars penetrating the plate conductive pattern and insulated from the plate conductive pattern, and a plurality of data storage parts directly connected to the plurality of through-pillars, respectively. The data storage parts may be electrically connected to second terminals of the cell selection parts, respectively.Type: GrantFiled: December 13, 2012Date of Patent: February 24, 2015Assignee: Samsung Electronics Co., Ltd.Inventors: Jungwoo Song, Jaekyu Lee
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Patent number: 8963235Abstract: A semiconductor structure of a trench power device comprises a base, an insulating layer, and a source conductive layer. The base includes a first trench etched from the top surface thereof, and two portions of the top surface arranged at two opposite sides of the first trench are respectively defined as two top contacting surfaces. Part of the first trench is filled with the insulating layer, and two inner walls of a non-filled portion of the first trench are respectively defined as two side contacting surfaces without contacting the insulating layer. The source conductive layer is embedded in the insulating layer. Thus, when a metallic layer is integrally formed on the semiconductor structure and connects the top contacting surfaces and the side contacting surfaces, the top contacting surfaces and the side contacting surfaces are configured to be a Schottky barrier interface.Type: GrantFiled: October 25, 2013Date of Patent: February 24, 2015Assignee: Sinopower Semiconductor, Inc.Inventor: Po-Hsien Li
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Patent number: 8963212Abstract: In one general aspsect, a semiconductor device can include at least a first device region and a second device region disposed at a surface of a semiconductor region where the second device region is adjacent to the first device region and spaced apart from the first device region. That semiconductor device can include a connection region disposed between the first device region and the second device region, and a trench extending into the semiconductor region and at least extending from the first device region, through the connection region, and to the second device region. The semiconductor device can include a dielectric layer lining opposing sidewalls of the trench, an electrode disposed in the trench, and a conductive trace disposed over a portion of the trench in the connection region and electrically coupled to a portion of the electrode disposed in the connection region.Type: GrantFiled: October 21, 2013Date of Patent: February 24, 2015Assignee: Fairchild Semiconductor CorporationInventors: Joseph A. Yedinak, Ashok Challa, Daniel M. Kinzer, Dean E. Probst, Daniel Calafut
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Patent number: 8963240Abstract: This invention discloses a semiconductor power device that includes a plurality of power transistor cells surrounded by a trench opened in a semiconductor substrate. At least one of the cells constituting an active cell has a source region disposed next to a trenched gate electrically connecting to a gate pad and surrounding the cell. The trenched gate further has a bottom-shielding electrode filled with a gate material disposed below and insulated from the trenched gate. At least one of the cells constituting a source-contacting cell surrounded by the trench with a portion functioning as a source connecting trench is filled with the gate material for electrically connecting between the bottom-shielding electrode and a source metal disposed directly on top of the source connecting trench.Type: GrantFiled: April 26, 2013Date of Patent: February 24, 2015Assignee: Alpha and Omega Semiconductor IncorporatedInventors: Anup Bhalla, Sik K. Lui
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Patent number: 8956940Abstract: An oxide termination semiconductor device may comprise a plurality of gate trenches, a gate runner, and an insulator termination trench. The gate trenches are located in an active region. Each gate trench includes a conductive gate electrode. The insulator termination trench is located in a termination region that surrounds the active region. The insulator termination trench is filled with an insulator material to form an insulator termination for the semiconductor device. Source and body regions inside the active region are at source potential and source and body regions outside the isolation trench are at drain potential. The device can be made using a three-mask or four-mask process.Type: GrantFiled: January 27, 2014Date of Patent: February 17, 2015Assignee: Alpha and Omega Semiconductor IncorporatedInventors: Sik Lui, Anup Bhalla
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Patent number: 8957474Abstract: A MOS transistor, can include a u-shaped cross-sectional channel region including spaced apart protruding portions separated by a trench and connected to one another by a connecting portion of the channel region at lower ends of the spaced apart protruding portions of the channel region. First and second impurity regions can be located at opposite ends of the -shaped cross-sectional channel region and separated from one another by the trench. A gate electrode can cover at least a planar face of the u-shaped cross-sectional channel region including the spaced apart protruding portions and the connecting portion and exposing the first and second impurity regions.Type: GrantFiled: May 15, 2013Date of Patent: February 17, 2015Assignee: Samsung Electronics Co., Ltd.Inventors: Dae-Ik Kim, Ji-Young Kim, Hyeong-Sun Hong
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Publication number: 20150041850Abstract: A semiconductor device includes a switching element having: a drift layer; a base region; an element-side first impurity region in the base region; an element-side gate electrode sandwiched between the first impurity region and the drift layer; a second impurity region contacting the drift layer; an element-side first electrode coupled with the element-side first impurity region and the base region; and an element-side second electrode coupled with the second impurity region, and a FWD having: a first conductive layer; a second conductive layer; a diode-side first electrode coupled to the second conductive layer; a diode-side second electrode coupled to the first conductive layer; a diode-side first impurity region in the second conductive layer; and a diode-side gate electrode in the second conductive layer sandwiched between first impurity region and the first conductive layer and having a first gate electrode as an excess carrier injection suppression gate.Type: ApplicationFiled: October 14, 2014Publication date: February 12, 2015Inventors: Hirotaka SAIKAKU, Tsuyoshi YAMAMOTO, Shoji MIZUNO, Masakiyo SUMITOMO, Tetsuo FUJII, Jun SAKAKIBARA, Hitoshi YAMAGUCHI, Yoshiyuki HATTORI, Rie TAGUCHI, Makoto KUWAHARA
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Patent number: 8952430Abstract: The present application relates to technology for improving a withstand voltage of a semiconductor device. The semiconductor device includes a termination area that surrounds a cell area. The cell area is provided with a plurality of main trenches. The termination area is provided with one or more termination trenches surrounding the cell area. A termination trench is disposed at an innermost circumference of one or more termination trenches. A body region is disposed on a surface of a drift region. Each main trench reaches the drift region. A gate electrode is provided within each main trench. The termination trench reaches the drift region. Sidewalls and a bottom surface of the termination trench are covered with a insulating layer. A surface of the insulating layer covering the bottom surface of the termination trench is covered with a buried electrode. A gate potential is applied to the buried electrode.Type: GrantFiled: June 2, 2011Date of Patent: February 10, 2015Assignees: Denso Corporation, Toyota Jidosha Kabushiki KaishaInventors: Hidefumi Takaya, Hideo Matsuki, Naohiro Suzuki, Tsuyoshi Ishikawa
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Publication number: 20150035006Abstract: A semiconductor device includes a first-conductivity-type semiconductor layer including an active region in which a transistor having impurity regions is formed and a marginal region surrounding the active region, a second-conductivity-type channel layer formed between the active region and the marginal region and forming a front surface of the semiconductor layer, at least one gate trench formed in the active region to extend from the front surface of the semiconductor layer through the channel layer, a gate insulation film formed on an inner surface of the gate trench, a gate electrode formed inside the gate insulation film in the gate trench, and at least one isolation trench arranged between the active region and the marginal region to surround the active region and extending from the front surface of the semiconductor layer through the channel layer, the isolation trench having a depth equal to that of the gate trench.Type: ApplicationFiled: October 17, 2014Publication date: February 5, 2015Inventor: Kenichi YOSHIMOCHI
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Publication number: 20150035051Abstract: This invention discloses a semiconductor power device disposed in a semiconductor substrate and the semiconductor substrate has a plurality of deep trenches. The deep trenches are filled with an epitaxial layer thus forming a top epitaxial layer covering areas above a top surface of the deep trenches covering over the semiconductor substrate. The semiconductor power device further includes a plurality of transistor cells disposed in the top epitaxial layer whereby a device performance of the semiconductor power device is dependent on a depth of the deep trenches and not dependent on a thickness of the top epitaxial layer. Each of the plurality of transistor cells includes a trench DMOS transistor cell having a trench gate opened through the top epitaxial layer and filled with a gate dielectric material.Type: ApplicationFiled: July 30, 2013Publication date: February 5, 2015Inventor: François Hébert
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Patent number: 8946816Abstract: Aspects of the present disclosure describe a high density trench-based power MOSFETs with self-aligned source contacts and methods for making such devices. The source contacts are self-aligned with spacers and the active devices may have a two-step gate oxide. A lower portion may have a thickness that is larger than the thickness of an upper portion of the gate oxide. The MOSFETS also may include a depletable shield in a lower portion of the substrate. The depletable shield may be configured such that during a high drain bias the shield substantially depletes. It is emphasized that this abstract is provided to comply with rules requiring an abstract that will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims.Type: GrantFiled: May 5, 2014Date of Patent: February 3, 2015Assignee: Alpha and Omega Semiconductor IncorporatedInventors: Madhur Bobde, Hamza Yilmaz, Sik Lui, Daniel Ng
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Publication number: 20150014767Abstract: A semiconductor device includes a semiconductor substrate including an active region defined by a device isolation film; a gate electrode filled in the active region; a bit line contact structure coupled to an active region between the gate electrodes; and a line-type bit line electrode formed over the bitline contact structure. The bit line contact structure includes a bit line contact formed over the active region; and an ohmic contact layer formed over the bit line contact.Type: ApplicationFiled: January 27, 2014Publication date: January 15, 2015Applicant: SK HYNIX INC.Inventor: Min Soo YOO
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Patent number: 8933501Abstract: A monolithic three dimensional NAND string includes a vertical semiconductor channel and a plurality of control gate electrodes in different device levels. The string also includes a blocking dielectric layer, a charge storage region and a tunnel dielectric. A first control gate electrode is separated from a second control gate electrode by an air gap located between the major surfaces of the first and second control gate electrodes and/or the charge storage region includes silicide nanoparticles embedded in a charge storage dielectric.Type: GrantFiled: January 28, 2014Date of Patent: January 13, 2015Assignee: SanDisk Technologies Inc.Inventors: Raghuveer S. Makala, Johann Alsmeier, Yao-Sheng Lee
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Patent number: 8932924Abstract: Exemplary power semiconductor devices with features providing increased breakdown voltage and other benefits are disclosed.Type: GrantFiled: October 21, 2013Date of Patent: January 13, 2015Assignee: Fairchild Semiconductor CorporationInventors: Joseph A. Yedinak, Dean E. Probst, Daniel Calafut
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Patent number: 8933509Abstract: A semiconductor device includes a device isolation structure, a recess channel structure, a first lower gate conductive layer conformal to the recess channel structure and defining a recess, a holding layer over the first lower gate conductive layer to fill the recess defined by the first lower gate conductive layer, and a second lower gate conductive layer over the first lower gate conductive layer and the holding layer. The holding layer is configured to hold a shift of the seam occurring in the recess channel structure.Type: GrantFiled: February 8, 2011Date of Patent: January 13, 2015Assignee: SK hynix Inc.Inventors: Shin Gyu Choi, Seung Chul Oh
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Publication number: 20150008517Abstract: A semiconductor device includes transistor cells with vertical channels perpendicular to a first surface of a semiconductor portion. A buried compensation structure in the semiconductor portion between the transistor cells and a second surface of the semiconductor portion parallel to the first surface includes first areas and second areas. The first and second areas are alternatingly arranged along a lateral direction parallel to the first surface. A contiguous impurity layer of a first conductivity type separates the transistor cells from the buried compensation structure.Type: ApplicationFiled: July 5, 2013Publication date: January 8, 2015Inventors: Anton Mauder, Katarzyna Kowalik-Seidl, Rolf Weis, Uwe Wahl
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Patent number: 8928073Abstract: A semiconductor device includes a substrate partitioned into a cell region, a peripheral circuit region, and an interface region between the cell region and the peripheral circuit region. A guard ring is provided in the interface region of the substrate and surrounds the cell region. A first gate structure is in the cell region, and a second gate structure is in the peripheral circuit region.Type: GrantFiled: March 6, 2013Date of Patent: January 6, 2015Assignee: Samsung Electronics Co., Ltd.Inventors: Se-myeong Jang, Sang-hyun Han, Hyo-dong Ban
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Patent number: 8928065Abstract: A termination structure for a power transistor includes a semiconductor substrate having an active region and a termination region. The substrate has a first type of conductivity. A termination trench is located in the termination region and extends from a boundary of the active region to within a certain distance of an edge of the semiconductor substrate. A doped region has a second type of conductivity disposed in the substrate below the termination trench. A MOS gate is formed on a sidewall adjacent the boundary. The doped region extends from below a portion of the MOS gate spaced apart from the boundary toward a remote sidewall of the termination trench. A termination structure oxide layer is formed on the termination trench and covers a portion of the MOS gate and extends toward the edge of the substrate. A first conductive layer is formed on a backside surface of the semiconductor substrate.Type: GrantFiled: October 21, 2010Date of Patent: January 6, 2015Assignee: Vishay General Semiconductor LLCInventors: Chih-Wei Hsu, Florin Udrea, Yih-Yin Lin
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Publication number: 20150001616Abstract: A Schottky diode includes first and second trenches formed in a semiconductor layer where the first and second trenches are lined with a thin dielectric layer and filled partially with a trench conductor layer with the remaining portion being filled with a first dielectric layer. Well regions are formed spaced-apart in a top portion of the semiconductor layer between the first and second trenches. A Schottky metal layer is formed on a top surface of the semiconductor layer between the first and second trenches. The Schottky diode is formed with the Schottky metal layer as the anode and the semiconductor layer between the first and second trenches as the cathode. The trench conductor layer in the first and second trenches is electrically connected to the anode of the Schottky diode. In one embodiment, the Schottky diode is formed integrated with a trench field effect transistor on the same semiconductor substrate.Type: ApplicationFiled: September 15, 2014Publication date: January 1, 2015Inventors: Daniel Calafut, Yi Su, Jongoh Kim, Hong Chang, Hamza Yilmaz, Daniel S. Ng
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Publication number: 20150001617Abstract: Methods of fabricating semiconductor devices may include forming first trenches in a substrate to define fin patterns and forming buried dielectric patterns filling lower regions of the first trenches. The first trenches extend in parallel. A gate dielectric layer is formed on upper inner sidewalls of the first trenches, and a gate conductive layer filling the first trenches is formed on the substrate including the gate dielectric layer. The gate conductive layer, the gate dielectric layer and the fin patterns are patterned to form second trenches crossing the first trenches and defining active pillars. Semiconductor devices may also be provided.Type: ApplicationFiled: September 17, 2014Publication date: January 1, 2015Inventors: Daeik KIM, HyeongSun HONG, Yongchul OH, Yoosang HWANG
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Publication number: 20140374825Abstract: Disclosed is a power semiconductor device that includes a plurality of source trenches and adjacent source regions. The plurality of source trenches extend from a top surface of a semiconductor substrate into the semiconductor substrate. The power semiconductor device further includes a plurality of gate trenches that extend from the top of the semiconductor substrate into the semiconductor substrate, and are arranged in hexagonal or zigzag patterns. A contiguous formation is created by the plurality of gate trenches, and the plurality of gate trenches separate the plurality of source trenches from one another.Type: ApplicationFiled: June 9, 2014Publication date: December 25, 2014Inventors: Kapil Kelkar, Timothy D. Henson, Ling Ma, Hugo Burke, Niraj Ranjan, Alain Charles
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Publication number: 20140374824Abstract: Aspects of the present disclosure describe a Schottky structure with two trenches formed in a semiconductor material. The trenches are spaced apart from each other by a mesa. Each trench may have first and second conductive portions lining the first and second sidewalls. The first and second portions of conductive material are electrically isolated from each other in each trench. The Schottky contact may be formed at any location between the outermost conductive portions. The Schottky structure may be formed in the active area or the termination area of a device die. It is emphasized that this abstract is provided to comply with rules requiring an abstract that will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims.Type: ApplicationFiled: June 25, 2013Publication date: December 25, 2014Inventors: Daniel Calafut, Yeeheng Lee
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Publication number: 20140374823Abstract: This invention discloses a semiconductor power device that includes an active cell area having a plurality of power transistor cells. Each of said power transistor cells has a planar Schottky diode that includes a Schottky junction barrier metal covering areas above gaps between separated body regions between two adjacent power transistor cells. The separated body regions further provide a function of adjusting a leakage current of said Schottky diode in each of said power transistor cells. Each of the planar Schottky diodes further includes a Shannon implant region disposed in a gap between the separated body regions of two adjacent power transistor cells for further adjusting a leakage current of said Schottky diode. Each of the power transistor cells further includes heavy body doped regions in the separated body regions next to source regions surrounding said Schottky diode forming a junction barrier Schottky (JBS) pocket region.Type: ApplicationFiled: June 24, 2013Publication date: December 25, 2014Inventors: Anup Bhalla, Xiaobin Wang, Moses Ho
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Patent number: 8916930Abstract: A trenched power semiconductor device on a lightly doped substrate is provided. The device has a base, a plurality of trenches including at least a gate trench, a plurality of first heavily doping regions, a body region, a source doped region, a contact window, a second heavily doped region, and a metal layer. The trenches are formed in the base. The first heavily doped regions are beneath the trenches respectively and spaced from the bottom of the respective trench with a lightly doped region. The body region encircles the trenches and is away from the first heavily doped region with a predetermined distance. The source doped region is in an upper portion of the body region. The contact window is adjacent to the edge of the base. The second heavily doped region is below the contact window filled by the metal layer for electrically connecting the second heavily doped region.Type: GrantFiled: September 1, 2011Date of Patent: December 23, 2014Assignee: Super Group Semiconductor Co., Ltd.Inventors: Yuan-Shun Chang, Yi-Yun Tsai, Kao-Way Tu
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Publication number: 20140367775Abstract: A semiconductor device and a method for forming the same can block a moving path of electrons between neighbor buried gates. A semiconductor device includes a device isolation film formed to define an active region over a semiconductor substrate. The semiconductor device also includes a plurality of buried gates formed over the active region, and a barrier film formed between neighboring buried gates from the plurality of buried gates.Type: ApplicationFiled: December 13, 2013Publication date: December 18, 2014Applicant: SK HYNIX INC.Inventor: Kyung Kyu MIN
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Patent number: 8907416Abstract: A semiconductor device and fabrication methods are disclosed. The device includes a plurality of gate electrodes formed in trenches located in an active region of a semiconductor substrate. A first gate runner is formed in the substrate and electrically connected to the gate electrodes, wherein the first gate runner surrounds the active region. A second gate runner is connected to the first gate runner and located between the active region and a termination region. A termination structure surrounds the first and second gate runners and the active region. The termination structure includes a conductive material in an insulator-lined trench in the substrate, wherein the termination structure is electrically shorted to a source or body layer of the substrate thereby forming a channel stop for the device.Type: GrantFiled: February 28, 2013Date of Patent: December 9, 2014Assignee: Alpha and Omega Semiconductor IncorporatedInventors: Sung-Shan Tai, Sik Lui, Xiaobin Wang
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Patent number: 8907415Abstract: A shielded gate trench metal oxide semiconductor filed effect transistor (MOSFET) having high switching speed is disclosed. The inventive shielded gate trench MOSFET includes a shielded electrode spreading resistance placed between a shielded gate electrode and a source metal to enhance the performance of the shielded gate trench MOSFET by adjusting doping concentration of poly-silicon in gate trenches to a target value. Furthermore, high cell density is achieved by employing the inventive shielded gate trench MOSFET without requirement of additional cost.Type: GrantFiled: May 16, 2011Date of Patent: December 9, 2014Assignee: Force Mos Technology Co., Ltd.Inventor: Fu-Yuan Hsieh
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Patent number: 8907413Abstract: A dual trench MOS transistor comprises of the following elements. A plurality of trenches are formed in an n? epitaxial layer on a heavy doped n+ semiconductor substrate and spaced to each other by one mesa. Each the trench has a trench oxide layer formed on a bottom and sidewalls thereof. A first polysilicon layer is formed in the trenches. A plurality of recesses are formed in the mesas and spaced to each other with one sub-mesa. Each the recess has a recess oxide layer formed on a bottom and sidewalls thereof. A second polysilicon layer for serving as a gate is formed in the recesses. The mesas are implanted to have implanted areas at two side of the gate. The implanted areas and the first polysilicon layer are applied to serve as the source. The rear surface of the substrate is served as the drain.Type: GrantFiled: December 2, 2013Date of Patent: December 9, 2014Assignee: Chip Integration Tech. Co., Ltd.Inventor: Qinhai Jin
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Patent number: 8907418Abstract: A semiconductor device includes a transistor array, including first transistors and second transistors. Gate electrodes of the first transistors are disposed in first trenches in a first main surface of a semiconductor substrate, and gate electrodes of the second transistors are disposed in second trenches in the first main surface. The first and second trenches are disposed in parallel to each other. The semiconductor device further includes a first gate conductive line in contact with the gate electrodes in the first trenches, a second gate conductive line in contact with the gate electrodes in the second trenches, and a control element configured to control the potential applied to the second gate conductive line.Type: GrantFiled: May 7, 2013Date of Patent: December 9, 2014Assignee: Infineon Technologies Austria AGInventors: Gerhard Noebauer, Christoph Kadow, Donald Dibra, Robert Illing
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Publication number: 20140353748Abstract: A field effect transistor (“FET”), a termination structure and associated method for manufacturing. The FET has a plurality of active transistor cells and a termination structure. The termination structure for the FET includes a plurality of termination cells arranged substantially in parallel from an inner side toward an outer side of a termination area of the FET. Each of the termination cells comprises a termination trench lined with a termination insulation layer and filled with a termination conduction layer. The innermost termination cell is electrically coupled to gate regions of the active transistor cells while the rest of the termination cells are electrically floating.Type: ApplicationFiled: May 29, 2014Publication date: December 4, 2014Applicant: Chengdu Monolithic Power Systems, Inc.Inventors: Rongyao Ma, Tiesheng Li, Huaifeng Wang
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Publication number: 20140353747Abstract: A trench gate MOSFET is provided. An N-type epitaxial layer is disposed on an N-type substrate. An N-type source region is disposed in the N-type epitaxial layer. The N-type epitaxial layer has at least one trench therein. An insulating layer serving as a gate insulating layer is disposed in the trench. A conductive layer serving as a gate fills up the trench. Two isolation structures are disposed in the N-type source region beside the trench and contact the trench. Two conductive plugs are disposed in the N-type epitaxial layer beside the trench and penetrate through the N-type source region. A dielectric layer is disposed on the N-type epitaxial layer. A metal layer is disposed on the dielectric layer and electrically connected to the N-type source region.Type: ApplicationFiled: February 26, 2014Publication date: December 4, 2014Applicant: BEYOND INNOVATION TECHNOLOGY CO., LTD.Inventor: Chien-Hsing Cheng
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Patent number: 8901630Abstract: A semiconductor device including a buried cell array transistor and an electronic device including the same are provided. The device includes a field region in a substrate and the filed region defines an active region. A first source/drain region and a second source/drain region are in the active region. A gate trench is between the first and second source/drain regions, and in the active region and the field region. A gate structure is within the gate trench. The gate structure includes a gate electrode, an insulating gate capping pattern on the gate electrode, a gate dielectric between the gate electrode and the active region, and an insulating metal-containing material layer between the insulating gate capping pattern and the active region.Type: GrantFiled: February 27, 2013Date of Patent: December 2, 2014Assignee: Samsung Electronics Co., Ltd.Inventors: Ki-Jae Huh, Satoru Yamada, Jun-Hee Lim, Sung-Ho Jang
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Patent number: 8901641Abstract: A semiconductor device with a super-junction structure is provided, including: a semiconductor substrate having a first conductivity type; an epitaxial layer having the first conductivity type formed over the semiconductor substrate; a first doping region having the first conductive type formed in a portion of the epitaxial layer; a second doping region having a second conductivity type formed in a portion of the of the epitaxial layer; a third doping region having the second conductivity type formed in a portion of the of the epitaxial layer, wherein the doping region partially comprises doped polysilicon materials having the second conductivity type; a gate dielectric layer formed over the epitaxial layer, partially overlying the well region; and a gate electrode formed over a portion of the gate dielectric layer.Type: GrantFiled: February 1, 2012Date of Patent: December 2, 2014Assignee: Vanguard International Semiconductor CorporationInventor: Tsung-Hsiung Lee
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Patent number: 8900950Abstract: A fabrication method of a high cell density trench power MOSFET structure is provided. Form at least a gate trench in a silicon substrate and a gate dielectric layer on the silicon substrate. Form a gate polysilicon structure in the gate trench and cover by a passivation layer. Form a first-conductive-type body region in the silicon substrate and implant impurities with a second conductive type thereof to form a source doped region. Expose the gate polysilicon structure and the source doped region. Form a dielectric spacer having a predetermined thickness on a sidewall of the gate trench. Deposit metal on the gate polysilicon structure and the source doped region. A first and a second self-aligned silicide layer are respectively formed on the gate polysilicon structure and the source doped region. The dielectric spacer forms an appropriate distance between the first and the second self-aligned silicide layer.Type: GrantFiled: March 20, 2012Date of Patent: December 2, 2014Assignee: Great Power Semiconductor Corp.Inventor: Hsiu-Wen Hsu
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Patent number: 8901647Abstract: A semiconductor device includes a first semiconductor element including a first pn junction between a first terminal and a second terminal. The semiconductor device further includes a semiconductor element including a second pn junction between a third terminal and a fourth terminal. The semiconductor element further includes a semiconductor body including the first semiconductor element and the second semiconductor element monolithically integrated. The first and third terminals are electrically coupled to a first device terminal. The second and fourth terminals are electrically coupled to a second device terminal. A temperature coefficient ?1 of a breakdown voltage Vbr1 of the first pn junction and a temperature coefficient ?2 of a breakdown voltage Vbr2 of the second pn junction have a same algebraic sign and satisfy 0.6×?1<?2<1.1×?1 at T=300 K, wherein Vbr2<Vbr1.Type: GrantFiled: November 9, 2012Date of Patent: December 2, 2014Assignee: Infineon Technologies AGInventors: Franz Hirler, Ulrich Glaser, Christian Lenzhofer
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Publication number: 20140346595Abstract: A semiconductor device includes a semiconductor device may include, but is not limited to, a semiconductor substrate, an isolation electrode, a gate electrode, a gate insulating film, and a first insulating film. The semiconductor substrate has a first groove and a second groove. An isolation electrode is positioned in the first groove. The gate electrode is positioned in the second groove. The gate insulating film is adjacent to the gate electrode. The first insulating film is adjacent to the isolation electrode. The isolation electrode is greater in threshold voltage than the gate electrode.Type: ApplicationFiled: August 7, 2014Publication date: November 27, 2014Inventor: Hiroaki TAKETANI
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Publication number: 20140346594Abstract: A semiconductor device with an embedded schottky diode and a manufacturing method thereof are provided. A semiconductor device having a schottky diode include: an epilayer of a first conductivity type, a body layer of a second conductivity type, and a source layer of the first conductivity type arranged in that order; a gate trench that extends from the source layer to a part of the epilayer; a body trench formed a predetermined distance from the gate trench and extends from the source layer to a part of the epilayer; and a guard ring of the second conductivity type that contacts an outer wall of the body trench and formed in the epilayer.Type: ApplicationFiled: August 27, 2013Publication date: November 27, 2014Applicant: MagnaChip Semiconductor, Ltd.Inventor: Francois HEBERT
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Publication number: 20140346593Abstract: A super-junction trench MOSFET with a short termination area is disclosed, wherein the short termination area comprising a charge balance region and a channel stop region formed near a top surface of an epitaxial layer with a trenched termination contact penetrating therethrough.Type: ApplicationFiled: May 22, 2013Publication date: November 27, 2014Applicant: Force Mos Technology Co., Ltd.Inventor: FU-YUAN HSIEH
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Publication number: 20140339631Abstract: Some embodiments of the present disclosure relate to a memory array comprising memory cells having vertical gate-all-around (GAA) selection transistors. In some embodiments, the memory array has a source region disposed within an upper surface of a semiconductor body, and a semiconductor pillar of semiconductor material extending outward from the upper surface of the semiconductor body and having a channel region and an overlying drain region. A gate region vertically overlies the source region at a position laterally separated from sidewalls of the channel region by a gate dielectric layer. A first metal contact couples the drain region to a data storage element that stores data. The vertical GAA selection transistors provide for good performance, while decreasing the size of the selection transistor relative to a planar MOSFET, so that the selection transistors do not negatively impact the size of the memory array.Type: ApplicationFiled: August 4, 2014Publication date: November 20, 2014Inventors: Yu-Wei Ting, Chi-Wen Liu, Chun-Yang Tsai, Kuo-Ching Huang
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Publication number: 20140339630Abstract: Aspects of the present disclosure describe a high density trench-based power MOSFETs with self-aligned source contacts and methods for making such devices. The source contacts are self-aligned with spacers that are formed along the sidewall of the gate caps. Additionally, the active devices may have a two-step gate oxide. A lower portion may have a thickness that is larger than the thickness of an upper portion of the gate oxide. The two-step gate oxide combined with the self-aligned source contacts allow for the production of devices with a pitch in the deep sub-micron level. It is emphasized that this abstract is provided to comply with rules requiring an abstract that will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims.Type: ApplicationFiled: July 11, 2014Publication date: November 20, 2014Inventors: Hamza Yilmaz, Madhur Bobde, Hong Chang, Yeeheng Lee, Daniel Calafut, Jongoh Kim, Sik Lui, John Chen
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Patent number: 8890242Abstract: A closed cell trenched power semiconductor structure is provided. The closed cell trenched power semiconductor structure has a substrate and cells. The cells are arranged on the substrate in an array. Every cell has a body and a trenched gate. The trenched gate surrounds the body. A side wall of the trenched gate facing body has a concave.Type: GrantFiled: February 23, 2012Date of Patent: November 18, 2014Assignee: Super Group Semiconductor Co., Ltd.Inventors: Yuan-Shun Chang, Kao-Way Tu, Yi-Yun Tsai
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Patent number: 8890252Abstract: A semiconductor device includes a switching element having: a drift layer; a base region; an element-side first impurity region in the base region; an element-side gate electrode sandwiched between the first impurity region and the drift layer; a second impurity region contacting the drift layer; an element-side first electrode coupled with the element-side first impurity region and the base region; and an element-side second electrode coupled with the second impurity region, and a FWD having: a first conductive layer; a second conductive layer; a diode-side first electrode coupled to the second conductive layer; a diode-side second electrode coupled to the first conductive layer; a diode-side first impurity region in the second conductive layer; and a diode-side gate electrode in the second conductive layer sandwiched between first impurity region and the first conductive layer and having a first gate electrode as an excess carrier injection suppression gate.Type: GrantFiled: July 26, 2011Date of Patent: November 18, 2014Assignee: DENSO CORPORATIONInventors: Hirotaka Saikaku, Tsuyoshi Yamamoto, Shoji Mizuno, Masakiyo Sumitomo, Tetsuo Fujii, Jun Sakakibara, Hitoshi Yamaguchi, Yoshiyuki Hattori, Rie Taguchi, Makoto Kuwahara
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Publication number: 20140332882Abstract: A method for manufacturing a Schottky diode comprising steps of 1) providing a region with a dopant of a second conductivity type opposite to a first conductivity type to form a top doped region in a semiconductor substrate of said first conductivity type; 2) providing a trench through the top doped region to a predetermined depth and providing a dopant of the second conductivity type to form a bottom dopant region of the second conductivity type; and 3) lining a Schottky barrier metal layer on a sidewall of the trench at least extending from a bottom of the top doped region to a top of the bottom doped region.Type: ApplicationFiled: May 13, 2013Publication date: November 13, 2014Inventors: SiK K. Lui, Anup Bhalla
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Publication number: 20140332881Abstract: A semiconductor device includes a transistor array, including first transistors and second transistors. Gate electrodes of the first transistors are disposed in first trenches in a first main surface of a semiconductor substrate, and gate electrodes of the second transistors are disposed in second trenches in the first main surface. The first and second trenches are disposed in parallel to each other. The semiconductor device further includes a first gate conductive line in contact with the gate electrodes in the first trenches, a second gate conductive line in contact with the gate electrodes in the second trenches, and a control element configured to control the potential applied to the second gate conductive line.Type: ApplicationFiled: May 7, 2013Publication date: November 13, 2014Inventors: Gerhard Noebauer, Christoph Kadow, Donald Dibra, Robert Illing
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Patent number: 8884366Abstract: A semiconductor device includes an active region having a sidewall, which has a sidewall step, a junction formed under a surface of the sidewall step, and a buried bit line configured to contact the junction.Type: GrantFiled: June 6, 2013Date of Patent: November 11, 2014Assignee: SK Hynix Inc.Inventors: Cha-Deok Dong, Gyu-Hyun Kim
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Patent number: 8883621Abstract: Provided is a semiconductor structure including a gate structure, a first spacer, and a second spacer. The gate structure is formed on a substrate and includes a gate material layer, a first hard mask layer disposed on the gate material layer, and a second hard mask layer disposed on the first hard mask layer. The first spacer is disposed on sidewalls of the gate structure. The second spacer is disposed adjacent to the first spacer. The etch rate of the first hard mask layer, the etch rate of the first spacer, and the etch rate of the second spacer are substantially the same and significantly smaller than the etch rate of the second hard mask layer in a rinsing solution.Type: GrantFiled: December 27, 2012Date of Patent: November 11, 2014Assignee: United Microelectronics Corp.Inventors: Chia-Jung Li, Po-Chao Tsao
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Patent number: 8878293Abstract: A semiconductor device includes an interlayer insulating layer on a substrate, and a direct contact (DC) structure vertically penetrating the interlayer insulating layer and contacting the substrate, the DC structure including a DC hole exposing the substrate, an insulating DC spacer on an inner wall of the DC hole, and a conductive DC plug on the DC spacer and filling the DC hole, the DC plug including a lower DC plug and an upper DC plug on the lower DC plug, the lower DC plug having a smaller horizontal width than that of the upper DC plug.Type: GrantFiled: February 15, 2013Date of Patent: November 4, 2014Assignee: Samsung Electronics Co., Ltd.Inventors: Hyeon-Woo Jang, Won-Chul Lee, Jin-Won Jeong
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Patent number: 8878285Abstract: A vertical semiconductor device having a vertical channel region is disclosed. The vertical semiconductor device includes a pillar having a vertical channel region, a bit line buried in a semiconductor substrate located at a lower part of the pillar, and a body connection unit configured to couple at least one sidewall of the pillar to the semiconductor substrate. As a result, the floating body effect of the vertical semiconductor device can be more effectively removed.Type: GrantFiled: December 18, 2012Date of Patent: November 4, 2014Assignee: SK Hynix Inc.Inventors: Seong Wan Ryu, Min Soo Yoo
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Publication number: 20140319606Abstract: This invention discloses a semiconductor power device that includes a plurality of power transistor cells surrounded by a trench opened in a semiconductor substrate. At least one of the cells constituting an active cell has a source region disposed next to a trenched gate electrically connecting to a gate pad and surrounding the cell. The trenched gate further has a bottom-shielding electrode filled with a gate material disposed below and insulated from the trenched gate. At least one of the cells constituting a source-contacting cell surrounded by the trench with a portion functioning as a source connecting trench is filled with the gate material for electrically connecting between the bottom-shielding electrode and a source metal disposed directly on top of the source connecting trench.Type: ApplicationFiled: April 26, 2013Publication date: October 30, 2014Inventors: Anup Bhalla, Sik K. Lui