With Means To Increase Breakdown Voltage Patents (Class 257/339)
  • Patent number: 10886400
    Abstract: A semiconductor device (1) includes a drain region (14) of a first conductivity type which includes a high-concentration drain region (14a), a first drain drift-region (14b), and a second drain drift-region (14c) of the first conductivity type, a source region (15) of the first conductivity type, a body region (16) of a second conductivity type, a gate insulating film (12), a gate electrode (13), and an STI insulating film (11) formed on the drain region (14). The second drain drift-region (14c) is formed from a first position (11f) of the STI insulating film (11) which is away from a first corner portion (11a) by a distance (x1) in a direction of a second corner portion (11b).
    Type: Grant
    Filed: June 5, 2019
    Date of Patent: January 5, 2021
    Assignee: ABLIC INC.
    Inventor: Hirofumi Shinohara
  • Patent number: 10886365
    Abstract: A silicon carbide semiconductor device has an n-type drift layer provided on a front surface of an n+-type silicon carbide substrate. In a surface layer of the n-type drift layer, a first p+-type region is provided. On a front surface side of the n+-type silicon carbide substrate, a trench is formed. The first p+-type region includes a deep first p+-type region and a shallow first p+-type region, the deep first p+-type region being at a position farther toward a drain electrode than a bottom of the trench is and the shallow first p+-type region being at a position closer to a source region than the bottom of the trench is. An impurity concentration of the shallow first p+-type region is lower than an impurity concentration of the deep first p+-type region.
    Type: Grant
    Filed: July 25, 2017
    Date of Patent: January 5, 2021
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Tsuyoshi Araoka, Yusuke Kobayashi
  • Patent number: 10720424
    Abstract: An ESD protection device includes a substrate structure having a substrate, first and second fins, and first and second doped regions having different conductivity types. The first doped region includes a first portion of the substrate and a first region of the first fin, the second doped region includes a second portion of the substrate, a second region of the first fin adjacent to the first region and the second fin. The ESD device also includes a first gate structure on a surface portion of the first region and on an entire surface of the second region of the first fin and including, from bottom to top, an interface layer on the surface portion of the first region and the surface portion of the second region of the first fin, a spacer, a high-k dielectric layer, a first work-function adjusting layer, a second work-function adjusting layer, and a gate.
    Type: Grant
    Filed: November 2, 2018
    Date of Patent: July 21, 2020
    Assignees: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATION, SEMICONDUCTOR MANUFACTURING INTERNATIONAL (BEIJING) CORPORATION
    Inventor: Yong Li
  • Patent number: 10629683
    Abstract: A semiconductor device includes a semiconductor substrate having a first conductivity type. First and second wells are located within the substrate, the first well being formed with a dopant of the first conductivity type, e.g. n-type, and the second well formed with a dopant of a second different conductivity type, e.g. p-type. A doped gap region is located between the first and second wells. The doped gap region is formed with a dopant of the second conductivity type, e.g. p-type, at a lower dopant concertation than the dopant concentration in the second well.
    Type: Grant
    Filed: December 29, 2017
    Date of Patent: April 21, 2020
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventor: Doug Weiser
  • Patent number: 10629727
    Abstract: In an embodiment, a semiconductor device includes a semiconductor substrate having a front surface, a LDMOS transistor in the front surface, and a metallization structure arranged on the front surface. The metallization structure includes at least one cavity arranged in at least one dielectric layer. Related methods of manufacture are also described.
    Type: Grant
    Filed: August 10, 2018
    Date of Patent: April 21, 2020
    Assignee: Infineon Technologies AG
    Inventors: Albert Birner, Helmut Brech, Matthias Zigldrum, Michaela Braun, Jan Ropohl
  • Patent number: 10622358
    Abstract: A method of manufacturing a semiconductor device is provided. The semiconductor device includes a semiconductor substrate, first and second fins on the semiconductor substrate and separated by a trench. The first fin includes a first portion having a first conductivity type and a second portion having a second conductivity type different from the first conductivity type, the first and second portions are adjacent to each other, and the second portion connected to the second fin through the semiconductor substrate. The semiconductor device also includes a gate structure on the first and second portions and including a gate insulator layer on the first and second portions, a gate on a portion of the gate insulator layer on the first portion, and a dummy gate on the second portion and including an insulating layer or an undoped semiconductor layer and adjacent to the gate.
    Type: Grant
    Filed: May 23, 2019
    Date of Patent: April 14, 2020
    Assignees: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (BEIJING) CORPORATION, SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATION
    Inventors: Fei Zhou, Zhongshan Hong
  • Patent number: 10622474
    Abstract: A Lateral Diffusion Metal Oxide Semiconductor (LDMOS) device and its manufacturing method are presented. The LDMOS device comprises a first region that has a first conductivity type; a drift region that has a second conductivity type in the first region, wherein the second conductivity type is opposite to the first conductivity type; and a plurality of second regions that have the first conductivity type in the drift region, wherein the second regions are separated from each other and extend to the first region along a depth direction of the drift region. This LDMOS device has an higher Breakdown Voltage and thus better performance than conventional LDMOS devices.
    Type: Grant
    Filed: July 17, 2019
    Date of Patent: April 14, 2020
    Assignees: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATION, SEMICONDUCTOR MANUFACTURING INTERNATIONAL (BEIJING) CORPORATION
    Inventor: Lei Fang
  • Patent number: 10622440
    Abstract: A high voltage MOS device includes: a first drift region with a first conductive type, a body region with a second conductive type, plural second drift regions with the second conductive type, a gate, a source region with the first conductive type, a drain with the first conductive type, and a body contact region with the second conductive type. The plural second drift regions contact the body region along the lateral direction, and are located separately in the width direction. Any neighboring two second drift regions do not contact each other. Each of the second drift regions is separated from the drain by the first drift region.
    Type: Grant
    Filed: November 29, 2018
    Date of Patent: April 14, 2020
    Assignee: RICHTEK TECHNOLOGY CORPORATION
    Inventors: Tsung-Yi Huang, Chu-Feng Chen
  • Patent number: 10586865
    Abstract: A dual-gate metal-oxide-semiconductor field-effect transistor (MOSFET) may include a MOSFET having a channel region, a drain, and a source, a first gate formed proximate to the channel region, a drain extension region formed proximate to the drain, and a second gate formed proximate to the drain extension region.
    Type: Grant
    Filed: September 29, 2017
    Date of Patent: March 10, 2020
    Assignee: Cirrus Logic, Inc.
    Inventors: Scott Warrick, Justin Dougherty, Alexander Barr, Christian Larsen, Marc L. Tarabbia, Ying Ying
  • Patent number: 10580856
    Abstract: A structure for improved noise signal isolation in semiconductor devices. In one embodiment, the structure includes a second-conductivity type substrate, a 1st first-conductivity type well, a 1st first-conductivity type layer, a second-conductivity type layer positioned between the 1st first-conductivity type well and the 1st first-conductivity type layer. The structure also includes a 2nd first-conductivity type well, and a 2nd first-conductivity type layer positioned between the 2nd first-conductivity type well and the 1st first-conductivity type layer. The 1st first-conductivity type layer and the second-conductivity type layer are positioned between the P type substrate and the 1st first-conductivity type well, and the 1st first-conductivity type well is laterally separated from the 2nd first-conductivity type well.
    Type: Grant
    Filed: June 19, 2018
    Date of Patent: March 3, 2020
    Assignee: NXP USA, Inc.
    Inventors: Radu Mircea Secareanu, Bernhard Grote
  • Patent number: 10522677
    Abstract: A transistor includes a trench formed in a semiconductor substrate with the trench having a first sidewall and a second sidewall. A vertical field plate is formed in the trench and the vertical field plate is located between the first sidewall and the second sidewall. A gate electrode is formed in the trench with a first edge of the gate electrode proximate to the first sidewall and a second edge of the gate electrode proximate to the vertical field plate. A first dielectric material is formed in the trench between the first sidewall and the vertical field plate. A second dielectric material is formed in the trench between the vertical field plate and the second sidewall with the second dielectric material having a dielectric constant lower than that of the first dielectric material.
    Type: Grant
    Filed: September 26, 2017
    Date of Patent: December 31, 2019
    Assignee: NXP USA, INC.
    Inventors: Saumitra Raj Mehrotra, Ljubo Radic, Bernhard Grote
  • Patent number: 10476383
    Abstract: The disclosure relates to a negative charge pump circuit including a first capacitor; a first selector switch; a second selector switch; and a control circuit designed to, in a first phase of operation, alternately control the first and second selector switches in a first configuration in which the first and second electrodes of the first capacitor are respectively linked to the first and second nodes and in a second configuration in which the first and second electrodes of the first capacitor are respectively linked to the second and third nodes. In a second phase of operation, the control circuit forces the first selector switch to link the first electrode of the first capacitor to the second node and control the second selector switch so as to alternately link the second electrode of the first capacitor to the second and to the third node.
    Type: Grant
    Filed: June 19, 2018
    Date of Patent: November 12, 2019
    Assignee: STMicroelectronics SA
    Inventor: Thierry Di Gilio
  • Patent number: 10460942
    Abstract: A semiconductor structure includes a substrate, at least one active semiconductor fin, at least one insulating structure, a gate electrode, and a gate dielectric. The active semiconductor fin is disposed on the substrate. The insulating structure is disposed on the substrate and adjacent to the active semiconductor fin. A top surface of the insulating structure is non-concave and is lower than a top surface of the active semiconductor fin. The gate electrode is disposed over the active semiconductor fin. The gate dielectric is disposed between the gate electrode and the active semiconductor fin.
    Type: Grant
    Filed: September 26, 2017
    Date of Patent: October 29, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Che-Cheng Chang, Po-Chi Wu, Chih-Han Lin, Horng-Huei Tseng
  • Patent number: 10453917
    Abstract: An n-type region and a p-type region of a first parallel pn layer are arranged parallel to a base front surface, in a striped planar layout extending from an active region over an edge termination region. In the n-type region, a gate trench extending linearly along a first direction is provided. In an intermediate region, in a surface region on the base front surface side of the first parallel pn layer, a second parallel pn layer is provided. The second parallel pn layer is arranged having a repetition cycle shifted along a second direction ½ a cell with respect to a repetition cycle of the n-type region and the p-type region of the first parallel pn layer. A gate trench termination portion terminates in the intermediate region between the active region and the edge termination region, and is covered by the p-type region of the second parallel pn layer.
    Type: Grant
    Filed: January 31, 2019
    Date of Patent: October 22, 2019
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Isamu Sugai, Takeyoshi Nishimura
  • Patent number: 10424655
    Abstract: A method for forming a high voltage device is disclosed. The method comprises providing a substrate defined with a high voltage device region. A device well is formed to encompass the high voltage device region. A drift region is formed within the device well. A body well is formed within the device well adjacent to the drift region. A variable thickness gate dielectric is formed on the substrate. Forming the variable thickness gate dielectric comprises patterned a sacrificial polysilicon layer and oxidizing the patterned sacrificial polysilicon layer to define a thick gate oxide having sloped sidewalls. A gate electrode is formed on the variable thickness gate dielectric, wherein the gate electrode partially overlaps the thick gate oxide. A first and a second source/drain (S/D) region is formed adjacent to first and second sides of the variable thickness gate dielectric.
    Type: Grant
    Filed: December 15, 2017
    Date of Patent: September 24, 2019
    Assignee: GLOBALFOUNDRIES SINGAPORE PTE. LTD.
    Inventors: Ming Li, Jeoung Mo Koo, Raj Verma Purakh
  • Patent number: 10403750
    Abstract: A Lateral Diffusion Metal Oxide Semiconductor (LDMOS) device and its manufacturing method are presented. The LDMOS device comprises a first region that has a first conductivity type; a drift region that has a second conductivity type in the first region, wherein the second conductivity type is opposite to the first conductivity type; and a plurality of second regions that have the first conductivity type in the drift region, wherein the second regions are separated from each other and extend to the first region along a depth direction of the drift region. This LDMOS device has an higher Breakdown Voltage and thus better performance than conventional LDMOS devices.
    Type: Grant
    Filed: January 10, 2018
    Date of Patent: September 3, 2019
    Assignees: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATION, SEMICONDUCTOR MANUFACTURING INTERNATIONAL (BEIJING) CORPORATION
    Inventor: Lei Fang
  • Patent number: 10396204
    Abstract: A semiconductor device includes: a gate structure extending along a first direction on a substrate, in which the gate structure includes a first edge and a second edge extending along the first direction; a first doped region adjacent to one side of the gate structure, in which the first doped region includes a third edge and a fourth edge extending along the first direction; a second doped region adjacent to another side of the gate structure, in which the second doped region comprises a fifth edge and a sixth edge extending along the first direction; a first fin-shaped structure extending from the second edge of the gate structure toward the third edge of the first doped region; and a second fin-shaped structure extending from the first edge of the gate structure toward the sixth edge of the second doped region.
    Type: Grant
    Filed: September 11, 2017
    Date of Patent: August 27, 2019
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Che-Wei Chang, Chun-Hsiung Wang, Chih-Wei Chen
  • Patent number: 10326016
    Abstract: A high-side device includes: a substrate, an epitaxial layer, a high voltage well, a body region, a gate, a source, a drain, and a buried region. A channel junction is formed between the body region and the high voltage well. The buried region is formed in the substrate and the epitaxial layer, and in a vertical direction, a part of the buried region is located in the substrate and another part of the buried region is located in the epitaxial layer. In the channel direction, an inner side boundary of the buried region is between the drain and the channel junction. An impurity concentration of a second conductive type of the buried region is sufficient to prevent the high voltage well between the channel junction and the drain from being completely depleted when the high-side power device operates in a conductive operation. A corresponding manufacturing method is also disclosed.
    Type: Grant
    Filed: July 17, 2018
    Date of Patent: June 18, 2019
    Assignee: RICHTEK TECHNOLOGY CORPORATION
    Inventor: Tsung-Yi Huang
  • Patent number: 10325981
    Abstract: A high-side device includes: a substrate, an epitaxial layer, a high voltage well, a body region, a gate, a source, a drain, two buried regions. A PN junction is formed between the body region and the high voltage well, wherein the PN junction is perpendicular to a channel direction. One buried region is formed in the epitaxial layer and has a first conductive type, wherein an inner side boundary thereof is located between the drain and the PN junction. The other buried region is formed in the substrate and in the epitaxial layer and has a second conductive type, wherein an inner side boundary thereof is located between the drain and the PN junction. The impurity concentration of the second buried region is sufficient to prevent the high voltage well between the PN junction and the drain from being completely depleted when the high-side power device is ON.
    Type: Grant
    Filed: March 1, 2018
    Date of Patent: June 18, 2019
    Assignee: RICHTEK TECHNOLOGY CORPORATION
    Inventor: Tsung-Yi Huang
  • Patent number: 10290624
    Abstract: Disclosed is an ESD protection device, comprising: a semiconductor substrate; a semiconductor buried layer located in the semiconductor substrate; an epitaxial semiconductor layer located on the semiconductor substrate and comprising a first doped region and a second doped region, wherein the semiconductor substrate and the first doped region are of a first doping type, the semiconductor buried layer, the epitaxial semiconductor layer and the second doped region are of a second doping type, the first doping type and the second doping type are opposite to each other, and the first doped region forms a plurality of interfaces with the epitaxial semiconductor layer. The disclosure improves protection performance and maximum current bearing capacity without increasing parasitic capacitance of the ESD protection device.
    Type: Grant
    Filed: October 11, 2017
    Date of Patent: May 14, 2019
    Assignee: Silergy Semiconductor Technology (Hangzhou) Ltd.
    Inventors: Fei Yao, Shijun Wang, Dengping Yin
  • Patent number: 10283587
    Abstract: A semiconductor device—e.g., a super junction power MOSFET—includes a number of columns of one type of dopant formed in a region of another type of dopant. Generally speaking, the columns are modulated in some manner. For example, the widths (e.g., diameters) of some columns are greater than the widths of other columns.
    Type: Grant
    Filed: February 6, 2018
    Date of Patent: May 7, 2019
    Assignee: VISHAY-SILICONIX
    Inventors: Deva Pattanayak, Olof Tornblad
  • Patent number: 10276666
    Abstract: On a front surface of an n+-type SiC substrate becoming a drain region, an n?-type drift layer, a p-type base layer, and an n+-type source layer are sequentially formed by epitaxial growth. In the n+-type source layer, the p+-type contact region is selectively provided. A trench is provided penetrating the n+-type source layer and the p-type base layer in the depth direction and reaching the n?-type drift layer. In the trench, a gate electrode is provided via a gate insulating film. A width between adjacent trenches is, for example, 1 ?m or less. A depth of the trench is, for example, 1 ?m or less. The width is narrow whereby substantially the entire p-type base layer forms a channel. A cell includes a FinFET structure in which one channel is sandwiched between MOS gates on both side. Thus, ON resistance may be reduced and decreased reliability may be prevented.
    Type: Grant
    Filed: August 30, 2017
    Date of Patent: April 30, 2019
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Yasuyuki Hoshi, Masahito Otsuki, Shoji Yamada, Takashi Shiigi
  • Patent number: 10262908
    Abstract: A method for manufacturing a semiconductor device includes the steps of: determining a first design dimension of a gate electrode of a selection MISFET, a second design dimension of a sidewall insulating film, and initial setting conditions for ion implantation for a high-concentration semiconductor region; forming the gate electrode; measuring a first processed dimension of the gate electrode; implanting ions to form a low-concentration semiconductor region at each end of the gate electrode; forming the sidewall insulating film over a sidewall of the gate electrode; measuring a second processed dimension of the sidewall insulating film; and implanting ions to form a high-concentration semiconductor region. In the former implantation step, execution conditions to the initial setting conditions are reset according to a deviation of the first processed dimension from the first design dimension and a deviation of the second processed dimension from the second design dimension, and the step is executed.
    Type: Grant
    Filed: February 10, 2017
    Date of Patent: April 16, 2019
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventor: Kaoru Mori
  • Patent number: 10243051
    Abstract: Disclosed is a transistor device and a method for producing a transistor device. The transistor device includes: a source region, a drift region, and a body region arranged between the source region and the drift region; a gate electrode adjacent the body region and dielectrically insulated from the body region by a gate dielectric; and a field electrode adjacent the drift region and dielectrically insulated from the drift region by a field electrode dielectric. The field electrode includes at least two layers of different electrically conductive materials.
    Type: Grant
    Filed: July 31, 2017
    Date of Patent: March 26, 2019
    Assignee: Infineon Technologies Austria AG
    Inventor: Thomas Feil
  • Patent number: 10234486
    Abstract: Vertical sense devices in vertical trench MOSFET. In accordance with an embodiment of the present invention, an electronic circuit includes a vertical trench metal oxide semiconductor field effect transistor configured for switching currents of at least one amp and a current sensing field effect transistor configured to provide an indication of drain to source current of the MOSFET. A current sense ratio of the current sensing FET is at least 15 thousand and may be greater than 29 thousand.
    Type: Grant
    Filed: August 19, 2015
    Date of Patent: March 19, 2019
    Assignee: VISHAY/SILICONIX
    Inventors: M. Ayman Shibib, Wenjie Zhang
  • Patent number: 10236376
    Abstract: A high-side device includes: a substrate, an epitaxial layer, a high voltage well, a body region, a gate, a source, a drain, and a buried region. A channel junction is formed between the body region and the high voltage well. The buried region is formed in the substrate and the epitaxial layer, and in a vertical direction, a part of the buried region is located in the substrate and another part of the buried region is located in the epitaxial layer. In the channel direction, an inner side boundary of the buried region is between the drain and the channel junction. An impurity concentration of a second conductive type of the buried region is sufficient to prevent the high voltage well between the channel junction and the drain from being completely depleted when the high-side power device operates in a conductive operation. A corresponding manufacturing method is also disclosed.
    Type: Grant
    Filed: July 17, 2018
    Date of Patent: March 19, 2019
    Assignee: RICHTEK TECHNOLOGY CORPORATION
    Inventor: Tsung-Yi Huang
  • Patent number: 10226921
    Abstract: A printhead substrate, comprising an electrothermal transducer configured to heat a printing material, a first DMOS transistor configured to drive the electrothermal transducer, a MOS structure forming an anti-fuse element, a second DMOS transistor configured to write information in the anti-fuse element by causing an insulation breakdown of an insulating film of the MOS structure, and a driving unit consisted of at least one MOS transistor and configured to drive the second DMOS transistor.
    Type: Grant
    Filed: January 31, 2017
    Date of Patent: March 12, 2019
    Assignee: CANON KABUSHIKA KAISHA
    Inventor: Masanobu Ohmura
  • Patent number: 10229907
    Abstract: A semiconductor device includes a substrate, first and second body regions, a well region, a source region, a drain region, and first and second doped regions. The first and second body regions are disposed in first and second regions respectively. The well region is disposed in the first and second regions and between the first and second body regions. First and second portions of the source region are disposed in the first and second body regions respectively. The drain region is disposed on the well region. The first doped region is disposed in the well region. The second doped region is disposed on the first doped region. A first portion of the first doped region and a first portion of the second doped region are disposed in the well region of the first region and extend toward the first body region and out of the well region.
    Type: Grant
    Filed: September 8, 2017
    Date of Patent: March 12, 2019
    Assignee: VANGUARD INTERNATIONAL SEMICONDUCTOR CORPORATION
    Inventors: Cheng-Tsung Wu, Shin-Cheng Lin, Wen-Hsin Lin, Yu-Hao Ho
  • Patent number: 10199495
    Abstract: A laterally diffused metal-oxide semiconductor field-effect transistor, comprising a substrate, a first conductivity type well region, a second conductivity type well region, a drain electrode in the first conductivity type well region, a source electrode and a body region in the second conductivity type well region, and a gate electrode arranged across surfaces of the first conductivity type well region and the second conductivity type well region, and also comprising a floating layer ring arranged on the top of the first conductivity type well region and located between the gate electrode and the drain electrode and a plurality of groove polysilicon electrodes running through the floating layer ring and stretching into the first conductivity type well region.
    Type: Grant
    Filed: August 18, 2016
    Date of Patent: February 5, 2019
    Assignee: CSMC TECHNOLOGIES FAB2 CO., LTD.
    Inventors: Shukun Qi, Guipeng Sun
  • Patent number: 10177220
    Abstract: A high voltage MOS device includes: a first drift region with a first conductive type, a body region with a second conductive type, plural second drift regions with the second conductive type, a gate, a source region with the first conductive type, a drain with the first conductive type, and a body contact region with the second conductive type. The plural second drift regions contact the body region along the lateral direction, and are located separately in the width direction. Any neighboring two second drift regions do not contact each other. Each of the second drift regions is separated from the drain by the first drift region.
    Type: Grant
    Filed: July 27, 2017
    Date of Patent: January 8, 2019
    Assignee: RICHTEK TECHNOLOGY CORPORATION
    Inventors: Tsung-Yi Huang, Chu-Feng Chen
  • Patent number: 10147728
    Abstract: A method for fabricating semiconductor device includes the steps of: forming a first trench in a substrate; forming a first shallow trench isolation (STI) in the first trench; forming a first patterned mask on the substrate; and using the first patterned mask to remove part of the first STI for forming a second trench and remove part of the substrate for forming a third trench. Preferably, a bottom surface of the third trench is lower than a bottom surface of the second trench.
    Type: Grant
    Filed: August 15, 2017
    Date of Patent: December 4, 2018
    Assignees: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.
    Inventors: Feng-Yi Chang, Fu-Che Lee
  • Patent number: 10128355
    Abstract: Methods for forming a fin field effect transistor (FinFET) device structure are provided. The method includes providing a first fin structure and a second fin structure extending above a substrate and forming an isolation structure over the substrate, and the an upper portion of the first fin structure and an upper portion of the second fin structure protrudes from the isolation structure. The method also includes forming a first transistor and a second transistor on the first fin structure and the second fin structure, and the first transistor includes a first gate dielectric layer. The method further includes forming an inter-layer dielectric (ILD) structure between the first transistor and the second transistor, and a portion of the first gate dielectric layer above the isolation structure is in direct contact with a sidewall of the ILD structure.
    Type: Grant
    Filed: December 22, 2016
    Date of Patent: November 13, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Che-Cheng Chang, Yung-Jung Chang
  • Patent number: 10121889
    Abstract: A high voltage semiconductor device including a P type substrate, a high voltage N type well, a first P type well, a drift region, and a P type doping layer is provided. The high voltage N type well and the P type doping layer, which is formed in a region located below the first P type well and the drift region, are formed in the P type substrate. The first P type well is formed in the high voltage N type well. A bottom of the first P type well and a bottom of the P type doping layer are separated from a surface of the P type substrate by a first depth and a second depth larger than the first depth, respectively. The drift region is formed in the high voltage N type well and extending down from the surface of the P type substrate.
    Type: Grant
    Filed: August 29, 2014
    Date of Patent: November 6, 2018
    Assignee: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Ching-Lin Chan, Cheng-Chi Lin, Shyi-Yuan Wu
  • Patent number: 10068977
    Abstract: A power MOSFET IC device including an array of MOSFET cells formed in a semiconductor substrate. The array of MOSFET cells comprises an interior region of interior MOSFET cells and an outer edge region of peripheral MOSFET cells, each interior MOSFET cell of the interior region of the array comprising a pair of interior MOSFET devices coupled to each other at a common drain contact. In an example embodiment, each interior MOSFET device includes a source contact (SCT) trench extended into a substrate contact region of the semiconductor substrate. The SCT trench is provided with a length less than a linear portion of a polysilicon gate of the interior MOSFET device, wherein the SCT trench is aligned to the polysilicon gate having a curvilinear layout geometry.
    Type: Grant
    Filed: May 22, 2017
    Date of Patent: September 4, 2018
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Furen Lin, Frank Baiocchi, Haian Lin, Yunlong Liu, Lark Liu, Wei Song, ZiQiang Zhao
  • Patent number: 10062749
    Abstract: Metal-oxide-semiconductor field-effect transistor (MOSFET) devices are described which have a p-type region between the p-type well regions of the device. The p-type region can be either floating or connected to the p-type well regions by additional p-type regions. MOSFET devices are also described which have one or more p-type regions connecting the p-type well regions of the device. The p-type well regions can be arranged in a various geometric arrangements including square, diamond and hexagonal. Methods of making the devices are also described.
    Type: Grant
    Filed: June 12, 2014
    Date of Patent: August 28, 2018
    Assignee: Monolith Semiconductor Inc.
    Inventors: Kiran Chatty, Kevin Matocha, Sujit Banerjee, Larry Burton Rowland
  • Patent number: 10056481
    Abstract: The present disclosure provides a semiconductor device structure including an active region having a semiconductor-on-insulator (SOI) configuration, a semiconductor device of lateral double-diffused MOS (LDMOS) type, a dual ground plane region formed by two well regions which are counter-doped to each other, the dual ground plane region extending below the semiconductor device, and a deep well region extending below the dual ground plane region. Herein, the semiconductor device of LDMOS type comprises a gate structure formed on the active region, a source region and a drain region formed in the active region at opposing sides of the gate structure, and a channel region and a drift region, both of which being formed in the active region and defining a channel drift junction, wherein the channel drift junction is overlain by the gate structure.
    Type: Grant
    Filed: January 13, 2017
    Date of Patent: August 21, 2018
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Christian Schippel, Andrei Sidelnicov, Gerd Zschaetzsch
  • Patent number: 10056480
    Abstract: A high-side device includes: a substrate, an epitaxial layer, a high voltage well, a body region, a gate, a source, a drain, and a buried region. A channel junction is formed between the body region and the high voltage well. The buried region is formed in the substrate and the epitaxial layer, and in a vertical direction, a part of the buried region is located in the substrate and another part of the buried region is located in the epitaxial layer. In the channel direction, an inner side boundary of the buried region is between the drain and the channel junction. An impurity concentration of a second conductive type of the buried region is sufficient to prevent the high voltage well between the channel junction and the drain from being completely depleted when the high-side power device operates in a conductive operation. A corresponding manufacturing method is also disclosed.
    Type: Grant
    Filed: June 24, 2016
    Date of Patent: August 21, 2018
    Assignee: RICHTEK TECHNOLOGY CORPORATION
    Inventor: Tsung-Yi Huang
  • Patent number: 10026806
    Abstract: In an embodiment, a high frequency amplifying circuit includes a semiconductor device. The semiconductor device includes a semiconductor substrate having a bulk resistivity ??100 Ohm·cm, a front surface and a rear surface, an LDMOS (Lateral Diffused Metal Oxide Semiconductor) transistor in the semiconductor substrate, and a RESURF structure comprising a doped buried layer arranged in the semiconductor substrate, spaced at a distance from the front surface and the rear surface, and coupled with at least one of a channel region and a body contact region of the LDMOS transistor.
    Type: Grant
    Filed: March 14, 2017
    Date of Patent: July 17, 2018
    Assignee: Infineon Technologies AG
    Inventors: Albert Birner, Helmut Brech, Matthias Zigldrum, Michaela Braun, Christian Eckl
  • Patent number: 10014406
    Abstract: A semiconductor device and a forming method thereof, the semiconductor device includes a first and a second wells, a source region, a drain region, two gate structures and at least one doping region. The first well with a first conductive type is disposed in a substrate, and the source region is disposed in the first well. The second well with a second conductive type is disposed adjacent to the first well in a substrate, and the drain region is disposed in the second well. Two gate structures are disposed on the substrate between the source region and the drain region. At least one doping region with the first conductive type is disposed in the second well between the two gate structures.
    Type: Grant
    Filed: August 16, 2016
    Date of Patent: July 3, 2018
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Zhi-Cheng Lee, Yu-Hao Huang, Kai-Lin Lee
  • Patent number: 9997358
    Abstract: In a vertical MOSFET of a trench gate structure, a high-concentration implantation region is provided in a p-type base region formed from a p-type silicon carbide layer formed by epitaxial growth, so as to include a portion in which a channel is formed. The high-concentration implantation region is formed by ion implantation of a p-type impurity into the p-type silicon carbide layer. The high-concentration implantation region is formed by p-type ion implantation and has an impurity concentration profile in which concentration differences in a depth direction form a bell-shaped curve at a peak of impurity concentration that is higher than that of the p-type silicon carbide layer. In the p-type base region, disorder occurs partially in the crystal structure consequent to the ion implantation for forming the high-concentration implantation region.
    Type: Grant
    Filed: December 30, 2016
    Date of Patent: June 12, 2018
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Setsuko Wakimoto, Masanobu Iwaya
  • Patent number: 9991375
    Abstract: The invention relates to integrated circuit fabrication, and more particularly to a metal gate electrode. An exemplary structure for a semiconductor device comprises a substrate comprising a major surface; a first rectangular gate electrode on the major surface comprising a first layer of multi-layer material; a first dielectric material adjacent to one side of the first rectangular gate electrode; and a second dielectric material adjacent to the other 3 sides of the first rectangular gate electrode, wherein the first dielectric material and the second dielectric material collectively surround the first rectangular gate electrode.
    Type: Grant
    Filed: May 30, 2012
    Date of Patent: June 5, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jr-Jung Lin, Chih-Han Lin, Jin-Aun Ng, Ming-Ching Chang, Chao-Cheng Chen
  • Patent number: 9991380
    Abstract: A lateral superjunction MOSFET device includes multiple transistor cells connected to a lateral superjunction structure, each transistor cell including a conductive gate finger, a source region finger, a body contact region finger and a drain region finger arranged laterally within each transistor cell. Each of the drain region fingers, the source region fingers and the body contact region fingers is a doped region finger having a termination region at an end of the doped region finger. The lateral superjunction MOSFET device further includes a termination structure formed in the termination region of each doped region finger and including one or more termination columns having the same conductivity type as the doped region finger and positioned near the end of the doped region finger. The one or more termination columns extend through the lateral superjunction structure and are electrically unbiased.
    Type: Grant
    Filed: June 23, 2017
    Date of Patent: June 5, 2018
    Assignee: Alpha and Omega Semiconductor Incorporated
    Inventors: Madhur Bobde, Lingpeng Guan, Karthik Padmanabhan, Hamza Yilmaz
  • Patent number: 9985124
    Abstract: The present invention can reduce an on-resistance while suppressing reduction in a short circuit capacity. The present invention includes a SiC epitaxial layer, a well region, a source region, a channel resistance adjusting region, a gate electrode, an interlayer insulating film, a source electrode, and a drain electrode. The channel resistance adjusting region is sandwiched between the source region and the SiC epitaxial layer in a surface layer of the well region. The channel resistance adjusting region is a region in which a first impurity region is intermittently formed in a direction intersecting a direction in which the source region and the SiC epitaxial layer sandwich the channel resistance adjusting region.
    Type: Grant
    Filed: June 27, 2014
    Date of Patent: May 29, 2018
    Assignee: Mitsubishi Electric Corporation
    Inventors: Yasushi Takaki, Yoichiro Tarui
  • Patent number: 9972681
    Abstract: A semiconductor device including a dummy pillar and a plurality of racetrack pillars. The dummy pillar of semiconductor material extends in a first lateral direction. The plurality of racetrack pillars, including the semiconducting material, surrounds the dummy pillar. Each of the plurality of racetrack pillars has a first linear section, which extends in the first lateral direction, and a first rounded section to form a racetrack shape. The plurality of racetrack pillars includes a first racetrack pillar and a second racetrack pillar. The first racetrack pillar is disposed proximate to the dummy pillar and the second racetrack pillar surrounds the first racetrack pillar. The first racetrack pillar is disposed between the dummy pillar and the second racetrack pillar. The semiconductor device includes a plurality of spacing regions including a first spacing region that surrounds the dummy pillar and is disposed between the first racetrack pillar and the dummy pillar.
    Type: Grant
    Filed: June 8, 2017
    Date of Patent: May 15, 2018
    Assignee: Power Integrations, Inc.
    Inventors: Alexei Ankoudinov, Sorin Georgescu, Vijay Parthasarathy, Kelly Marcum, Jiankang Bu
  • Patent number: 9972619
    Abstract: Disclosed is a semiconductor device arrangement including a first semiconductor device having a load path, and a plurality of second transistors, each having a load path between a first and a second load terminal and a control terminal. The second transistors have their load paths connected in series and connected in series to the load path of the first transistor, each of the second transistors has its control terminal connected to the load terminal of one of the other second transistors, and one of the second transistors has its control terminal connected to one of the load terminals of the first semiconductor device.
    Type: Grant
    Filed: August 29, 2016
    Date of Patent: May 15, 2018
    Assignee: INFINEON TECHNOLOGIES AUSTRIA AG
    Inventors: Rolf Weis, Franz Hirler, Martin Feldtkeller, Gerald Deboy, Matthias Stecher, Armin Willmeroth
  • Patent number: 9954100
    Abstract: A method includes forming a gate spacer along sidewalls of a gate structure, forming a source region and a drain region on opposite sides of the gate structure, wherein a sidewall of the source region is vertically aligned with a first sidewall of the gate spacer, depositing a dielectric layer over the substrate, depositing a conductive layer over the dielectric layer, patterning the dielectric layer and the conductive layer to form a field plate, wherein the dielectric layer comprises a horizontal portion extending from the second drain/source region to a second sidewall of the gate spacer and a vertical portion formed along the second sidewall of the gate spacer, forming a plurality of metal silicide layers by applying a salicide process to the conductive layer, the gate structure, the first drain/source region and the second drain/source region and forming contact plugs over the plurality of metal silicide layers.
    Type: Grant
    Filed: March 24, 2016
    Date of Patent: April 24, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ming-Chyi Liu, Pei-Lun Wang, Yuan-Tai Tseng, Yu-Hsing Chang, Shih-Chang Liu
  • Patent number: 9935628
    Abstract: A transistor switch device is provided that exhibits relatively good voltage capability and relatively easy drive requirements to turn the device on and off. This can reduce transient drive current flows that may perturb other components.
    Type: Grant
    Filed: November 10, 2015
    Date of Patent: April 3, 2018
    Assignee: Analog Devices Global
    Inventor: Edward John Coyne
  • Patent number: 9905563
    Abstract: A semiconductor device includes: a first semiconductor layer stacked body including a compound semiconductor; a first field-effect transistor element including a first drain electrode, a first source electrode, and a first gate electrode that are provided on the first semiconductor layer stacked body; a second semiconductor layer stacked body including a compound semiconductor; and a second field-effect transistor element including a second drain electrode, a second source electrode, and a second gate electrode that are provided on the second semiconductor layer stacked body. The second gate electrode forms a Schottky junction or a p-n junction with the second semiconductor layer stacked body, the second drain electrode is connected to the first drain electrode, the second source electrode is connected to the first gate electrode, and the second gate electrode is connected to the first source electrode.
    Type: Grant
    Filed: December 15, 2016
    Date of Patent: February 27, 2018
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Takahiro Ohori, Chikashi Hayashi, Manabu Yanagihara
  • Patent number: 9893158
    Abstract: A semiconductor device is provided that includes a transistor in a semiconductor body having a main surface. The transistor includes a source region, a drain region, a body region, a drift zone, and a gate electrode at the body region. The body region and the drift zone are disposed along a first direction between the source region and the drain region. The first direction is parallel to the main surface. The semiconductor device further includes a field plate disposed in field plate trenches extending along the first direction in the drift zone, and a field dielectric layer between the field plate and the drift zone. A thickness of the field dielectric layer gradually increases along the first direction from a portion adjacent to the source region to a portion adjacent to the drain region.
    Type: Grant
    Filed: July 22, 2016
    Date of Patent: February 13, 2018
    Assignee: Infineon Technologies AG
    Inventors: Andreas Meiser, Oliver Haeberlen
  • Patent number: 9871135
    Abstract: A semiconductor device is disclosed that includes a first region of a first conductivity type that includes a drain, a region of a second conductivity type abutting the first region in a lateral direction and a vertical direction to form an interface between the first conductivity type and the second conductivity type, wherein the drain region is spaced apart from the interface. A source region of the first conductivity type abuts the second region in the lateral direction and vertical directions. A control gate structure includes a conductive layer that is spaced apart from the drain region by a first dimension in the lateral direction. A shallow trench isolation (STI) region having a second dimension in the lateral direction is disposed at a location of the first region between the source and drain regions, wherein the second dimension is less than one-half of the first dimension.
    Type: Grant
    Filed: June 2, 2016
    Date of Patent: January 16, 2018
    Assignee: NXP USA, Inc.
    Inventors: Xin Lin, Hongning Yang, Ronghua Zhu, Jiang-Kai Zuo