Abstract: A semiconductor device includes a first n-type semiconductor layer, a p-type semiconductor layer, a second n-type semiconductor layer and a trench. The first n-type semiconductor layer includes a first interface and a second interface. The second interface forms an upper surface of a convex protruded from the first interface. The p-type semiconductor layer is stacked on the first n-type semiconductor layer and includes a first region stacked on the first interface and a second region stacked on the second interface. The first region is uniformly continuous with the second region. The second n-type semiconductor layer is stacked on the p-type semiconductor layer. The trench is depressed from the second n-type semiconductor layer through the p-type semiconductor layer into the convex of the first n-type semiconductor layer.

Abstract: A Schottky barrier diode includes: an n? type epitaxial layer disposed on a first surface of an n+ type silicon carbide substrate; a first p+ region disposed on the n? type epitaxial layer; an n type epitaxial layer disposed on the n? type epitaxial layer and the first p+ region; a second p+ region disposed on the n type epitaxial layer, and being in contact with the first p+ region; a Schottky electrode disposed on the n type epitaxial layer and the second p+ region; and an ohmic electrode disposed on a second surface of the n+ type silicon carbide substrate. Also, the first p+ region has a lattice shape including a plurality of vertical portions and horizontal portions connecting both ends of the respective vertical portions to each other.

Abstract: A charge-compensation semiconductor device includes a semiconductor body including a first surface, a second surface arranged opposite to the first surface, an edge delimiting the semiconductor body in a horizontal direction substantially parallel to the first surface, a drain region of a of a first conductivity type extending to the second surface, an active area, and a peripheral area arranged between the active area and the edge, a source metallization arranged on the first surface, and a drain metallization arranged on the drain region and in Ohmic contact with the drain region.

Abstract: A semiconductor device is provided. The semiconductor device includes a substrate of a first conductivity type and an epitaxial structure of the first conductivity type disposed on the substrate. The semiconductor device further includes a well region having a first doping concentration of a second conductivity type disposed in the epitaxial structure and the substrate. The semiconductor device further includes a drain region and a source region respectively formed in the epitaxial structure inside and outside of the well region. The semiconductor device further includes a body region of the first conductivity type disposed under the source region, and a pair of first and second doped regions disposed in the well region between the drain region and the source region. The first and second doped regions extend outside of the well region and toward the body region.

Abstract: A semiconductor device includes a metal-oxide-semiconductor field effect transistor (MOSFET), in which parasitic silicon controlled rectifier (SCR) equivalent circuits are formed in the MOSFET, and the MOSFET further includes a drain region. The drain region includes P-type heavily doped regions which are different from each other, in which the P-type heavily doped regions are respectively operated as anodes of the SCR equivalent circuits.

Abstract: In one general aspect, a power semiconductor device can include a semiconductor substrate of a first conductivity type, and a semiconductor layer of a second conductivity type disposed on the semiconductor substrate. The semiconductor layer can include a high voltage unit, a low voltage unit disposed around the high voltage unit, and a level shift unit disposed between the high voltage unit and the low voltage unit. The power semiconductor device can include a first isolation region of the first conductivity type disposed between the high voltage unit and the level shift unit, and a second isolation region of the first conductivity type disposed between the low voltage unit and the level shift unit where the first isolation region and the second isolation region each are vertically aligned in the semiconductor layer and each extends to at least the semiconductor substrate.

Abstract: A p anode layer is formed on one main surface of an n? drift layer. N+ cathode layer having an impurity concentration more than that of the n? drift layer is formed on the other main surface. An anode electrode is formed on the surface of the p anode layer. A cathode electrode is formed on the surface of the n+ cathode layer. N-type broad buffer region having a net doping concentration more than the bulk impurity concentration of a wafer and less than the n+ cathode layer and p anode layer is formed in the n? drift layer. Resistivity ?0 of the n? drift layer satisfies 0.12V0??0?0.25V0 with respect to rated voltage V0. Total amount of net doping concentration of the broad buffer region is equal to or more than 4.8×1011 atoms/cm2 and equal to or less than 1.0×1012 atoms/cm2.

Abstract: A semiconductor device having a first layer adjoining a semiconductor layer, and further comprising at least one field modification structure positioned such that, in use, a potential at the field modification structure causes an E-field vector at a region of an interface between the semiconductor and the first layer to be modified.

Abstract: The invention discloses a high-voltage LDMOS integrated device, which is interdigitally structured in a plan view and which including: a first area corresponding to a source fingertip area, wherein a first sectional structure of the first area particularly includes: a first drain; and a first longitudinal voltage-withstanding buffer layer located below the first drain and consisted of a first deep N-well and a first low-voltage N-well, wherein the first low-voltage N-well is located in the first deep-N well, and the first deep-N well is located in a P-type substrate; and a second area non-overlapping with the first area, wherein a second sectional structure of the second area particularly includes: a second drain; and a second longitudinal voltage-withstanding buffer layer located below the second drain and consisted of a second deep N-well and a second low-voltage N-well.

Abstract: Disclosed are a field effect transistor (FET) (e.g., a lateral double-diffused metal oxide semiconductor field effect transistor (LDMOSFET)) and a method of forming the FET. In the FET, an etch stop pad is on a semiconductor substrate (e.g., a P-type silicon substrate). A semiconductor layer (e.g., a silicon layer) is also on the substrate and extends laterally over the etch stop pad. A first well region (e.g., an N-well region) extends through the semiconductor layer into the substrate such that it contains the etch stop pad. A second well region (e.g., a P-well region) is in the first well region aligned above the etch stop pad. A source region (e.g., a N-type source region) is in the second well region. A buried isolation region (e.g., a buried air-gap isolation region) is within the first well region aligned below the etch stop pad so as to limit vertical capacitor formation.

Abstract: A high voltage metal-oxide-semiconductor laterally diffused device (HV LDMOS), particularly an insulated gate bipolar junction transistor (IGBT), and a method of making it are provided in this disclosure. The device includes a semiconductor substrate, a gate structure formed on the substrate, a source and a drain formed in the substrate on either side of the gate structure, a first doped well formed in the substrate, and a second doped well formed in the first well. The gate, source, second doped well, a portion of the first well, and a portion of the drain structure are surrounded by a deep trench isolation feature and an implanted oxygen layer in the silicon substrate.

Abstract: The present disclosure provides a semiconductor device. The semiconductor device includes a first doped region and a second doped region both formed in a substrate. The first and second doped regions are oppositely doped. The semiconductor device includes a first gate formed over the substrate. The first gate overlies a portion of the first doped region and a portion of the second doped region. The semiconductor device includes a second gate formed over the substrate. The second gate overlies a different portion of the second doped region. The semiconductor device includes a first voltage source that provides a first voltage to the second gate. The semiconductor device includes a second voltage source that provides a second voltage to the second doped region. The first and second voltages are different from each other.

Abstract: A termination structure for a semiconductor device includes a semiconductor substrate having an active region and a termination region. Two or more trench cells are located in the termination region and extend from a boundary of the active region toward an edge of the semiconductor substrate. A termination trench is formed in the termination region on a side of the trench cells remote from the active region. A conductive spacer is located adjacent to a sidewall of the termination trench nearest the trench cells. A first oxide layer is formed in the termination trench and contacts a sidewall of the conductive spacer. A first conductive layer is formed on a backside surface of the semiconductor substrate. A second conductive layer is formed atop the active region and the termination region.

Abstract: Semiconductor devices, such as LDMOS devices, are described that include a plurality of trench regions formed in an extended drain region of the devices. In one or more implementations, the semiconductor devices include a substrate having an extended drain region, a source region, and a drain region, all of the first conductivity type, formed proximate to a surface of the substrate. A gate is positioned over the surface and between the source region and the drain region. The gate is configured to receive a voltage so that a conduction region may be formed at least partially below the gate to allow charge carriers (e.g., majority carriers) to travel between the source region and the drain region. A plurality of trench regions are formed within the extended drain region that are configured to increase resistivity within the extended drain region when charge carriers travel between the source region and the drain region.

Abstract: A semiconductor device includes a drift layer having a first conductivity type, a well region in the drift layer having a second conductivity type opposite the first conductivity type, and a source region in the well region, The source region has the first conductivity type and defines a channel region in the well region. The source region includes a lateral source region adjacent the channel region and a plurality of source contact regions extending away from the lateral source region opposite the channel region. A body contact region having the second conductivity type is between at least two of the plurality of source contact regions and is in contact with the well region. A source ohmic contact overlaps at least one of the source contact regions and the body contact region. A minimum dimension of a source contact area of the semiconductor device is defined by an area of overlap between the source ohmic contact and the at least one source contact region.

Abstract: An Electro-Static Discharge (ESD) protection using at least one I/O pad with at least one mesh structure of diodes provided on a semiconductor body is disclosed. The mesh structure has a plurality of cells. At least one cell can have a first type of implant surrounded by at least one cell with a second type of implant in at least one side of the cell, and at least cell can have a second type of implant surrounded by at least one cell with a first type of implant in at least one side of the cell. The two types of implant regions can be separated with a gap. A silicide block layer (SBL) can cover the gap and overlap into the both implant regions to construct P/N junctions on the polysilicon or active-region body on an insulated substrate. Alternatively, the two types of implant regions can be isolated by LOCOS, STI, dummy gate, or SBL on silicon substrate. The regions with the first and the second type of implants can be coupled to serve as the first and second terminal of a diode, respectively.

Abstract: A super junction semiconductor device includes strip structures between mesa regions that protrude from a base section in a cell area. Each strip structure includes a compensation structure with a first and a second section inversely provided on opposing sides of a fill structure. Each section includes a first compensation layer of a first conductivity type and a second compensation layer of a complementary second conductivity type. The strip structures extend into an edge area surrounding the cell area. In the edge area the strip structures include end sections. The end sections may be modified to enhance break down voltage characteristics, avalanche ruggedness and commutation behavior.

Abstract: An embodiment of a diode includes a semiconductor substrate, a first contact region having a first conductivity type, a second contact region laterally spaced from the first contact region, and having a second conductivity type, an intermediate region disposed in the semiconductor substrate between the first and second contact regions, electrically connected with the first contact region, and having the first conductivity type, and a buried region disposed in the semiconductor substrate, having the second conductivity type, and electrically connected with the second contact region. The buried region extends laterally across the first contact region and the intermediate region to establish first and second junctions, respectively. The first junction has a lower breakdown voltage than the second junction.

Abstract: A parallel p-n layer (20) is provided as a drift layer between an active portion and an n+ drain region (11). The parallel p-n layer (20) is formed by an n-type region (1) and a p-type region (2) being repeatedly alternately joined. An n-type high concentration region (21) is provided on a first main surface side of the n-type region (1). The n-type high concentration region (21) has an impurity concentration higher than that of an n-type low concentration region (22) provided on a second main surface side of the n-type region (1). The n-type high concentration region (21) has an impurity concentration 1.2 times or more, 3 times or less, preferably 1.5 times or more, 2.5 times or less, greater than that of the n-type low concentration region (22). Also, the n-type high concentration region (21) has one-third or less, preferably one-eighth or more, one-fourth or less, of the thickness of a region of the n-type region (1) adjacent to the p-type region (2).

Abstract: A semiconductor device includes an epitaxial layer of semiconductor material of a first conductivity type, a body region of a second (opposite) conductivity type extending into the epitaxial layer from a main surface of the epitaxial layer, a source region of the first conductivity type disposed in the body region, and a channel region extending laterally in the body region from the source region along the main surface. A charge compensation region of the second conductivity type can be provided under the body region which extends in a direction parallel to the main surface and terminates prior to a pn-junction between the source and body regions at the main surface, and/or an additional region of the first conductivity type which has at least one peak doping concentration each of which occurs deeper in the epitaxial layer from the main surface than a peak doping concentration of the device channel region.

Abstract: The present invention provides a semiconductor device that ensures both the breakdown voltage characteristic and specific on-resistance characteristic required for a high-voltage semiconductor device and that includes a gate over a substrate, a source region formed at one side of the gate, a drain region formed at the other side of the gate, and a plurality of device isolation films formed between the source region and the drain region, below the gate.

Abstract: A semiconductor device includes a semiconductor substrate of a first conductivity type, a first region of a second conductivity type formed in the semiconductor substrate, a second region of the first conductivity type formed in the first region, a source region of the second conductivity type formed in the second region, a drain region of the second conductivity type formed in the first region, a first junction part including a part of a border between the first region and the second region, which is on the side of the drain region, a second junction part including a part of the border between the first region and the second region, which is at a location different from the first junction part, a gate electrode formed above the first junction, and a conductor pattern formed above the second junction part and being electrically independent from the gate electrode.

Abstract: A super junction semiconductor device includes a semiconductor portion with a first surface and a second surface parallel to the first surface. The semiconductor portion includes a doped layer of a first conductivity type formed at least in a cell area. The super junction semiconductor device further includes columnar first super junction regions of a second, opposite conductivity type extending in a direction perpendicular to the first surface and separated by columnar second super junction regions of the first conductivity type. The first and second super junction regions form a super junction structure between the first surface and the doped layer. A distance between the first super junction regions and the second surface does not exceed 30 ?m.

Abstract: A power semiconductor device according to an embodiment includes an element portion in which MOSFET elements are provided and a termination portion provided around the element portion, and has pillar layers provided respectively in parallel to each other in a semiconductor substrate. The device includes a first trench and a first insulation film. The first trench is provided between end portions of the pillar layers, in the semiconductor substrate at the termination portion exposed from a source electrode of the MOSFET elements. The first insulation film is provided on a side surface and a bottom surface of the first trench.

Abstract: The invention provides a semiconductor device, including: a substrate having a first conductivity type, including: a body region having the first conductivity type; a source region formed in the body region; a drift region having a second conductivity type adjacent to the body region, wherein the first conductivity type is opposite to the second conductivity type; and a drain region formed in the drift region; a multiple reduced surface field (RESURF) structure embedded in the drift region of the substrate; and a gate dielectric layer having a thick portion formed over the substrate, wherein the gate dielectric includes at least a stepped-shape or a curved shape curved-shape formed thereon, and wherein the multiple RESURF structure is aligned with the thick portion of the gate dielectric layer.

Abstract: An aspect of the present embodiment, there is provided a semiconductor device includes a high-voltage element, the high-voltage element including a substrate, a first semiconductor region with a first conductive type on the substrate, an insulating isolation film on the substrate, a second semiconductor region with a second conductive type, the second semiconductor region being provided between the first semiconductor region and the insulating isolation film, a drain region with the second conductive type provided on a surface of the second semiconductor region, an impurity concentration of the drain region being higher than an impurity concentration of the second semiconductor region, a source region with the second conductive type provided on a surface of the first semiconductor, the source region being separated from the drain region, a floating drain region with the second conductive type provided on the surface of the first semiconductor region between the second semiconductor region and the source regio

Abstract: In a semiconductor substrate with a first surface and a working surface parallel to the first surface, columnar first and second super junction regions of a first and a second conductivity type are formed. The first and second super junction regions extend in a direction perpendicular to the first surface and form a super junction structure. The semiconductor portion is thinned such that, after the thinning, a distance between the first super junction regions having the second conductivity type and a second surface obtained from the working surface does not exceed 30 ?m. Impurities are implanted into the second surface to form one or more implanted zones. The embodiments combine super junction approaches with backside implants enabled by thin wafer technology.

Abstract: A lateral diffused semiconductor device is disclosed, including: a substrate; a first isolation and a second isolation comprising at least portions disposed in the substrate to define an active area; a first drift region and a second drift region disposed in the active area, wherein the first drift region is disposed in the second drift region; a gate structure on the substrate; a source region in the first drift region; a drain region in the second drift region; and a ring-shaped field plate on the substrate, wherein the ring-shaped field plate surrounds at least one of the source and the drain region.

Abstract: An extended-drain transistor is formed in a semiconductor layer arranged on one side of an insulating layer with a semiconductor region being arranged on the other side of the insulating layer. The semiconductor region includes a first portion of a first conductivity type arranged in front of the source and at least one larger portion of the gate and a second portion of a second conductivity type arranged in front of at least the larger portion of the extended drain region, each of the first and second portions being coupled to a connection pad.

Abstract: A semiconductor device according an aspect of the present disclosure may include an isolation layer formed within a substrate and formed to define an active region, a junction formed in the active region, well regions formed under the isolation layer, and a plug embedded within the substrate between the junction and the well regions and formed extend to a greater depth than the well regions.

Abstract: The present invention discloses a high voltage device and a manufacturing method thereof. The high voltage device is formed in a first conductive type substrate, wherein the substrate includes isolation regions defining a device region. The high voltage device includes: a drift region, located in the device region, doped with second conductive type impurities; a gate in the device region and on the surface of the substrate; and a second conductive type source and drain in the device region, at different sides of the gate respectively. From top view, the concentration of the second conductive type impurities of the drift region is distributed substantially periodically along horizontal and vertical directions.

Abstract: A semiconductor device includes a semiconductor substrate of a first conductivity type, a drift layer of the first conductivity type which is formed on a first main surface of the semiconductor substrate, a second well region of a second conductivity type which is formed to surround a cell region of the drift layer, and a source pad for electrically connecting the second well regions and a source region of the cell region through a first well contact hole provided to penetrate a gate insulating film on the second well region, a second well contact hole provided to penetrate a field insulating film on the second well region and a source contact hole.

Abstract: A transistor includes a semiconductor body; a body region of a first conductivity type formed in the semiconductor body; a gate electrode formed partially overlapping the body region and insulated from the semiconductor body by a gate dielectric layer; a source diffusion region of a second conductivity type formed in the body region on a first side of the gate electrode; a trench formed in the semiconductor body on a second side, opposite the first side, of the gate electrode, the trench being lined with a sidewall dielectric layer; and a doped sidewall region of the second conductivity type formed in the semiconductor body along the sidewall of the trench where the doped sidewall region forms a vertical drain current path for the transistor.

Abstract: An MOSFET includes a silicon carbide substrate, an active layer, a gate oxide film, and a gate electrode. The active layer includes a body region where an inversion layer is formed at a region in contact with the gate oxide film by application of voltage to the gate electrode. The body region includes a low concentration region arranged at a region where an inversion layer is formed, and containing impurities of low concentration, and a high concentration region adjacent to the low concentration region in the carrier mobile direction in the inversion layer, arranged in a region where the inversion layer is formed, and containing impurities higher in concentration than in the low concentration region.

Abstract: A problem associated with n-channel power MOSFETs and the like that the following is caused even by relatively slight fluctuation in various process parameters is solved: source-drain breakdown voltage is reduced by breakdown at an end of a p-type body region in proximity to a portion in the vicinity of an annular intermediate region between an active cell region and a chip peripheral portion, arising from electric field concentration in that area. To solve this problem, the following measure is taken in a power semiconductor device having a superjunction structure in the respective drift regions of a first conductivity type of an active cell region, a chip peripheral region, and an intermediate region located therebetween: the width of at least one of column regions of a second conductivity type comprising the superjunction structure in the intermediate region is made larger than the width of the other regions.

Abstract: A lateral drain metal oxide semiconductor (LDMOS) device includes a well region having a second conductive type in a substrate, a body region having a first conductive type in the well region, a drift region having the second conductive type in the well region and spaced apart from the body region, a source region having the second conductive type in the body region, a drain region having the second conductive type in the drift region, a gate structure on the well region between the source region and the drain region, a shallow trench isolation (STI) structure in the drift region between the drain region and the source region, and a buried layer having the first conductive type in the well region under the drift region, a center of the buried layer being aligned with a center of the STI structure.

Abstract: A downsized semiconductor device having an excellent reverse characteristic, and a method of manufacturing the semiconductor device is sought to improve. The semiconductor device comprises a semiconductor body having a polygonal contour. An active area is formed in the semiconductor body. An EQR electrode is formed so as to surround the active area and to have curved portions of the EQR electrode along the corners of the semiconductor body. An interlayer insulating film is formed to cover the active area and the EQR electrode. The EQR electrode is embedded in the interlayer insulating film around the active area. EQR contacts are in contact with the curved portions of the EQR electrode and the semiconductor body outside the curved portions, and have at least side walls covered with the interlayer insulating film.

Abstract: A method of fabricating an LDMOS device includes: forming a gate of the LDMOS device on a semiconductor substrate; performing tilt body implantation by implanting dopants of a first conductivity type in the semiconductor substrate using a mask, wherein the tilt body implantation is implanted at an angle from a vertical direction; performing zero tilt body implantation by implanting dopants of the first conductivity type using the same mask, wherein the zero tilt body implantation is implanted with zero tilt from the vertical direction, and wherein the tilt body implantation and the zero tilt body implantation are configured to form a body region of the LDMOS device; and forming a source region and a drain contact region of the LDMOS device, wherein the source region and the drain contact region are of a second conductivity type.

Abstract: A semiconductor device has an FET of a trench-gate structure obtained by disposing a conductive layer, which will be a gate, in a trench extended in the main surface of a semiconductor substrate, wherein the upper surface of the trench-gate conductive layer is formed equal to or higher than the main surface of the semiconductor substrate. The conductive layer of the trench gate is formed to have a substantially flat or concave upper surface and the upper surface is formed equal to or higher than the main surface of the semiconductor substrate. After etching of the semiconductor substrate to form the upper surface of the conductive layer of the trench gate, a channel region and a source region are formed by ion implantation so that the semiconductor device is free from occurrence of a source offset.

Abstract: There is provided a super junction semiconductor device and a method of manufacturing the same. A super junction semiconductor device includes an n-type semiconductor region disposed in a substrate, two or more p-type semiconductor regions disposed adjacent to the n-type semiconductor region alternately in a direction parallel to a surface of the substrate, a p-type body region disposed on at least one of the p-type semiconductor regions, and a source region disposed in the p-type body region, and an n-type ion implantation region is formed along a lower end of the n-type semiconductor region and lower ends of the p-type semiconductor regions.

Abstract: There is provided a super junction semiconductor device. The super junction semiconductor device includes a cell area and a junction termination area disposed on a substrate, and a transition area disposed between the cell area and the junction termination area, and the cell area, the junction termination area, and the transition area each include one or more unit cells comprising a N-type pillar region and a P-type pillar region among a plurality of N-type pillar regions and a P-type pillar regions that are alternated between the cell area and the junction termination area.

Abstract: Lateral power devices where immobile electrostatic charge is emplaced in dielectric material adjoining the drift region. A shield gate is interposed between the gate electrode and the drain, to reduce the Miller charge. In some embodiments the gate electrode is a trench gate, and in such cases the shield electrode too is preferably vertically extended.

Abstract: A high-voltage MOS transistor has a semiconductor substrate formed with a first well of a first conductivity type in which a drain region and a drift region are formed and a second well of a second, opposite conductivity type in which a source region and a channel region are formed, a gate electrode extends over the substrate from the second well to the first well via a gate insulation film, wherein there is formed a buried insulation film in the drift region underneath the gate insulation film at a drain edge of the gate electrode, there being formed an offset region in the semiconductor substrate between the channel region and the buried insulation film, wherein the resistance of the offset region is reduced in a surface part thereof by being introduced with an impurity element of the first conductivity type with a concentration exceeding the first well.

Abstract: An aspect of the present embodiment, there is provided a semiconductor device includes a high-voltage element, the high-voltage element including a substrate, a first semiconductor region with a first conductive type on the substrate, an insulating isolation film on the substrate, a second semiconductor region with a second conductive type, the second semiconductor region being provided between the first semiconductor region and the insulating isolation film, a drain region with the second conductive type provided on a surface of the second semiconductor region, an impurity concentration of the drain region being higher than an impurity concentration of the second semiconductor region, a source region with the second conductive type provided on a surface of the first semiconductor, the source region being separated from the drain region, a floating drain region with the second conductive type provided on the surface of the first semiconductor region between the second semiconductor region and the source regio

Abstract: A trenched power semiconductor device with enhanced breakdown voltage is provided. The trenched power semiconductor device has a first trench penetrating the body region located between two neighboring gate trenches. A polysilicon structure with a conductivity type identical to that of the body region is located in a lower portion of the first trench and spaced from the body region with a predetermined distance. A dielectric structure is located on the polysilicon structure and at least extended to the body region. Source regions are located in an upper portion of the body region. A heavily doped region located in the body region is extended to the bottom of the body region. A conductive structure is electrically connected to the heavily doped region and the source region.

Abstract: A super junction semiconductor device includes a semiconductor portion with a first surface and a parallel second surface. A doped layer of a first conductivity type is formed at least in a cell area. Columnar first super junction regions of a second, opposite conductivity type extend in a direction perpendicular to the first surface. Columnar second super junction regions of the first conductivity type separate the first super junction regions from each other. The first and second super junction regions form a super junction structure between the first surface and the doped layer. A distance between the first super junction regions and the second surface does not exceed 30 ?m. The on-state or forward resistance of low-voltage devices rated for reverse breakdown voltages below 1000 V can be defined by the resistance of the super junction structure.

Abstract: Source zones of a first conductivity type and body zones of a second conductivity type are formed in a semiconductor die. The source zones directly adjoin a first surface of the semiconductor die. A dielectric layer adjoins the first surface. Polysilicon plugs extend through the dielectric layer and are electrically connected to the source and the body zones. An impurity source containing at least one metallic recombination element is provided in contact with deposited polycrystalline silicon material forming the polysilicon plugs and distant to the semiconductor die. Atoms of the metallic recombination element, for example platinum atoms, may be diffused out from the impurity source into the semiconductor die to reliably reduce the reverse recovery charge.

Abstract: A semiconductor device includes a semiconductor substrate of a first conductivity type, a buried layer a second conductivity type different from the first conductivity type on the substrate and an epitaxial layer of the second conductivity type on the buried layer. The device further includes a pocket well of the first conductivity type in the epitaxial layer, a first drift region in the epitaxial layer at least partially overlapping the pocket well, a second drift region in the epitaxial layer and spaced apart from the first drift region, and a body region of the first conductivity type in the pocket well. A gate electrode is disposed on the body region, the pocket well and the first drift region and has an edge overlying the epitaxial region between the first and second drift regions.

Abstract: The high-voltage transistor device comprises a semiconductor substrate (1) with a source region (2) of a first type of electrical conductivity, a body region (3) including a channel region (4) of a second type of electrical conductivity opposite to the first type of conductivity, a drift region (5) of the first type of conductivity, and a drain region (6) of the first type of conductivity extending longitudinally in striplike fashion from the channel region (4) to the drain region (6) and laterally confined by isolation regions (9). The drift region (5) comprises a doping of the first type of conductivity and includes an additional region (8) with a net doping of the second type of conductivity to adjust the electrical properties of the drift region (5). The drift region depth and the additional region depth do not exceed the maximal depth (17) of the isolation regions (9).

Abstract: A power semiconductor element having a lightly doped drift and buffer layer is disclosed. One embodiment has, underneath and between deep well regions of a first conductivity type, a lightly doped drift and buffer layer of a second conductivity type. The drift and buffer layer has a minimum vertical extension between a drain contact layer on the adjacent surface of a semiconductor substrate and the bottom of the deepest well region which is at least equal to a minimum lateral distance between the deep well regions. The vertical extension can also be determined such that a total amount of dopant per unit area in the drift and buffer layer is larger than a breakdown charge amount at breakdown voltage.