With Means (other Than Self-alignment Of The Gate Electrode) To Decrease Gate Capacitance (e.g., Shield Electrode) Patents (Class 257/340)
  • Patent number: 10396166
    Abstract: A semiconductor device capable of high-voltage operation includes a semiconductor substrate having a first conductivity type. A first well doped region is formed in a portion of the semiconductor substrate. The first well doped region has a second conductivity type. A first doped region is formed on the first well doped region, having the second conductivity type. A second doped region is formed on the first well doped region and is separated from the first doped region, having the second conductivity type. A first gate structure is formed over the first well doped region and is adjacent to the first doped region. A second gate structure is formed beside the first gate structure and is close to the second doped region. A third gate structure is formed overlapping a portion of the first gate structure and a first portion of the second gate structure.
    Type: Grant
    Filed: February 6, 2017
    Date of Patent: August 27, 2019
    Assignee: MediaTek Inc.
    Inventors: Cheng Hua Lin, Yan-Liang Ji
  • Patent number: 10003014
    Abstract: A method of forming a memory device that in one embodiment may include forming a magnetic tunnel junction on a first electrode using an electrically conductive mask and subtractive etch method. Following formation of the magnetic tunnel junction, at least one dielectric layer is deposited to encapsulate the magnetic tunnel junction. Ion beam etching/Ion beam milling may then remove the portion of the at least one dielectric layer that is present on the electrically conductive mask, wherein a remaining portion of the at least one dielectric layer is present over the first electrode. A second electrode may then be formed in contact with the electrically conductive mask.
    Type: Grant
    Filed: June 20, 2014
    Date of Patent: June 19, 2018
    Assignees: INTERNATIONAL BUSINESS MACHINES CORPORATION, CROCUS TECHNOLOGY
    Inventors: Michael C. Gaidis, Erwan Gapihan, Rohit Kilaru, Eugene J. O'Sullivan
  • Patent number: 9941378
    Abstract: Methods for forming a transistor include forming a gate conductor in contact with a gate stack. The gate conductor has a top surface that meets a middle point of sidewalls of a sacrificial region of a fin. The sacrificial region of the fin is trimmed to create gaps above the gate stack. A top spacer is formed on the gate conductor. The top spacer includes airgaps above the gate stack.
    Type: Grant
    Filed: June 15, 2017
    Date of Patent: April 10, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Veeraraghavan S. Basker, Kangguo Cheng, Theodorus E. Standaert, Junli Wang
  • Patent number: 9871134
    Abstract: A semiconductor device and the method of manufacturing the same are provided. The semiconductor device includes a substrate, a source region, a drain region, a filed plate and a gate electrode. The source region is of a first conductivity type located at a first side within the substrate. The drain region is of the first conductive type located at a second side within the substrate opposite to the first side. The field plate is located over the substrate and between the source region and the drain region. A portion of the gate electrode is located over the field plate.
    Type: Grant
    Filed: December 21, 2015
    Date of Patent: January 16, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Yogendra Yadav, Chi-Chih Chen, Ruey-Hsin Liu, Chih-Wen Yao
  • Patent number: 9825138
    Abstract: A method of fabricating a FET includes forming a gate on the surface of a substrate. A trench contact extends between a first region located proximate the surface of the substrate and a second region located below the first region is formed in the surface. The surface of the substrate is coated with a conductive material, wherein the conductive material at least partially covers the gate and lines the trench contact to electrically connect the first region and the second region. A void remains in the trench contact. A dielectric material is applied to the conductive material, wherein the dielectric material at least partially fills the void in the trench contact. At least a portion of the conductive material is etched from the gate.
    Type: Grant
    Filed: June 21, 2016
    Date of Patent: November 21, 2017
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Hong Yang, Zachary K. Lee, Yufei Xiong, Yunlong Liu, Wei Tang
  • Patent number: 9666671
    Abstract: A device includes a semiconductor substrate, a body region in the semiconductor substrate having a first conductivity type and in which a channel is formed during operation, source and drain regions in the semiconductor substrate and having a second conductivity type, the source region being disposed on the body region, and a composite drift region in the semiconductor substrate, having the second conductivity type, and through which charge carriers from the source region drift to reach the drain region after passing through the channel. The composite drift region includes a first section adjacent the channel, a second section adjacent the drain region, and a third section disposed between the first and second sections. The first and second sections have a lower effective dopant concentration level than the third section.
    Type: Grant
    Filed: May 16, 2014
    Date of Patent: May 30, 2017
    Assignee: NXP USA, Inc.
    Inventors: Zhihong Zhang, Hongning Yang, Jiang-Kai Zuo
  • Patent number: 9614072
    Abstract: A semiconductor device includes a first semiconductor region of a first conductivity type, a first electrode, a second electrode, a third electrode, a first insulation region, a second insulation region, a second semiconductor region of a second conductivity type, a third semiconductor region of the first conductivity type, a fourth semiconductor region of the second conductivity type, and a fourth electrode. The second electrode includes first portions and a second portion. The second portion extends in a first direction. The first portions extend in a direction away from the second portion. The second portion is between the first portions and the first electrode in a second direction. The fourth semiconductor region is positioned between adjacent first electrode portions in the first direction.
    Type: Grant
    Filed: August 5, 2015
    Date of Patent: April 4, 2017
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Yusuke Kawaguchi
  • Patent number: 9614078
    Abstract: A semiconductor device and a method for manufacturing the same are provided. A semiconductor device includes a semiconductor substrate and a gate structure formed on the semiconductor substrate. A source region and a drain region are disposed on opposite sides of the gate structure on the semiconductor substrate. A lightly-doped drain region is adjacent to a side of the drain region close to the gate structure, and a lightly-doped source region is adjacent to a side of the source region close to the gate structure. An oxidation region is disposed in the lightly-doped drain region. A trench extends from the surface of the semiconductor substrate to the drain region. A source electrode is disposed on the source region, and the drain electrode has a first portion disposed on the drain region and a second portion disposed in the trench.
    Type: Grant
    Filed: October 22, 2015
    Date of Patent: April 4, 2017
    Assignee: VANGUARD INTERNATIONAL SEMICONDUCTOR CORPORATION
    Inventors: Chih-Hung Lin, Chia-Hao Lee, Chih-Cherng Liao
  • Patent number: 9595546
    Abstract: An organic light emitting display is provided. The organic light emitting display comprises a multi-type thin-film transistor (TFT) and an organic light emitting diode. The multi-type TFT has a low-temperature-poly-silicon (LTPS) TFT and an oxide semiconductor TFT (oxide TFT) disposed on the LTPS TFT. The organic light emitting diode is electrically connected to the multi-type TFT. The LTPS TFT and the oxide TFT are connected to the same gate line.
    Type: Grant
    Filed: February 25, 2015
    Date of Patent: March 14, 2017
    Assignee: LG DISPLAY CO., LTD.
    Inventors: TaeHwan Kim, Namwook Cho, Hyoung-Su Kim, Jaemyon Lee
  • Patent number: 9536960
    Abstract: A semiconductor device includes a gate electrode adjacent to a body region in a semiconductor substrate. The semiconductor device further includes a field electrode in a field plate trench in the main surface, the field plate trench having an extension length in a first direction parallel to a main surface. The extension length is less than the double of an extension length in a second direction that is perpendicular to the first direction parallel to the main surface. The extension length in the first direction is more than half of the extension length in the second direction. The field electrode is insulated from an adjacent drift zone by means of a field dielectric layer. A field plate material of the field electrode has a resistivity in a range from 105 to 10?1 Ohm·cm.
    Type: Grant
    Filed: June 24, 2015
    Date of Patent: January 3, 2017
    Assignee: Infineon Technologies Austria AG
    Inventors: David Laforet, Franz Hirler, Oliver Blank, Ralf Siemieniec
  • Patent number: 9472579
    Abstract: An array substrate having a wiring of a pad region formed without an insulating film or without an insulating film and an organic film to reduce abnormal operations due to an increase in resistance caused by a contact margin at a high temperature, and a method for manufacturing the same are provided. The array substrate includes: an insulating substrate including a pad region and a thin film transistor (TFT) formation region; a first electrode layer formed in the pad region of the substrate; and a second electrode formed on the first electrode layer in an overlapping manner.
    Type: Grant
    Filed: October 9, 2014
    Date of Patent: October 18, 2016
    Assignee: LG Display Co., Ltd.
    Inventors: JongWoo Kim, ChangHo Oh, WonHyung Yoo, SangYoon Paik, JunKi Kang, JongHoon Kim
  • Patent number: 9455205
    Abstract: A method for processing a semiconductor device in accordance with various embodiments may include: providing a semiconductor device having a first pad and a second pad electrically disconnected from the first pad; applying at least one electrical test potential to at least one of the first pad and the second pad; and electrically connecting the first pad and the second pad to one another after applying the at least one electrical test potential.
    Type: Grant
    Filed: October 17, 2013
    Date of Patent: September 27, 2016
    Assignee: INFINEON TECHNOLOGIES AG
    Inventors: Markus Zundel, Franz Hirler, Peter Nelle, Ludger Borucki, Markus Winkler, Erwin Vogl
  • Patent number: 9429616
    Abstract: A test method in accordance with one or more embodiments may include: providing a semiconductor device to be tested, the semiconductor device including at least one device cell, the at least one device cell having at least one trench, at least one first terminal electrode region and at least one second terminal electrode region, at least one gate electrode, and at least one additional electrode disposed at least partially in the at least one trench, wherein an electrical potential of the at least one additional electrode may be controlled separately from electrical potentials of the at least one first terminal electrode region, the at least one second terminal electrode region and the at least one gate electrode; and applying at least one electrical test potential to at least the at least one additional electrode to detect defects in the at least one device cell.
    Type: Grant
    Filed: June 30, 2015
    Date of Patent: August 30, 2016
    Assignee: INFINEON TECHNOLOGIES AG
    Inventors: Markus Zundel, Franz Hirler, Peter Nelle
  • Patent number: 9425305
    Abstract: A split gate field effect transistor device. The device includes a split gate structure having a trench, a gate electrode and a source electrode. A first poly layer is disposed within the trench and is connected to the gate electrode. A second poly layer connected to the source electrode, wherein the first poly layer and the second poly layer are independent.
    Type: Grant
    Filed: August 26, 2010
    Date of Patent: August 23, 2016
    Assignee: Vishay-Siliconix
    Inventors: Kyle Terrill, Yang Gao, Chanho Park
  • Patent number: 9224853
    Abstract: In one embodiment, an apparatus can include a trench extending into a semiconductor region of a first conductivity type, an electrode disposed in the trench, and a source region of the first conductivity type abutting a sidewall of the trench. The apparatus can include a first well region of a second conductivity type disposed in the semiconductor region below the source region and abutting the sidewall of the trench lateral to the electrode where the second conductivity type is opposite the first conductivity type. The apparatus can also include a second well region of the second conductivity type disposed in the semiconductor region and abutting the sidewall of the trench, and a third well region of the first conductivity type disposed between the first well region and the second well region.
    Type: Grant
    Filed: July 19, 2012
    Date of Patent: December 29, 2015
    Assignee: Fairchild Semiconductor Corporation
    Inventor: James Pan
  • Patent number: 9178057
    Abstract: A lateral double diffused metal-oxide-semiconductor device includes: a semiconductor substrate; an epitaxial semiconductor layer disposed over the semiconductor substrate; a gate structure disposed over the epitaxial semiconductor layer; a first doped region disposed in the epitaxial semiconductor layer at a first side of the gate structure; a second doped region disposed in the epitaxial semiconductor layer at a second side of the gate structure; a third doped region disposed in the first doped region; a fourth doped region disposed in the second doped region; a trench formed in the third doped region, the first doped region and the epitaxial semiconductor layer under the first doped region; a conductive contact formed in the trench; and a fifth doped region disposed in the epitaxial semiconductor layer under the trench.
    Type: Grant
    Filed: November 21, 2013
    Date of Patent: November 3, 2015
    Assignee: VANGUARD INTERNATIONAL SEMICONDUCTOR CORPORATION
    Inventors: Tsung-Hsiung Lee, Jui-Chun Chang
  • Patent number: 9099419
    Abstract: A test method in accordance with one or more embodiments may include: providing a semiconductor device to be tested, the semiconductor device including at least one device cell, the at least one device cell having at least one trench, at least one first terminal electrode region and at least one second terminal electrode region, at least one gate electrode, and at least one additional electrode disposed at least partially in the at least one trench, wherein an electrical potential of the at least one additional electrode may be controlled separately from electrical potentials of the at least one first terminal electrode region, the at least one second terminal electrode region and the at least one gate electrode; and applying at least one electrical test potential to at least the at least one additional electrode to detect defects in the at least one device cell.
    Type: Grant
    Filed: October 9, 2012
    Date of Patent: August 4, 2015
    Assignee: INFINEON TECHNOLOGIES AG
    Inventors: Markus Zundel, Franz Hirler, Peter Nelle
  • Patent number: 9041101
    Abstract: A power semiconductor device according to an embodiment includes an element portion in which MOSFET elements are provided and a termination portion provided around the element portion, and has pillar layers provided respectively in parallel to each other in a semiconductor substrate. The device includes a first trench and a first insulation film. The first trench is provided between end portions of the pillar layers, in the semiconductor substrate at the termination portion exposed from a source electrode of the MOSFET elements. The first insulation film is provided on a side surface and a bottom surface of the first trench.
    Type: Grant
    Filed: March 10, 2014
    Date of Patent: May 26, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Syotaro Ono, Masaru Izumisawa, Hiroshi Ohta, Hiroaki Yamashita
  • Patent number: 9029870
    Abstract: A semiconductor device of the present invention includes a semiconductor layer composed of SiC, a metal layer directly bonded to one face of the semiconductor layer, and a high carbon concentration layer formed on a surface layer portion at one side of the semiconductor layer and containing more highly concentrated carbon than a surface layer portion of the other side. Further, a manufacturing method of a semiconductor device of the present invention includes the steps of forming, on a surface layer portion at one face side of a semiconductor layer composed of SiC, a high carbon concentration layer containing more highly concentrated carbon than a surface layer portion at the other face side by heat treatment and directly bonding metal to the high carbon concentration layer.
    Type: Grant
    Filed: June 19, 2013
    Date of Patent: May 12, 2015
    Assignee: Rohm Co., Ltd.
    Inventor: Yuki Nakano
  • Patent number: 9024382
    Abstract: According to one embodiment, the semiconductor device includes a drift region, a first semiconductor region, a second semiconductor region, a main electrode, first gate electrodes and a second gate electrode. The first gate electrodes and the second gate electrode between a pair of first gate electrodes are provided in the drift region. The first semiconductor region is provided between the first gate electrodes and the second gate electrode. The first semiconductor region has a first side surface opposite to the one of the adjacent ones and a second side surface partially opposite to the second gate electrode. The second semiconductor region is selectively provided on the first semiconductor region. The main electrode has a portion directly adjacent to part of the second side surface and the second semiconductor region.
    Type: Grant
    Filed: February 24, 2011
    Date of Patent: May 5, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Mitsuhiko Kitagawa
  • Patent number: 8987820
    Abstract: A LDMOS device includes a substrate having opposite first and second surfaces; a well region in a portion of the substrate; a gate structure over a portion of the substrate; a first doped region disposed in a portion of the well region from a first side; a second doped region disposed in the well region from a second side; a third doped region disposed in the first doped region; a fourth doped region disposed in the second doped region; a first trench in the third doped region, the first doped region, the well region, and the substrate adjacent to the first surface; a conductive contact in the first trench; a second trench in the substrate adjacent to the second surface; a first conductive layer in second trench; and a second conductive layer over the second surface of the substrate and the first conductive layer.
    Type: Grant
    Filed: October 11, 2013
    Date of Patent: March 24, 2015
    Assignee: Vanguard International Semiconductor Corporation
    Inventors: Tsung-Hsiung Lee, Jui-Chun Chang
  • Patent number: 8987817
    Abstract: A semiconductor device of the present invention includes: a semiconductor substrate of a first conductive type; an epitaxial layer of the first conductive type formed on the semiconductor substrate and having a protrusion formed on a surface thereof; a well region of a second conductive type formed on the surface of the epitaxial layer at each side of the protrusion; a source region of the first conductive type selectively formed in a surface of the well region; a gate insulating film formed so as to cover at least the protrusion and the surface of the well region; and a gate electrode formed on a part of the gate insulating film corresponding to the protrusion. The gate insulating film is thicker in a region thereof corresponding to an upper surface of the protrusion than the other regions thereof.
    Type: Grant
    Filed: August 3, 2011
    Date of Patent: March 24, 2015
    Assignee: Mitsubishi Electric Corporation
    Inventor: Yoichiro Tarui
  • Patent number: 8963240
    Abstract: This invention discloses a semiconductor power device that includes a plurality of power transistor cells surrounded by a trench opened in a semiconductor substrate. At least one of the cells constituting an active cell has a source region disposed next to a trenched gate electrically connecting to a gate pad and surrounding the cell. The trenched gate further has a bottom-shielding electrode filled with a gate material disposed below and insulated from the trenched gate. At least one of the cells constituting a source-contacting cell surrounded by the trench with a portion functioning as a source connecting trench is filled with the gate material for electrically connecting between the bottom-shielding electrode and a source metal disposed directly on top of the source connecting trench.
    Type: Grant
    Filed: April 26, 2013
    Date of Patent: February 24, 2015
    Assignee: Alpha and Omega Semiconductor Incorporated
    Inventors: Anup Bhalla, Sik K. Lui
  • Patent number: 8928078
    Abstract: The present invention discloses a double diffused metal oxide semiconductor (DMOS) device and a manufacturing method thereof. The DMOS device includes: a first conductive type substrate, a second conductive type high voltage well, a gate, a first conductive type body region, a second conductive type source, a second conductive type drain, a first conductive type body electrode, and a first conductive type floating region. The floating region is formed in the body region, which is electrically floating and is electrically isolated from the source and the gate, such that the electrostatic discharge (ESD) effect is mitigated.
    Type: Grant
    Filed: December 25, 2012
    Date of Patent: January 6, 2015
    Assignee: Richtek Technology Corporation, R.O.C.
    Inventors: Tzu-Cheng Kao, Jian-Hsing Lee, Jin-Lian Su, Huan-Ping Chu, Hung-Der Su
  • Publication number: 20150001621
    Abstract: A semiconductor device including a gate insulating film; a gate electrode; a source region of a first conductivity; a drain region of the first conductivity type; a drift region of the first conductivity type formed between the channel region and the drain region; a first semiconductor region of a second conductivity type that encloses the source region, the drift region and the drain region, and includes the channel region; and a first shield wiring that encloses a portion of the source region in a plan view in conjunction with the gate electrode, the portion being not covered by the gate electrode, and is connected to the first semiconductor region, or that covers the portion and is connected to the first semiconductor region and the source region.
    Type: Application
    Filed: May 30, 2014
    Publication date: January 1, 2015
    Applicant: FUJITSU SEMICONDUCTOR LIMITED
    Inventor: Kazuhiko Takada
  • Patent number: 8889511
    Abstract: In one general aspect, a method can include forming a shield dielectric layer in a trench in a semiconductor substrate, forming a shield electrode on at least a portion of the shield dielectric layer, and etching the shield dielectric layer so that a portion of the shield dielectric layer is recessed in the trench. The method can include forming a gate dielectric layer on the recessed portion of the shield dielectric layer in the trench, forming a first conductive gate electrode on a first side of the shield electrode and insulated from a first sidewall of the trench by the gate dielectric layer, and forming a second conductive gate electrode on a second side of the shield electrode and insulated from a second sidewall of the trench by the gate dielectric layer.
    Type: Grant
    Filed: August 26, 2011
    Date of Patent: November 18, 2014
    Assignee: Fairchild Semiconductor Corporation
    Inventors: Joseph A. Yedinak, Nathan L. Kraft
  • Patent number: 8866222
    Abstract: A semiconductor device includes a semiconductor body and a source metallization arranged on a first surface of the body. The body includes: a first semiconductor layer including a compensation-structure; a second semiconductor layer adjoining the first layer, comprised of semiconductor material of a first conductivity type and having a doping charge per horizontal area lower than a breakdown charge per area of the semiconductor material; a third semiconductor layer of the first conductivity type adjoining the second layer and comprising at least one of a self-charging charge trap, a floating field plate and a semiconductor region of a second conductivity type forming a pn-junction with the third layer; and a fourth semiconductor layer of the first conductivity type adjoining the third layer and having a maximum doping concentration higher than that of the third layer. The first semiconductor layer is arranged between the first surface and the second semiconductor layer.
    Type: Grant
    Filed: February 28, 2013
    Date of Patent: October 21, 2014
    Assignee: Infineon Technologies Austria AG
    Inventors: Hans Weber, Stefan Gamerith, Franz Hirler
  • Patent number: 8853780
    Abstract: A device includes a semiconductor substrate, source and drain regions in the semiconductor substrate, a channel region in the semiconductor substrate between the source and drain regions through which charge carriers flow during operation from the source region to the drain region, and a drift region in the semiconductor substrate, on which the drain region is disposed, and through which the charge carriers drift under an electric field arising from application of a bias voltage between the source and drain regions. A PN junction along the drift region includes a first section at the drain region and a second section not at the drain region. The drift region has a lateral profile that varies such that the first section of the PN junction is shallower than the second section of the PN junction.
    Type: Grant
    Filed: May 7, 2012
    Date of Patent: October 7, 2014
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Hongning Yang, Daniel J. Blomberg, Xu Cheng, Xin Lin, Won Gi Min, Zhihong Zhang, Jiang-Kai Zuo
  • Patent number: 8853778
    Abstract: A multi-path transistor includes an active region including a channel region and an impurity region. A gate is dielectrically separated from the channel region. A signal line is dielectrically separated from the impurity region. A conductive shield is disposed between, and dielectrically separated from, the signal line and the channel region. In some multi-path transistors, the channel region includes an extension-channel region under the conductive shield and the multi-path transistor includes different conduction paths, at least one of the different conduction paths being in the extension-channel region to conduct substantially independent of a voltage on the signal line. In other multi-path transistors, the conductive shield is operably coupled to the impurity region and the multi-path transistor includes different conduction paths, at least one of the different conduction paths being under the conductive shield to conduct substantially independent of a voltage on the signal line.
    Type: Grant
    Filed: August 27, 2012
    Date of Patent: October 7, 2014
    Assignee: Micron Technology, Inc.
    Inventor: Toru Tanzawa
  • Patent number: 8841724
    Abstract: In an LDMOS transistor, a channel length is reduced to increase a saturation current without causing an off-state breakdown voltage optimized in terms of trade-off between an on-resistance and the off-state breakdown voltage. A short channel region is selectively formed between an element isolation film and a low-concentration body region in which a channel is formed such that the short channel region is located immediately below a gate oxide film. The short channel region has a conduction type opposite to that of the low-concentration body region and has a carrier concentration higher than that of the low-concentration body region. The body region is retreated by the presence of the short channel region toward a high-concentration source region.
    Type: Grant
    Filed: December 29, 2010
    Date of Patent: September 23, 2014
    Assignee: Hitachi, Ltd.
    Inventors: Kenji Miyakoshi, Shinichiro Wada, Yohei Yanagida, Takayuki Oshima, Keigo Kitazawa
  • Patent number: 8836028
    Abstract: In a general aspect, a power device can include at least one N-type epitaxial layer disposed on a substrate and a plurality of N-pillars and P-pillars that define alternating P-N-pillars in the at least one N-type epitaxial layer. The power device can also include an active region and a termination region, where the termination region surrounds the active region. The alternating P-N-pillars can be disposed in both the active region and the termination region, where the termination region can include a predetermined number of floating P-pillars.
    Type: Grant
    Filed: April 27, 2011
    Date of Patent: September 16, 2014
    Assignee: Fairchild Semiconductor Corporation
    Inventors: Joseph A. Yedinak, Mark L. Rinehimer, Praveen Muraleedharan Shenoy, Jaegil Lee, Dwayne S. Reichl, Harold Heidenreich
  • Patent number: 8829614
    Abstract: This invention discloses a method for manufacturing a semiconductor power device in a semiconductor substrate comprises an active cell area and a termination area.
    Type: Grant
    Filed: August 31, 2009
    Date of Patent: September 9, 2014
    Assignee: Alpha and Omega Semiconductor Incorporated
    Inventors: Lingpeng Guan, Anup Bhalla, Madhur Bobde, Tinggang Zhu
  • Patent number: 8822291
    Abstract: A method of forming a device is disclosed. A substrate having a device region is provided. The device region comprises a source region, a gate and a drain region defined thereon. A drift well is formed in the substrate adjacent to a second side of the gate. The drift well underlaps a portion of the gate with a first edge of the drift well beneath the gate. A secondary portion is formed in the drift well. The secondary portion underlaps a portion of the gate with a first edge of the secondary portion beneath the gate. The first edge of the secondary portion is offset from the first edge of the drift well. A gate dielectric of the gate comprises a first portion having a first thickness and a second portion having a second thickness. The second portion is over the secondary portion.
    Type: Grant
    Filed: August 29, 2012
    Date of Patent: September 2, 2014
    Assignee: Globalfoundries Singapore Pte. Ltd.
    Inventors: Guowei Zhang, Purakh Raj Verma
  • Patent number: 8823096
    Abstract: A device includes a semiconductor region in a semiconductor chip, a gate dielectric layer over the semiconductor region, and a gate electrode over the gate dielectric. A drain region is disposed at a top surface of the semiconductor region and adjacent to the gate electrode. A gate spacer is on a sidewall of the gate electrode. A dielectric layer is disposed over the gate electrode and the gate spacer. A conductive field plate is over the dielectric layer, wherein the conductive field plate has a portion on a drain side of the gate electrode. A deep metal via is disposed in the semiconductor region. A source electrode is underlying the semiconductor region, wherein the source electrode is electrically shorted to the conductive field plate through the deep metal via.
    Type: Grant
    Filed: June 1, 2012
    Date of Patent: September 2, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Po-Chih Su, Hsueh-Liang Chou, Ruey-Hsin Liu, Chun-Wai Ng
  • Publication number: 20140239392
    Abstract: A technique for improving characteristics of a semiconductor device (DMOSFET) is provided. A semiconductor device is configured so as to include: an n-type source layer (102) disposed on an upper portion of a first surface side of an SiC substrate (106); a p body layer (103) which surrounds the source layer and has a channel region; an n?-type drift layer (107) which is in contact with the p body layer (103); a gate electrode (116) which is disposed on an upper portion of the channel region via a gate insulating film; and a first p+ layer (109) which is disposed in the p body layer (103), extends to a portion below the n+ source layer (102), and serves as a buried semiconductor region having an impurity concentration higher than that of the p body layer (103). In this manner, since the first p+ layer (109) is formed in the middle of the p body layer (103), it is possible to reduce the diffusion resistance of the p body layer (103). Thus, it is possible to make a parasitic bipolar transistor harder to turn on.
    Type: Application
    Filed: June 7, 2012
    Publication date: August 28, 2014
    Inventors: Daisuke Matsumoto, Naoki Tega, Yasuhiro Shimamoto
  • Patent number: 8816433
    Abstract: In one embodiment, a transistor fabricated on a semiconductor die includes a first section of transistor segments disposed in a first area of the semiconductor die, and a second section of transistor segments disposed in a second area of the semiconductor die adjacent the first area. Each of the transistor segments in the first and second sections includes a pillar of a semiconductor material that extends in a vertical direction. First and second dielectric regions are disposed on opposite sides of the pillar. First and second field plates are respectively disposed in the first and second dielectric regions. Outer field plates of transistor segments adjoining first and second sections are either separated or partially merged.
    Type: Grant
    Filed: March 28, 2013
    Date of Patent: August 26, 2014
    Assignee: Power Integrations, Inc.
    Inventors: Vijay Parthasarathy, Sujit Banerjee, Martin H. Manley
  • Patent number: 8816431
    Abstract: A MOSFET device has a funnel-shaped trench etched in a semiconductor substrate. The funnel-shaped trench has flared rim extending from a wider cross section trench mouth at the surface of the semiconductor substrate to a narrower cross section trench body portion which terminates in an epilayer portion of the semiconductor substrate. A gate electrode is disposed in the trench on the flared rim. Source and gate regions of the device abut upper and lower portions of the flared rim, respectively. A drain region of the device, which abuts the narrower cross section trench body portion, is self-aligned with a lower edge of a gate electrode.
    Type: Grant
    Filed: March 9, 2012
    Date of Patent: August 26, 2014
    Assignee: Fairchild Semiconductor Corporation
    Inventor: Brian Bowers
  • Patent number: 8803225
    Abstract: A tunneling field effect transistor and a method for fabricating the same are provided. The tunneling field effect transistor includes: a semiconductor substrate and a drain layer formed in the semiconductor substrate, in which the drain layer is first type heavily doped; an epitaxial layer formed on the drain layer, with an isolation region formed in the epitaxial layer; a buried layer formed in the epitaxial layer, in which the buried layer is second type lightly doped; a source formed in the buried layer, in which the source is second type heavily doped; a gate dielectric layer formed on the epitaxial layer, and a gate formed on the gate dielectric layer; and a source metal contact layer formed on the source, and a drain metal contact layer formed under the drain layer.
    Type: Grant
    Filed: September 6, 2012
    Date of Patent: August 12, 2014
    Assignee: Tsinghua University
    Inventors: Ning Cui, Renrong Liang, Jing Wang, Jun Xu
  • Patent number: 8803236
    Abstract: An LDMOS device includes: a semiconductor layer formed over a semiconductor substrate; a gate structure disposed over the semiconductor layer; a first doped region disposed in the semiconductor layer adjacent to a first side of the gate structure; a second doped region disposed in the semiconductor layer adjacent to a second side of the gate structure; a third doped region disposed in the first doped region; a fourth doped region disposed in the second doped region; a trench formed in the third doped region, the first doped region and the semiconductor layer under in the first doped region; an insulating layer covering the third doped region, the gate structure, and the fourth doped region; a conductive layer conformably formed over a bottom surface and sidewalls of the trench; a dielectric layer disposed in the trench; and a diffused region disposed in the semiconductor layer under the trench.
    Type: Grant
    Filed: May 30, 2013
    Date of Patent: August 12, 2014
    Assignee: Vanguard International Semiconductor Corporation
    Inventors: Tsung-Hsiung Lee, Jui-Chun Chang
  • Patent number: 8796088
    Abstract: A semiconductor device and a method of fabricating the semiconductor device is provided. In the method, a semiconductor substrate defining a device region and an outer region at a periphery of the device region is provided, an align trench is formed in the outer region, a dummy trench is formed in the device region, an epi layer is formed over a top surface of the semiconductor substrate and within the dummy trench, a current path changing part is formed over the epi layer, and a gate electrode is formed over the current path changing part. When the epi layer is formed, a current path changing trench corresponding to the dummy trench is formed over the epi layer, and the current path changing part is formed within the current path changing trench.
    Type: Grant
    Filed: July 10, 2012
    Date of Patent: August 5, 2014
    Assignee: Dongbu HiTek Co., Ltd.
    Inventor: Chul Jin Yoon
  • Patent number: 8791525
    Abstract: A power semiconductor device that includes a stack of a thin metal layer and a thick metal layer over the active region thereof, and a method for the fabrication thereof.
    Type: Grant
    Filed: February 25, 2008
    Date of Patent: July 29, 2014
    Assignee: International Rectifier Corporation
    Inventors: Robert Montgomery, Hugo Burke, Philip Parsonage, Susan Johns, David Paul Jones
  • Publication number: 20140197487
    Abstract: An electronic semiconductor device comprising: a semiconductor body, having a first side and a second side opposite to one another and including a first structural region facing the second side, and a second structural region extending over the first structural region and facing the first side; a body region extending in the second structural region at the first side; a source region extending inside the body region; an LDD region facing the first side of the semiconductor body; and a gate electrode. The device comprises: a trench dielectric region extending through the second structural region a first trench conductive region immediately adjacent to the trench dielectric region; and a second trench conductive region in electrical contact with the body region and with the source region. An electrical contact at the second side of the semiconductor body is in electrical contact with the drain region via the first structural region.
    Type: Application
    Filed: January 9, 2014
    Publication date: July 17, 2014
    Applicant: STMicroelectronics S.r.l.
    Inventors: Salvatore Cascino, Leonardo Gervasi, Antonello Santangelo
  • Patent number: 8759914
    Abstract: The invention provides integrated circuit designs that use of an M2 interconnect layer in place of local interconnect conductors for programming in OD area to enable efficient use of OD area for routing the M1 signals in the stack devices. The use of M2 in place of local interconnect conductors for programming also enables the introduction of shields between adjacent M2 programming lines to reduce the capacitive coupling impact. This improves the transistor density and circuit performance significantly. Although the invention is applicable to integrated circuit design in general, it is particularly well suited to 20 nm static random accessory memory (SRAM) chips to produce transistor density circuit performance advantages over prior 20 nm and 28 nm SRAM chip layouts.
    Type: Grant
    Filed: February 8, 2013
    Date of Patent: June 24, 2014
    Assignee: LSI Corporation
    Inventors: Anil Singh Rawat, Sumaant Kumar Thapliyal, Deepak Doddamani, Deepa V
  • Patent number: 8742495
    Abstract: In one embodiment, a vertical HVFET includes a pillar of semiconductor material a pillar of semiconductor material arranged in a loop layout having at least two substantially parallel and substantially linear fillet sections each having a first width, and at least two rounded sections, the rounded sections having a second width narrower than the first width, a source region of a first conductivity type being disposed at or near a top surface of the pillar, and a body region of a second conductivity type being disposed in the pillar beneath the source region. First and second dielectric regions are respectively disposed on opposite sides of the pillar, the first dielectric region being laterally surrounded by the pillar, and the second dielectric region laterally surrounding the pillar. First and second field plates are respectively disposed in the first and second dielectric regions.
    Type: Grant
    Filed: March 11, 2013
    Date of Patent: June 3, 2014
    Assignee: Power Integrations, Inc.
    Inventors: Vijay Parthasarathy, Sujit Banerjee, Lin Zhu
  • Patent number: 8716811
    Abstract: A semiconductor device includes a first conduction-type semiconductor substrate, a first semiconductor region of a first conduction-type formed on the semiconductor substrate, a second semiconductor region of a second conduction-type formed on a surface of the first semiconductor region, a third semiconductor region of the second conduction-type formed to be separated from the second semiconductor region on the surface of the first semiconductor region, a fourth semiconductor region of the second conduction-type formed to be separated from the second semiconductor region and the third semiconductor region on the surface of the first semiconductor region, and a first electrode connected to the second semiconductor region and the third semiconductor region.
    Type: Grant
    Filed: March 2, 2012
    Date of Patent: May 6, 2014
    Assignee: Sony Corporation
    Inventors: Hideki Mori, Chihiro Arai
  • Patent number: 8716701
    Abstract: Embodiments of the invention are directed to an improved device for sensing infrared (IR) radiation with upconversion to provide an output of electromagnetic radiation having a shorter wavelength than the incident IR radiation, such as visible light. The device comprises an anode, a hole blocking layer to separate an IR sensing layer from the anode, an organic light emitting layer that is separated from the anode by the IR sensing layer, and a cathode. The hole blocking layer assures that when a potential is applied between the anode and the cathode the organic light emitting layer generates electromagnetic radiation only when the IR sensing layer is irradiated with IR radiation.
    Type: Grant
    Filed: May 24, 2011
    Date of Patent: May 6, 2014
    Assignees: Nanoholdings, LLC, University of Florida Research Foundation, Inc.
    Inventors: Franky So, Do Young Kim, Dong Woo Song, Galileo Sarasqueta, Bhabendra K. Pradhan
  • Patent number: 8716789
    Abstract: A power semiconductor device according to an embodiment includes an element portion in which MOSFET elements are provided and a termination portion provided around the element portion, and has pillar layers provided respectively in parallel to each other in a semiconductor substrate. The device includes a first trench and a first insulation film. The first trench is provided between end portions of the pillar layers, in the semiconductor substrate at the termination portion exposed from a source electrode of the MOSFET elements. The first insulation film is provided on a side surface and a bottom surface of the first trench.
    Type: Grant
    Filed: September 11, 2012
    Date of Patent: May 6, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Syotaro Ono, Masaru Izumisawa, Hiroshi Ohta, Hiroaki Yamashita
  • Patent number: 8697539
    Abstract: An integrated circuit device includes a gate region extending above a semiconductor substrate and extending in a first longitudinal direction. A first fin has a first sidewall that extends in a second longitudinal direction above the semiconductor substrate such that the first fin intersects the gate region. A second fin has a second sidewall extending in the second direction above the semiconductor substrate such that the second fin intersects the gate region. A shallow trench isolation (STI) region is formed in the semiconductor substrate between the first and second sidewalls of the first and second fins. A conductive layer disposed over the first insulating layer and over top surfaces of the first and second fins. A first insulating layer is disposed between an upper surface of the STI region and a lower surface of the conductive layer to separate the STI region from the conductive layer.
    Type: Grant
    Filed: December 19, 2012
    Date of Patent: April 15, 2014
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chih-Hsiang Huang, Chia-Pin Lin
  • Patent number: 8680615
    Abstract: A customized shield plate field effect transistor (FET) includes a semiconductor layer, a gate dielectric, a gate electrode, and at least one customized shield plate. The shield plate includes a conductive layer overlying a portion of the gate electrode, one of the gate electrode sidewalls, and a portion of the substrate adjacent to the sidewall. The shield plate defines a customized shield plate edge at its lateral boundary. A distance between the customized shield plate edge and the sidewall of the gate electrode varies along a length of the sidewall. The customized shield plate edge may form triangular, curved, and other shaped shield plate elements. The configuration of the customized shield plate edge may reduce the area of the resulting capacitor and thereby achieve lower parasitic capacitance associated with the FET. The FET may be implemented as a lateral diffused MOS (LDMOS) transistor suitable for high power radio frequency applications.
    Type: Grant
    Filed: December 13, 2011
    Date of Patent: March 25, 2014
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Agni Mitra, David C. Burdeaux
  • Patent number: 8664717
    Abstract: This application is directed to a semiconductor device with an oversized local contact as a Faraday shield, and methods of making such a semiconductor device. One illustrative device disclosed herein includes a transistor comprising a gate electrode and a source region, a source region conductor that is conductively coupled to the source region, a Faraday shield positioned above the source region conductor and the gate electrode and a first portion of a first primary metallization layer for an integrated circuit device positioned above and electrically coupled to the Faraday shield.
    Type: Grant
    Filed: January 9, 2012
    Date of Patent: March 4, 2014
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Yanxiang Liu, Young Way Teh, Vara Vakada