With Means To Reduce On Resistance Patents (Class 257/342)
  • Patent number: 10418450
    Abstract: A fin-shaped field effect transistor (finFET) device comprising includes a substrate, an insulating layer displaced over the substrate, and a fin. The device also includes a gate formed over the fin, the gate including: a gate stack; and a high-k dielectric on opposing side of the gate stack. The device further includes metallic source and drain regions formed over the fin and on opposing sides of the gate.
    Type: Grant
    Filed: April 22, 2016
    Date of Patent: September 17, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Emre Alptekin, Robert R. Robison, Reinaldo A Vega
  • Patent number: 10388783
    Abstract: Apparatus and associate methods relate to a high-voltage MOSFET bounded by two trenches, each having dielectric sidewalls and a dielectric bottom isolating a top field plate and a bottom field plate. The top field plate is electrically connected to a biasing circuit net, and the bottom field plate is biased via a capacitive coupling to the top field plate. The upper field plate and lower field plate are configured to deplete the majority carriers in a drain region of the MOSFET bounded by the two trenches so as to equalize two local maxima of an electric field induced by a drain/body bias, the two local maxima located proximate a drain/body metallurgical junction and proximate a trench bottom. The two local maxima of the electric field are equalized by controlling a depth location of an intervening dielectric between the upper field plate and the lower field plate.
    Type: Grant
    Filed: February 17, 2016
    Date of Patent: August 20, 2019
    Assignee: Polar Semiconductor, LLC
    Inventor: Don Rankila
  • Patent number: 10269897
    Abstract: A power metal-oxide-semiconductor field-effect transistor (MOSFET) device includes a first metal layer, a substrate, an epitaxy layer, a plurality of first trench wells, a plurality of second trench wells, a plurality of body structure layers, a plurality of polysilicon layers, and a second metal layer. A part of a depletion region is formed between each first trench well and the epitaxy layer and between a body structure layer corresponding to the each first trench well and the epitaxy layer, and a rest part of the depletion region is formed between a second trench well corresponding to the each first trench well and the epitaxy layer. The plurality of second trench wells increase a breakdown voltage of the power MOSFET device and reduce a conduction resistor of the power MOSFET device.
    Type: Grant
    Filed: January 11, 2018
    Date of Patent: April 23, 2019
    Assignee: Leadtrend Technology Corp.
    Inventors: Chih-Wen Hsiung, Jen-Hao Yeh, Yi-Rong Tu, Wan-Wen Tseng
  • Patent number: 10211284
    Abstract: A silicon carbide film has first and second main surfaces. The second main surface has an element formation surface and a termination surface. The silicon carbide film has a first range that constitutes a first main surface and an intermediate surface opposite to the first main surface, and a second range that is provided on the intermediate surface and constitutes the element formation surface. The first range includes: a first breakdown voltage holding layer, and a guard ring region partially provided at the intermediate surface in the termination portion. The second range has a second breakdown voltage holding layer. The second range has one of a structure only having the second breakdown voltage holding layer in the termination portion and a structure disposed only in the element portion of the element portion and the termination portion.
    Type: Grant
    Filed: November 27, 2013
    Date of Patent: February 19, 2019
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Takeyoshi Masuda, Keiji Wada
  • Patent number: 10068927
    Abstract: A semiconductor device includes a MEMS device, a first transistor that supplies a first voltage to a first electrode of the MEMS device, a second transistor that supplies a second voltage to the first electrode of the MEMS device, a third transistor that supplies a first video signal to a gate of the first transistor, a fourth transistor that supplies the first voltage to a second electrode of the MEMS device, a fifth transistor that supplies the second voltage to the second electrode of the MEMS device, and a sixth transistor that supplies a second video signal to a gate of the fourth transistor. A gate of the second transistor is connected to the gate of the fourth transistor. A gate of the fifth transistor is connected to the gate of the first transistor.
    Type: Grant
    Filed: October 19, 2015
    Date of Patent: September 4, 2018
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Atsushi Umezaki
  • Patent number: 10038059
    Abstract: An improvement is achieved in the performance of a semiconductor device. The semiconductor device includes a coupling transistor made of a p-channel MOSFET and formed in an n?-type semiconductor region over a base made of a p-type semiconductor. The coupling transistor has a resurf layer as a p-type semiconductor region and couples a lower-voltage circuit region to a higher-voltage circuit region to which a power supply potential higher than the power supply potential supplied to the lower-voltage circuit region is supplied. The semiconductor device has a p-type semiconductor region formed in the portion of the n?-type semiconductor region which surrounds the coupling transistor in plan view.
    Type: Grant
    Filed: July 7, 2016
    Date of Patent: July 31, 2018
    Assignee: Renesas Electronics Corporation
    Inventors: Yoshinori Kaya, Yasushi Nakahara
  • Patent number: 10008562
    Abstract: A first parallel pn layer in which first n-type regions and first p-type regions are disposed in a plan view layout of stripes in an element active portion. A second parallel pn layer has a plan view layout of stripes oriented in the same direction as that of the stripes of the first parallel pn layer in a breakdown voltage structure portion. Corner portions of the first parallel pn layer has a plan view shape where stepped regions formed by shortening the length of the first n-type and p-type regions in steps are disposed in a stepwise arrangement. The stepped regions continue with a second parallel pn layer via an intermediate region lower in average impurity concentration than the first parallel pn layer.
    Type: Grant
    Filed: January 15, 2018
    Date of Patent: June 26, 2018
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Yasushi Niimura, Toshiaki Sakata, Shunji Takenoiri
  • Patent number: 9876004
    Abstract: A semiconductor component including a short-circuit structure. One embodiment provides a semiconductor component having a semiconductor body composed of doped semiconductor material. The semiconductor body includes a first zone of a first conduction type and a second zone of a second conduction type, complementary to the first conduction type, the second zone adjoining the first zone. The first zone and the second zone are coupled to an electrically highly conductive layer. A connection zone of the second conduction type is arranged between the second zone and the electrically highly conductive layer.
    Type: Grant
    Filed: February 5, 2016
    Date of Patent: January 23, 2018
    Assignee: Infineon Technologies AG
    Inventors: Hans-Joachim Schulze, Franz-Josef Niedernostheide, Uwe Kellner-Werdehausen, Reiner Barthelmess
  • Patent number: 9812338
    Abstract: Embodiments of a multi-layer environmental barrier for a semiconductor device and methods of manufacturing the same are disclosed. In one embodiment, a semiconductor device is formed on a semiconductor die. The semiconductor die includes a semiconductor body and a passivation structure on the semiconductor body. A multi-level environmental barrier is provided on the passivation structure. The multi-layer environmental barrier is a low-defect multi-layer dielectric film that hermetically seals the semiconductor device from the environment. In one embodiment, the multi-layer environmental barrier has a defect density of less than 10 defects per square centimeter (cm2). By having a low defect density, the multi-layer environmental barrier serves as a robust barrier to the environment.
    Type: Grant
    Filed: March 14, 2013
    Date of Patent: November 7, 2017
    Assignee: Cree, Inc.
    Inventors: Zoltan Ring, Helmut Hagleitner, Daniel Namishia
  • Patent number: 9767732
    Abstract: A display device includes dummy pixels adjacent to active pixels, and a controller to control pixel driving circuits in the active pixels and dummy driving circuits in the dummy pixels. The dummy driving circuit includes a pumping capacitor, and first and second transistors to connect an initialization voltage terminal to a dummy anode terminal. The first transistor includes a control electrode connected to a first input signal terminal, a source terminal connected to the dummy anode terminal, a drain terminal connected to a source terminal via a first node. The pumping capacitor connects the first node and a first power source voltage terminal. The second transistor includes a control electrode connected to a second input signal terminal, a source terminal connected to the drain terminal of the first transistor, and a drain terminal connected to a second power source voltage terminal.
    Type: Grant
    Filed: December 16, 2014
    Date of Patent: September 19, 2017
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Kyong Tae Park, Mi Jin Yoon, Yu Hyun Cho
  • Patent number: 9722002
    Abstract: An organic light-emitting diode (OLED) display is disclosed. In one aspect, the OLED display includes a substrate including a pixel region including a plurality of pixels. A plurality of lighting test transistors is formed in a peripheral region surrounding the pixel region and electrically connected to the pixels, and the lighting test transistors are configured to test lighting of the pixels. Each of the lighting test transistors includes a first active layer pattern formed over the substrate, a first gate electrode formed over the first active layer pattern, and a conductive pattern formed over the first gate electrodes. The conductive pattern is electrically connected to the first gate electrode, the first gate electrodes are spaced apart from each other and have substantially the same shape, and the conductive patterns are integrally formed.
    Type: Grant
    Filed: September 22, 2015
    Date of Patent: August 1, 2017
    Assignee: Samsung Display Co., Ltd.
    Inventors: Kwang-Min Kim, Byoung-Sun Kim, Hyun-Ae Park, Hye-Jin Shin
  • Patent number: 9711357
    Abstract: A semiconductor device is manufactured in a semiconductor body by forming an initial mask on a process surface of a semiconductor layer, openings in the mask exposing a part of the semiconductor layer in alignment structure and super-junction structure areas. A recess structure is formed in the semiconductor layer at portions of the process surface that are exposed by the openings, the recess structure in the alignment structure area constituting an initial alignment structure. Dopants are introduced into the semiconductor layer through portions of the process surface that are exposed by the openings of the initial mask. The dopants introduced in the super-junction area constitute part of a super-junction structure. A thickness of the semiconductor layer is increased by growing an epitaxial layer. The initial alignment structure is imaged into the process surface. Dopants are introduced into the semiconductor layer by using a mask aligned to the initial alignment structure.
    Type: Grant
    Filed: March 21, 2016
    Date of Patent: July 18, 2017
    Assignee: Infineon Technologies Austria AG
    Inventors: Hans Weber, Andreas Moser, Johannes Baumgartl, Gabor Mezoesi
  • Patent number: 9698256
    Abstract: The present disclosure relates to an integrated circuit with a termination region, and an associated method of formation. In some embodiments, the integrated circuit comprises a cell region and a termination region. The termination region is disposed at an outer periphery of the cell region. The cell region comprises an array of device cells. The termination region comprises a plurality of termination rings encompassing the cell region. The plurality of termination rings have different depths.
    Type: Grant
    Filed: September 24, 2014
    Date of Patent: July 4, 2017
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Jheng-Sheng You, Che-Yi Lin, Shen-Ping Wang, Lieh-Chuan Chen, Po-Tao Chu
  • Patent number: 9685443
    Abstract: An integrated circuit includes an active device formed in a semiconductor layer of a first conductivity type, a first guard ring of the first conductivity type formed in the semiconductor layer surrounding at least part of the active device; a second guard ring of the second conductivity type formed in the semiconductor layer surrounding the first guard ring and the active device and including comprising alternating first well regions of the first conductivity type and the second well regions of the second conductivity type, the first and second well regions being electrically shorted together and electrically coupled to a ground potential or floating; and a third guard ring of the first conductivity type formed in the semiconductor layer surrounding the second guard ring. The first and third guard rings do not receive direct electrical connection.
    Type: Grant
    Filed: May 24, 2016
    Date of Patent: June 20, 2017
    Assignee: Alpha and Omega Semiconductor Incorporated
    Inventor: Shekar Mallikarjunaswamy
  • Patent number: 9673103
    Abstract: First and second transistors with different electrical characteristics are supported by a substrate having a first-type dopant. The first transistor includes a well region within the substrate having the first-type dopant, a first body region within the well region having a second-type dopant and a first source region within the first body region and laterally offset from the well region by a first channel. The second transistor includes a second body region within the semiconductor substrate layer having the second-type dopant and a second source region within the second body region and laterally offset from material of the substrate by a second channel having a length greater than the length of the first channel. A gate region extends over portions of the first and second body regions for the first and second channels, respectively.
    Type: Grant
    Filed: June 30, 2015
    Date of Patent: June 6, 2017
    Assignee: STMICROELECTRONICS, INC.
    Inventors: John C. Pritiskutch, Richard Hildenbrandt
  • Patent number: 9660059
    Abstract: In a method for fabricating a field-effect transistor (FET) structure, forming a fin on a semiconductor substrate. The method further includes forming a gate on a portion of the fin and the semiconductor substrate. The method further includes epitaxially growing a semiconductor material on the fin. The method further includes depositing oxide covering the fin and the epitaxially grown semiconductor material. The method further includes recessing the deposited oxide and the epitaxially grown semiconductor material to expose a top portion of the fin. The method further includes removing the fin. In another embodiment, the method further includes epitaxially growing another fin in a respective trench formed by removing the first set of fins.
    Type: Grant
    Filed: December 12, 2014
    Date of Patent: May 23, 2017
    Assignee: International Business Machines Corporation
    Inventors: Kangguo Cheng, Pouya Hashemi, Ali Khakifirooz, Alexander Reznicek, Dominic J. Schepis
  • Patent number: 9627517
    Abstract: A bipolar semiconductor switch having a semiconductor body is provided. The semiconductor body includes a first p-type semiconductor region, a second p-type semiconductor region, and a first n-type semiconductor region forming a first pn-junction with the first p-type semiconductor region and a second pn-junction with the second p-type semiconductor region. On a shortest path through the first n-type semiconductor region between the first pn-junction and the second pn-junction a concentration of charge recombination centers and a concentration of n-dopants vary. The concentration of the charge recombination centers has a maximum at a point along the shortest path where the concentration of n-dopants is at least close to a maximum dopant concentration. Further, a manufacturing method for the bipolar semiconductor switch is provided.
    Type: Grant
    Filed: February 7, 2013
    Date of Patent: April 18, 2017
    Assignee: Infineon Technologies AG
    Inventors: Hans-Joachim Schulze, Franz-Josef Niedernostheide
  • Patent number: 9543386
    Abstract: A semiconductor device includes field electrode structures extending in a direction vertical to a first surface in a semiconductor body. Cell mesas are formed from portions of the semiconductor body between the field electrode structures and include body zones that form first pn junctions with a drift zone. Gate structures between the field electrode structures control a current flow through the body zones. Auxiliary diode structures with a forward voltage lower than the first pn junctions are electrically connected in parallel with the first pn junctions, wherein semiconducting portions of the auxiliary diode structures are formed in the cell mesas.
    Type: Grant
    Filed: September 9, 2015
    Date of Patent: January 10, 2017
    Assignee: Infineon Technologies Austria AG
    Inventors: Ralf Siemieniec, Oliver Blank, Franz Hirler, Martin Henning Vielemeyer
  • Patent number: 9502498
    Abstract: A power semiconductor device may include a first conductivity type semiconductor substrate, a super-junction portion disposed on the first conductivity type semiconductor substrate and including a first conductivity type pillar and a second conductivity type pillar arranged in an alternating manner, and a three-dimensional (3D) gate portion disposed on the first conductivity type pillar. The 3D gate portion is disposed on the first conductivity type pillar to reduce the widths of the first and second conductivity type pillars, thereby effectively reducing a device size.
    Type: Grant
    Filed: February 9, 2015
    Date of Patent: November 22, 2016
    Assignee: Samsung Electro-Mechanics Co., Ltd.
    Inventors: Kyu Hyun Mo, Dong Soo Seo, Chang Su Jang, Jae Hoon Park, In Hyuk Song
  • Patent number: 9431428
    Abstract: A display device capable of operating at high speed and with low power consumption is provided. A miniaturized display device occupying a small area is also provided. The display device includes a support; a display portion which includes a pixel; a light-blocking unit which is in the support and includes a light-blocking layer having a first opening overlapping with at least part of the pixel, and a movable light-blocking layer blocking light passing through the first opening; a transistor which is electrically connected to the light-blocking unit and includes an oxide semiconductor film; and a capacitor electrically connected to the transistor.
    Type: Grant
    Filed: February 19, 2015
    Date of Patent: August 30, 2016
    Assignee: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
    Inventor: Shunpei Yamazaki
  • Patent number: 9431491
    Abstract: A semiconductor device including an active cell region formed over the surface of a silicon substrate and including a vertical MOSFET, a drain electrode formed over the surface of the silicon substrate and leading out the drain of the vertical MOSFET from the back surface of the silicon substrate, an external drain terminal formed over the drain electrode, and a source electrode formed over the active cell region so as to be opposed to the drain electrode at least along three sides at the periphery of the external drain terminal over the active cell region and connected to the source of the vertical MOSFET.
    Type: Grant
    Filed: May 20, 2014
    Date of Patent: August 30, 2016
    Assignee: Renesas Electronics Corporation
    Inventors: Takashi Aoki, Takahiro Korenari
  • Patent number: 9368587
    Abstract: An accumulation-mode field effect transistor including a plurality of gates. The accumulation-mode field effect transistor including a semiconductor region including a channel region adjacent to but insulated from each of the plurality of gates.
    Type: Grant
    Filed: May 31, 2014
    Date of Patent: June 14, 2016
    Assignee: Fairchild Semiconductor Corporation
    Inventors: Christopher Boguslaw Kocon, Praveen Muraleedharan Shenoy
  • Patent number: 9349847
    Abstract: A semiconductor device of this invention (an IGBT with a built-in diode) includes: an n?-type drift layer 1; a p-type channel region 2 that is arranged in contact with the surface side of this n?-type drift layer 1; a gate electrode 5 that is provided in a trench T provided so as to penetrate this p-type channel region 2 and reach to the n?-type drift layer 1 through a gate insulating film 3; an n-type source region 4 that is provided so as to contact the trench T on the surface side of the p-type channel region 2; a high-concentration n-type region 6 that is arranged in contact with the back side of the n?-type drift layer 1; and a high-concentration p-type region 7 that is arranged in contact with the back side of this high-concentration n-type region 6; in which a junction of the high-concentration n-type region 6 and the high-concentration p-type region 7 is a tunnel junction. According to this semiconductor device, it is possible to form the IGBT and the diode on a single chip.
    Type: Grant
    Filed: December 15, 2011
    Date of Patent: May 24, 2016
    Assignee: Hitachi, Ltd.
    Inventors: Takayuki Hashimoto, Mutsuhiro Mori
  • Patent number: 9324782
    Abstract: A semiconductor layer, a well region, and a source region form a unit cell. The unit cell is defined into a certain shape in plan view at a main surface of the semiconductor layer, and a plurality of the unit cells is coupled in a chain manner to form a unit chain structure with a constriction. The certain shape of the unit cell is defined by an outer edge of a virtual region of the semiconductor layer defined so as to include the source region and the well region inside and by respective outer edges of the source region and the well region at a joint with a different unit cell. An active region is composed of a plurality of the unit chain structures. The unit chain structures are arranged so as to avoid generation of a gap between the unit cells of adjacent ones of the unit chain structures.
    Type: Grant
    Filed: November 9, 2012
    Date of Patent: April 26, 2016
    Assignee: Mitsubishi Electric Corporation
    Inventors: Naruhisa Miura, Shiro Hino, Kenichi Ohtsuka
  • Patent number: 9318597
    Abstract: A semiconductor device includes a vertical field-effect-transistor (FET) and a bypass diode. The vertical FET device includes a substrate, a drift layer formed over the substrate, a gate contact and a plurality of source contacts located on a first surface of the drift layer opposite the substrate, a drain contact located on a surface of the substrate opposite the drift layer, and a plurality of junction implants, each of the plurality of junction implants laterally separated from one another on the surface of the drift layer opposite the substrate and extending downward toward the substrate. Each of the one or more bypass diodes are formed by placing a Schottky metal contact on the first surface of the drift layer, such that each Schottky metal contact runs between two of the plurality of junction implants.
    Type: Grant
    Filed: September 20, 2013
    Date of Patent: April 19, 2016
    Assignee: Cree, Inc.
    Inventors: Vipindas Pala, Edward Robert Van Brunt, Lin Cheng, John Williams Palmour
  • Patent number: 9299774
    Abstract: A semiconductor device has a substrate and a gate formed over the substrate. An LDD region is formed in the substrate adjacent to the gate. A superjunction is formed in the LDD region while a portion of the LDD region remains between the superjunction and gate. A mask is formed over the substrate. A first region is doped with a first type of dopant using the mask. A stripe is doped with a second type of dopant using a portion of the mask. A drain contact region is formed in the substrate. The first region extends to the drain contact region. The first region and stripe are formed using chain implants. A source field plate and drain field plate are formed over the substrate. A trench is formed in the substrate. A source contact region is formed in the trench.
    Type: Grant
    Filed: July 16, 2014
    Date of Patent: March 29, 2016
    Assignee: Great Wall Semiconductor Corporation
    Inventors: Patrick M. Shea, Samuel J. Anderson, David N. Okada
  • Patent number: 9214458
    Abstract: In a semiconductor device having a built-in Schottky barrier diode as a reflux diode, a maximum unipolar current is increased in a reflux state and a leakage current is reduced in an OFF state. A Schottky electrode is provided in at least a part of a surface between adjacent well regions of a second conductivity type disposed on a surface layer side of a drift layer of a first conductivity type, and an impurity concentration of a first conductivity type in a first region provided in a lower part of the Schottky electrode and provided between the adjacent well regions is set to be higher than a first impurity concentration of a first conductivity type in the drift layer and to be lower than a second impurity concentration of a second conductivity type in the well region.
    Type: Grant
    Filed: April 11, 2013
    Date of Patent: December 15, 2015
    Assignee: Mitsubishi Electric Corporation
    Inventors: Shiro Hino, Naruhisa Miura, Masayuki Imaizumi
  • Patent number: 9190468
    Abstract: A semiconductor device that can improve reliability while suppressing increase of a conduction loss or a switching loss. In the semiconductor device, when a two-dimensional shape on a main surface of the semiconductor substrate is an unit cell, the shape being a repeating unit of a plurality of well regions periodically disposed in a surface layer of a drift layer, one unit cell and another unit cell adjacent in an x-axis direction are disposed misaligned in a y-axis direction, and one unit cell and another unit cell adjacent in the y-axis direction are disposed misaligned in the x-axis direction.
    Type: Grant
    Filed: September 24, 2012
    Date of Patent: November 17, 2015
    Assignee: Mitsubishi Electric Corporation
    Inventors: Shiro Hino, Naruhisa Miura, Akihiko Furukawa, Tomokatsu Watanabe, Kenichi Ohtsuka, Hiroshi Watanabe, Yuji Ebiike
  • Patent number: 9184258
    Abstract: A semiconductor device according to one embodiment includes an n-type first GaN-based semiconductor layer, a p-type second GaN-based semiconductor layer on the first GaN-based semiconductor layer. The second GaN-based semiconductor layer includes a low impurity concentration region and a high impurity concentration region. An n-type third GaN-based semiconductor layer is provided on the second GaN-based semiconductor layer. The device includes a gate electrode being located adjacent to the third GaN-based semiconductor layer, the low impurity concentration region, and the first GaN-based semiconductor layer intervening a gate insulating film. The device includes a first electrode on the third GaN-based semiconductor layer, a second electrode on the high impurity concentration region, and a third electrode on the opposite side of the first GaN-based semiconductor layer from the second GaN-based semiconductor layer.
    Type: Grant
    Filed: March 17, 2014
    Date of Patent: November 10, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Akira Yoshioka, Toru Sugiyama, Yasunobu Saito, Kunio Tsuda
  • Patent number: 9159795
    Abstract: A high side DMOS provides high breakdown voltage with small termination area. The high side DMOS has three parts which may comprise a stair-field plate in the termination part of the poly gate.
    Type: Grant
    Filed: June 28, 2013
    Date of Patent: October 13, 2015
    Assignee: Monolithic Power Systems, Inc.
    Inventors: Ji-Hyoung Yoo, Lei Zhang, Daping Fu, Yanjie Lian
  • Patent number: 9123766
    Abstract: In accordance with an embodiment of the present invention a transistor is disclosed. The transistor comprises a collector, a base and an emitter, wherein a first end width of the base is larger than a middle width of the base, wherein a first end width of the collector is larger than a middle width of the collector, or wherein a first end width of the emitter is larger than a middle width of the emitter.
    Type: Grant
    Filed: September 26, 2013
    Date of Patent: September 1, 2015
    Assignee: Infineon Technologies AG
    Inventor: Klaus Diefenbeck
  • Patent number: 9064925
    Abstract: A power semiconductor device is disclosed with layers of different conductivity types between an emitter electrode on an emitter side and a collector electrode on a collector side. The device can include a drift layer, a first base layer in direct electrical contact to the emitter electrode, a first source region embedded into the first base layer which contacts the emitter electrode and has a higher doping concentration than the drift layer, a first gate electrode in a same plane and lateral to the first base layer, a second base layer in the same plane and lateral to the first base layer, a second gate electrode on top of the emitter side, and a second source region electrically insulated from the second base layer, the second source region and the drift layer by a second insulating layer.
    Type: Grant
    Filed: September 24, 2012
    Date of Patent: June 23, 2015
    Assignee: ABB TECHNOLOGY AG
    Inventors: Munaf Rahimo, Arnost Kopta, Christoph Von Arx, Maxi Andenna
  • Patent number: 9059283
    Abstract: A semiconductor structure is provided. The semiconductor structure includes a first doped region, a second doped region, a field oxide layer, a gate structure, and a metal layer. The first doped region has a first type conductivity. The second doped region is formed in the first doped region and has a second type conductivity opposite to the first type conductivity. The field oxide layer is located on the first doped region. The gate structure includes a first gate portion and a second gate portion which are separated from each other, wherein the second gate portion is located on the field oxide layer and electrically connected to a source end. The metal layer is located on the gate structure and includes a first metal portion and a second metal portion which are separated from each other.
    Type: Grant
    Filed: December 1, 2014
    Date of Patent: June 16, 2015
    Assignee: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Ching-Lin Chan, Cheng-Chi Lin
  • Patent number: 9048308
    Abstract: A rectifier building block has four electrodes: source, drain, gate and probe. The main current flows between the source and drain electrodes. The gate voltage controls the conductivity of a narrow channel under a MOS gate and can switch the RBB between OFF and ON states. Used in pairs, the RBB can be configured as a three terminal half-bridge rectifier which exhibits better than ideal diode performance, similar to synchronous rectifiers but without the need for control circuits. N-type and P-type pairs can be configured as a full bridge rectifier. Other combinations are possible to create a variety of devices.
    Type: Grant
    Filed: March 14, 2013
    Date of Patent: June 2, 2015
    Assignee: STMICROELECTRONICS INTERNATIONAL N.V.
    Inventors: Alexei Ankoudinov, Vladimir Rodov
  • Patent number: 9029945
    Abstract: A semiconductor device includes a drift layer having a first conductivity type, a well region in the drift layer having a second conductivity type opposite the first conductivity type, and a source region in the well region. The source region has the first conductivity type and defines a channel region in the well region. The source region includes a lateral source region adjacent the channel region and a plurality of source contact regions extending away from the lateral source region opposite the channel region. A body contact region having the second conductivity type is between at least two of the plurality of source contact regions and is in contact with the well region. A source ohmic contact overlaps at least one of the source contact regions and the body contact region. A minimum dimension of a source contact area of the semiconductor device is defined by an area of overlap between the source ohmic contact and the at least one source contact region.
    Type: Grant
    Filed: May 6, 2011
    Date of Patent: May 12, 2015
    Assignee: Cree, Inc.
    Inventors: Sei-Hyung Ryu, Doyle Craig Capell, Lin Cheng, Sarit Dhar, Charlotte Jonas, Anant Agarwal, John Palmour
  • Patent number: 9024382
    Abstract: According to one embodiment, the semiconductor device includes a drift region, a first semiconductor region, a second semiconductor region, a main electrode, first gate electrodes and a second gate electrode. The first gate electrodes and the second gate electrode between a pair of first gate electrodes are provided in the drift region. The first semiconductor region is provided between the first gate electrodes and the second gate electrode. The first semiconductor region has a first side surface opposite to the one of the adjacent ones and a second side surface partially opposite to the second gate electrode. The second semiconductor region is selectively provided on the first semiconductor region. The main electrode has a portion directly adjacent to part of the second side surface and the second semiconductor region.
    Type: Grant
    Filed: February 24, 2011
    Date of Patent: May 5, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Mitsuhiko Kitagawa
  • Patent number: 9024383
    Abstract: A super junction semiconductor device comprises a semiconductor portion with mesa regions protruding from a base section. The mesa regions are spatially separated in a lateral direction parallel to a first surface of the semiconductor portion. A compensation structure with at least two first compensation layers of a first conductivity type and at least two second compensation layers of a complementary second conductivity type may cover sidewalls of the mesa regions and portions of the base section between the mesa regions. Buried lateral faces of segments of the compensation structure may cut the first and second compensation layers between the mesa regions. A drain connection structure of the first conductivity type may extend along the buried lateral faces and may structurally connect the first compensation layers in an economic way keeping the thermal budget low.
    Type: Grant
    Filed: May 1, 2013
    Date of Patent: May 5, 2015
    Assignee: Infineon Technologies Austria AG
    Inventors: Stefan Gamerith, Armin Willmeroth, Franz Hirler
  • Patent number: 9012984
    Abstract: A transistor device includes a drift layer having a first conductivity type, a body layer on the drift layer, the body layer having a second conductivity type opposite the first conductivity type, and a source region on the body layer, the source region having the first conductivity type. The device further includes a trench extending through the source region and the body layer and into the drift layer, a channel layer on the inner sidewall of the trench, the channel layer having the second conductivity type and having an inner sidewall opposite an inner sidewall of the trench, a gate insulator on the inner sidewall of the channel layer, and a gate contact on the gate insulator.
    Type: Grant
    Filed: March 13, 2013
    Date of Patent: April 21, 2015
    Assignee: Cree, Inc.
    Inventors: Lin Cheng, Anant Agarwal, John Palmour
  • Patent number: 9006839
    Abstract: In a semiconductor substrate of a semiconductor device, a drift layer, a body layer, an emitter layer, and a trench gate electrode are formed. When the semiconductor substrate is viewed in a plane manner, the semiconductor substrate is divided into a first region covered with a heat dissipation member, and a second region not covered with the heat dissipation member. A density of trench gate electrodes in the first region is equal to a density of trench gate electrodes in the second region. A value obtained by dividing an effective carrier amount of channel parts formed in the first region by an area of the first region is larger than a value obtained by dividing an effective carrier amount of channel parts formed in the second region by an area of the second region.
    Type: Grant
    Filed: April 25, 2014
    Date of Patent: April 14, 2015
    Assignee: Toyota Jidosha Kabushiki Kaisha
    Inventor: Tadashi Misumi
  • Patent number: 8999782
    Abstract: An electronic device can include a buried conductive region and a semiconductor layer over the buried conductive region. The electronic device can further include a horizontally-oriented doped region and a vertical conductive region, wherein the vertical conductive region is electrically connected to the horizontally-oriented doped region and the buried conductive region. The electronic device can still further include an insulating layer overlying the horizontally-oriented doped region, and a first conductive electrode overlying the insulating layer and the horizontally-oriented doped region, wherein a portion of the vertical conductive region does not underlie the first conductive electrode. The electronic device can include a Schottky contact that allows for a Schottky diode to be connected in parallel with a transistor. Processes of forming an electronic device allow a vertical conductive region to be formed after a conductive electrode, a gate electrode, a source region, or both.
    Type: Grant
    Filed: March 11, 2013
    Date of Patent: April 7, 2015
    Assignee: Semiconductor Components Industries, LLC
    Inventors: Gary H. Loechelt, Gordon M. Grivna
  • Patent number: 8975662
    Abstract: Source zones of a first conductivity type and body zones of a second conductivity type are formed in a semiconductor die. The source zones directly adjoin a first surface of the semiconductor die. A dielectric layer adjoins the first surface. Polysilicon plugs extend through the dielectric layer and are electrically connected to the source and the body zones. An impurity source containing at least one metallic recombination element is provided in contact with deposited polycrystalline silicon material forming the polysilicon plugs and distant to the semiconductor die. Atoms of the metallic recombination element, for example platinum atoms, may be diffused out from the impurity source into the semiconductor die to reliably reduce the reverse recovery charge.
    Type: Grant
    Filed: June 14, 2012
    Date of Patent: March 10, 2015
    Assignee: Infineon Technologies Austria AG
    Inventors: Michael Hutzler, Ralf Siemieniec, Oliver Blank
  • Patent number: 8975695
    Abstract: A display device capable of operating at high speed and with low power consumption is provided. A miniaturized display device occupying a small area is also provided. The display device includes a support; a display portion which includes a pixel; a light-blocking unit which is in the support and includes a light-blocking layer having a first opening overlapping with at least part of the pixel, and a movable light-blocking layer blocking light passing through the first opening; a transistor which is electrically connected to the light-blocking unit and includes an oxide semiconductor film; and a capacitor electrically connected to the transistor.
    Type: Grant
    Filed: April 16, 2014
    Date of Patent: March 10, 2015
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Shunpei Yamazaki
  • Patent number: 8975720
    Abstract: A superjunction device and methods for layout design and fabrication of a superjunction device are disclosed. A layout of active cell column structures can be configured so that a charge due to first conductivity type dopants balances out charge due to second conductivity type dopants in a doped layer in an active cell region. A layout of end portions of the active cell column structures proximate termination column structures can be configured so that a charge due to the first conductivity type dopants in the end portions and a charge due to the first conductivity type dopants in the termination column structures balances out charge due to the second conductivity type dopants in a portion of the doped layer between the termination column structures and the end portions.
    Type: Grant
    Filed: June 20, 2013
    Date of Patent: March 10, 2015
    Assignee: Alpha and Omega Semiconductor Incorporated
    Inventors: Lingpeng Guan, Madhur Bobde
  • Patent number: 8969961
    Abstract: A semiconductor body (10) comprises a field-effect transistor (11). The field-effect transistor (11) comprises a drain region (12) of a first conduction type, a source region (13) of the first conduction type, a drift region (16) and a channel region (14) of a second conduction type which is opposite to the first conduction type. The drift region (16) comprises at least two stripes (15, 32) of the first conduction type which extend from the drain region (12) in a direction towards the source region (13). The channel region (14) is arranged between the drift region (16) and the source region (13).
    Type: Grant
    Filed: November 7, 2008
    Date of Patent: March 3, 2015
    Assignee: AMS AG
    Inventors: Jong Mun Park, Verena Vescoli, Rainer Minixhofer
  • Patent number: 8969960
    Abstract: A power semiconductor device includes a second conductive type sense outer-peripheral well formed to surround a plurality of sense wells on the surface of a drift layer, a first conductive type main-cell source region selectively formed on the surface of the main cell well, a first conductive type sense source region selectively formed on the surface of the sense well, a first conductive type capacitor lower electrode region selectively formed on the surface of the sense outer-peripheral well, a gate insulation film formed on the channel regions and on the sense outer-peripheral well, a gate electrode formed on the gate insulation film, and a sense pad electrically connected to the sense well and the sense source region as well as on the sense outer-peripheral well and the capacitor lower electrode region.
    Type: Grant
    Filed: June 7, 2012
    Date of Patent: March 3, 2015
    Assignee: Mitsubishi Electric Corporation
    Inventors: Akihiko Furukawa, Yasuhiro Kagawa, Naruhisa Miura, Masayuki Imaizumi, Kazuyasu Nishikawa
  • Patent number: 8963245
    Abstract: An integrated circuit and component is disclosed. In one embodiment, the component is a compensation component, configuring the compensation regions in the drift zone in V-shaped fashion in order to achieve a convergence of the space charge zones from the upper to the lower end of the compensation regions is disclosed.
    Type: Grant
    Filed: August 6, 2013
    Date of Patent: February 24, 2015
    Assignee: Infineon Technologies Austria AG
    Inventors: Armin Willmeroth, Holger Kapels
  • Patent number: 8941175
    Abstract: A power array with a staggered arrangement for improving on-resistance and safe operating area of a device is provided. Each power array includes two or more rows with a plurality of parallel device units arranged along the row. Each device unit includes a source region, a drain region, and a gate disposed between the source region and the drain region, wherein each drain region is offset from the adjacent drain region of adjacent rows in a row direction.
    Type: Grant
    Filed: June 17, 2013
    Date of Patent: January 27, 2015
    Assignee: United Microelectronics Corp.
    Inventors: Wei-Lin Chen, Ke-Feng Lin, Chiu-Ling Lee, Chiu-Te Lee, Chih-Chung Wang, Hsuan-Po Liao
  • Patent number: 8940609
    Abstract: A semiconductor device and method of forming the semiconductor device are disclosed, where the semiconductor device includes additional implant regions in the source and drain areas of the device for improving Ron-sp and BVD characteristics of the device. The device includes a gate electrode formed over a channel region that separates first and second implant regions in the device substrate. The first implant region has a first conductivity type, and the second implant region has a second conductivity type. A source diffusion region is formed in the first implant region, and a drain diffusion region is formed in the second implant region.
    Type: Grant
    Filed: June 18, 2014
    Date of Patent: January 27, 2015
    Assignee: Macronix International Co., Ltd.
    Inventors: Chien-Chung Chen, Ming-Tung Lee, Shih-Chin Lien, Shyi-Yuan Wu
  • Patent number: RE45365
    Abstract: In one embodiment, a semiconductor device is formed in a body of semiconductor material. The semiconductor device includes a charge compensating trench formed in proximity to active portions of the device. The charge compensating trench includes a trench filled with various layers of semiconductor material including opposite conductivity type layers.
    Type: Grant
    Filed: September 5, 2013
    Date of Patent: February 10, 2015
    Assignee: Semiconductor Components Industries
    Inventors: Gary H. Loechelt, John M. Parsey, Jr., Peter J. Zdebel, Gordon M. Grivna
  • Patent number: RE45449
    Abstract: A power semiconductor element having a lightly doped drift and buffer layer is disclosed. One embodiment has, underneath and between deep well regions of a first conductivity type, a lightly doped drift and buffer layer of a second conductivity type. The drift and buffer layer has a minimum vertical extension between a drain contact layer on the adjacent surface of a semiconductor substrate and the bottom of the deepest well region which is at least equal to a minimum lateral distance between the deep well regions. The vertical extension can also be determined such that a total amount of dopant per unit area in the drift and buffer layer is larger than a breakdown charge amount at breakdown voltage.
    Type: Grant
    Filed: April 30, 2013
    Date of Patent: April 7, 2015
    Assignee: Infineon Technologies AG
    Inventors: Markus Zundel, Franz Hirler, Armin Willmeroth