Abstract: The present disclosure includes apparatuses and methods related to performing corner turn operations using sensing circuitry. An example apparatus comprises a first group of memory cells coupled to an access line and a plurality of sense lines and a second group of memory cells coupled to a plurality of access lines and one of the plurality of sense lines. The access line can be a same access line as one of the plurality of access lines. The example apparatus comprises a controller configured to cause a corner turn operation on an element stored in the first group of memory cells resulting in the element being stored in the second group of memory cells to be performed using sensing circuitry.

Abstract: A method of forming complementary vertical fins and vertical fins with uniform heights, including, forming a trench in a region of a substrate, wherein the trench extends through an upper portion of the substrate and a buried punch-through stop layer, and extends into a lower portion of the substrate, forming a reformed punch-through stop layer in a bottom portion of the trench, forming a fin formation region on the reformed punch-through stop layer, and forming a complementary vertical fin from the fin formation region and a vertical fin from the upper portion of the substrate on a first region of the substrate adjacent to the second region.

Abstract: A die stack comprises a first integrated circuit (IC) die having at least a first device comprising a first source, a first drain and a first gate electrode above a first channel region between the first source and the first drain. A second IC die has at least a second device comprising a second source, a second drain and a second gate electrode above a second channel region between the second source and the second drain. The second gate electrode is connected to the first gate electrode by a path including a first through substrate via (TSV), the second drain connected to the first source by a path including a second TSV.

Abstract: At least one method, apparatus and system disclosed involves an antenna diode design for a semiconductor device. A first common diode operatively coupled to a ground node and to a p-well layer serving as an isolated p-well that is formed over a deep n-well that is adjacent to an n-well in a semiconductor device is provided. A first antenna diode formed on the isolated p-well operatively coupled to the p-well layer and operatively coupled to a first signal line of the semiconductor device is provided for discharging accumulated charges on the first signal line. A second antenna diode formed on the isolated p-well operatively coupled to the p-well layer and operatively coupled to a second signal line of semiconductor device is provided for discharging accumulated charges on the second signal line.

Abstract: A method is provided for fabricating a semiconductor structure. The method includes providing a substrate including a first region for forming a first transistor and a second region for forming a second transistor. The method also includes forming a first stress layer in the substrate in the first region and a second stress layer in the substrate in the second region, wherein top surfaces of the first stress layer and the second stress layer are above a surface of the substrate. Further, the method includes forming a cover layer on each of the first stress layer and the second stress layer, and removing portions of the cover layer formed on adjacent side surfaces of the first stress layer and the second stress layer.

Abstract: A method includes forming first structures on a first portion of a silicon substrate and second structures on a second portion of the substrate; forming spacers on the first structures; forming dummy gates on the first and second structures; depositing a first interlayer dielectric on the dummy gates; removing the dummy gates from the second structures; forming metal gates on the second structures; performing an anneal; forming recess areas in the first interlayer dielectric; removing the spacers from the first structures; epitaxially growing sidewalls on the first structures; removing portions of the first structures outside the dummy gates from the first portion; depositing a second interlayer dielectric on the first portion; removing the dummy gates from the first portion; removing portions of the first structures previously under the dummy gates from the first portion; and forming metal gates on the first structures.

Abstract: A method includes forming first structures on a first portion of a silicon substrate and second structures on a second portion of the substrate; forming spacers on the first structures; forming dummy gates on the first and second structures; depositing a first interlayer dielectric on the dummy gates; removing the dummy gates from the second structures; forming metal gates on the second structures; performing an anneal; forming recess areas in the first interlayer dielectric; removing the spacers from the first structures; epitaxially growing sidewalls on the first structures; removing portions of the first structures outside the dummy gates from the first portion; depositing a second interlayer dielectric on the first portion; removing the dummy gates from the first portion; removing portions of the first structures previously under the dummy gates from the first portion; and forming metal gates on the first structures.

Abstract: An integrated circuit includes a first device having a first threshold voltage (Vt) adjusting implant extension region having a first conductivity type and extending from a first implant rail region under an entirety of a first channel region. The first implant rail region and first Vt adjusting implant extension region are contiguous, and the first channel region is over an insulating layer and the insulating layer is over the first implant rail region and first Vt adjusting implant extension region. A second device has a second Vt adjusting implant extension region having the first conductivity type and extending from a second implant rail region under an entirety of a second channel region. The second implant rail region and second Vt adjusting implant extension region are contiguous, and the second channel region is over the insulating layer and the insulating layer is over the second implant rail region and second Vt adjusting implant extension region.

Abstract: Low temperature epitaxial silicon deposition for forming the top source or drain regions of VTFET structures. The methods generally include epitaxially growing a silicon layer with a dopant at a temperature less 500° C. on a first surface and an additional surface to form a single crystalline silicon on the first surface and a polysilicon or amorphous silicon on the additional surface. The epitaxially grown silicon layer is then exposed to an etchant include HCl and germane at a temperature less than 500° C. for a period of time effective to selectively remove the polysilicon/amorphous silicon on the additional surface and form a germanium diffused region on and in an outer surface of the single crystalline silicon formed on the first surface.

Abstract: Vertical field effect transistors (FETs) with minimum pitch and methods of manufacture are disclosed. The structure includes at least one vertical fin structure and gate material contacting with the at least one vertical fin structure. The structure further includes metal material in electrical contact with the ends of the at least one vertical fin.

Abstract: An integrated circuit includes an array of devices including a physically unclonable function (PUF) for chip authentication. A logic pattern is stored in the devices. The logic pattern is determined in accordance with processing variations during manufacture of the array. The logic pattern is represented with a first state for one or more devices with contact shorts and a second state with one or more devices without contact shorts.

Abstract: A semiconductor device includes channel layers disposed over a substrate, a source/drain region disposed over the substrate, a gate dielectric layer disposed on and wrapping each of the channel layers, and a gate electrode layer disposed on the gate dielectric layer and wrapping each of the channel layers. Each of the channel layers includes a semiconductor wire made of a first semiconductor material. The semiconductor wire extends into the source/drain region. The semiconductor wire in the source/drain regions is wrapped around by a second semiconductor material.

Abstract: A semiconductor integrated circuit according to an embodiment includes: a CMOS inverter including an n-channel transistor and a p-channel transistor, one of the n-channel transistor and the p-channel transistor being disposed above the other of the n-channel transistor and the p-channel transistor.

Abstract: A semiconductor device and a method to form the semiconductor device are disclosed. An n-channel component of the semiconductor device includes a first horizontal nanosheet (hNS) stack and a p-channel component includes a second hNS stack. The first hNS stack includes a first gate structure having a plurality of first gate layers and at least one first channel layer. A first internal spacer is disposed between at least one first gate layer and a first source/drain structure in which the first internal spacer has a first length. The second hNS stack includes a second gate structure having a plurality of second gate layers and at least one second channel layer. A second internal spacer is disposed between at least one second gate layer and a second source/drain structure in which the second internal spacer has a second length that is greater than the first length.

Abstract: A FinFET comprises a hybrid substrate having a top wafer of (100) silicon, a handle wafer of (110) silicon, and a buried oxide layer between the top wafer and the handle wafer; a first set of fins disposed in the top wafer and oriented in a <110> direction of the (100) silicon; and a second set of fins disposed in the handle wafer and oriented in a <112> direction of the (110) silicon. The first set of fins and the second set of fins are aligned.

Abstract: An array substrate, a manufacturing method thereof and a display panel are disclosed. The array substrate comprises: a base substrate (200) and gate lines (202), data lines (205) and a plurality of pixel units (20). Each pixel unit (20) includes a first thin-film transistor (TFT), a pixel electrode (208) and at least second TFT connected in series with the first TFT. The pixel electrode (208) is connected with a drain electrode (207) of the second TFT; a source electrode (206?) of the second TFT is connected with a drain electrode (207) of the first TFT; and a source electrode (206) of the first TFT is connected with the data line (205). The array substrate can reduce the leakage current when the TFTs are switched off.

Abstract: An integrated circuit chip includes a first type memory cell and a second type memory cell. The first type memory cell includes a first reference line landing pad and a first word line landing pad. The first reference line landing pad of the first type memory cell and the first word line landing pad of the first type memory cell are aligned along a first direction. The second type memory cell includes a first reference line segment extending along the first direction and a first word line landing pad. The first word line landing pad of the second type memory cell and the first reference line segment of the second type memory cell are spaced apart along a second direction different from the first direction.

Abstract: Provided is a semiconductor device. The semiconductor device includes a fin disposed on a substrate along a first direction. A sacrificial layer is disposed on the fin. An active layer is disposed on the sacrificial layer. A gate insulating layer and a gate electrode are disposed along a second direction intersecting the first direction. The gate insulating layer covers substantially entire top, side and bottom surfaces of the active layer. A source or drain region is disposed on at least one side of the gate electrode on the substrate. A first concentration of germanium in a first region and a second region of the active layer is higher than a second concentration of germanium in a third region disposed between the first region and the second region.

Abstract: A method of forming an arrangement of long and short fins on a substrate, including forming a plurality of finFET devices having long fins on the substrate, where the long fins have a fin length in the range of about 180 nm to about 350 nm, and forming a plurality of finFET devices having short fins on the substrate, where the short fins have a fin length in the range of about 60 nm to about 140 nm, wherein at least one of the plurality of finFET devices having a long fin is adjacent to at least one of the plurality of finFET devices having a short fin.

Abstract: An integrated circuit structure may include an alignment column on a front-side surface of an isolation layer. The alignment column may extend through a backside surface opposite the front-side surface of the isolation layer. The integrated circuit structure may also include front-side transistors on the front-side surface of the isolation layer. The integrated circuit structure may further include backside transistors on the backside surface of the isolation layer. A first front-side transistor is aligned with a first backside transistor according to the alignment column.

Abstract: A device includes a gate isolation plug, which further includes a U-shaped layer having a bottom portion and two sidewall portions, and an inner region overlapping the bottom portion. The inner region contacts the two sidewall portions. A first transistor has a first gate stack, and a first end of the first gate stack is in contact with both the inner region and the U-shaped layer of the gate isolation plug. A second transistor has a second gate stack, and a second end of the second gate stack is in contact with both the inner region and the U-shaped layer of the gate isolation plug. The first gate stack and the second gate stack are on opposite sides of the gate isolation plug.

Abstract: Ge and III-V channel semiconductor devices having maximized compliance and free surface relaxation and methods of fabricating such Ge and III-V channel semiconductor devices are described. For example, a semiconductor device includes a semiconductor fin disposed above a semiconductor substrate. The semiconductor fin has a central protruding or recessed segment spaced apart from a pair of protruding outer segments along a length of the semiconductor fin. A cladding layer region is disposed on the central protruding or recessed segment of the semiconductor fin. A gate stack is disposed on the cladding layer region. Source/drain regions are disposed in the pair of protruding outer segments of the semiconductor fin.

Abstract: In a method of manufacturing a semiconductor device, a thermal treatment is performed on a substrate, thereby forming a defect free layer in an upper layer of the substrate, where a remaining layer of the substrate is a bulk layer. A density of defects in the bulk layer is equal to or more than 1×108 cm?3, where the defects are bulk micro defects. An electronic device is formed over the defect free layer. An opening is formed in the defect free layer such that the opening does not reach the bulk layer. The opening is filled with a conductive material, thereby forming a via. The bulk layer is removed so that a bottom part of the via is exposed. A density of defects in the defect free layer is less than 100 cm?3.

Abstract: Structures and formation methods of a semiconductor device structure are provided. The semiconductor device structure includes a fin structure over a semiconductor substrate and a gate stack covering a portion of the fin structure. The gate stack includes a work function layer and a gate dielectric layer. The semiconductor device structure also includes an isolation element over the semiconductor substrate and adjacent to the gate stack.

Abstract: A semiconductor device using an SOI (Silicon On Insulator) substrate, capable of preventing malfunction of MISFETs (Metal Insulator Semiconductor Field Effect Transistor) and thus improving the reliability of the semiconductor device. Moreover, the parasitic resistance of the MISFETs is reduced, and the performance of the semiconductor device is improved. An epitaxial layer formed on an SOI layer above an SOI substrate is formed to have a large width so as to cover the ends of the upper surface of an isolation region adjacent to the SOI layer. By virtue of this, contact plugs of which formation positions are misaligned are prevented from being connected to a semiconductor substrate below the SOI layer. Moreover, by forming the epitaxial layer at a large width, the ends of the SOI layer therebelow are prevented from being silicided. As a result, increase in the parasitic resistance of MISFETs is prevented.

Abstract: Methods and structures for forming highly-doped, ultrathin layers for transistors formed in semiconductor-on-insulator substrates are described. High dopant concentrations may be achieved in ultrathin semiconductor layers to improve device characteristics. Ion implantation at elevated temperatures may mitigate defect formation for stoichiometric dopant concentrations up to about 30%. In-plane stressors may be formed adjacent to channels of transistors formed in ultrathin semiconductor layers.

Abstract: In a particular aspect, an integrated circuit includes a first transistor including a first source region and a first drain region. The integrated circuit includes a second transistor including a second source region and a second drain region. The integrated circuit includes a first gate structure coupled to the first transistor and to the second transistor. The first gate structure is included in a first layer. The integrated circuit further includes a first metal line coupled to the first source region and to the second drain region. The first metal line has a two-dimensional routing arrangement and is included in a second layer that is distinct from the first layer.

Abstract: Integrated circuit equipped with at least two levels of superimposed transistors, comprising: a first transistor at a first level, a first plug, a second plug and a third plug, connected to a drain region, a gate and a source region respectively of the first transistor, the first plug, the second plug and the third plug passing through an insulating layer covering the first transistor a second transistor equipped with an active zone defined in a semi-conducting layer arranged at one end of the plugs and facing the first transistor, the transistor comprising a gate arranged between the first plug and the third plug.

Abstract: A touch sensor integrated display device includes a plurality of common electrode blocks that defines a plurality of touch driving channels and a plurality of touch sensing channels. The touch driving channel is formed of a group of common electrode blocks electrically linked via a touch signal line placed under the layer of the common electrode blocks. The source/drain of the circuit TFTs provided in the non-display area is formed of the same metal layer of the touch signal line. The source/drain of the pixel TFTs provided in the display area is formed of a metal layer different from the metal layer of the touch signal line.

Abstract: A method of fabricating raised fin structures is provided, the fabricating including: providing a substrate and at least one dielectric layer over the substrate; forming a trench in the at least one dielectric layer, the trench having a lower portion, a lateral portion, and an upper portion, the upper portion being at least partially laterally offset from the lower portion and being joined to the lower portion by the lateral portion; and, growing a material in the trench to form the raised fin structure, wherein the trench is formed to ensure that any growth defect in the lower portion of the trench terminates either in the lower portion or the lateral portion of the trench and does not extend into the upper portion of the trench.

Abstract: A substrate contact land for a first MOS transistor is produced in and on an active zone of a substrate of silicon on insulator type using a second MOS transistor without any PN junction that is also provided in the active zone. A contact land on at least one of a source or drain region of the second MOS transistor forms the substrate contact land.

Abstract: Embodiments relate to an improved tri-gate device having gate metal fills, providing compressive or tensile stress upon at least a portion of the tri-gate transistor, thereby increasing the carrier mobility and operating frequency. Embodiments also contemplate method for use of the improved tri-gate device.

Abstract: An offset spacer film (OSS) is formed on a side wall surface of a gate electrode (NLGE, PLGE) to cover a region in which a photo diode (PD) is disposed. Next, an extension region (LNLD, LPLD) is formed using the offset spacer film and the like as an implantation mask. Next, process is provided to remove the offset spacer film covering the region in which the photo diode is disposed. Next, a sidewall insulating film (SWI) is formed on the side wall surface of the gate electrode. Next, a source-drain region (HPDF, LPDF, HNDF, LNDF) is formed using the sidewall insulating film and the like as an implantation mask.

Abstract: A semiconductor structure is provided that includes a plurality of suspended and stacked nanosheets of semiconductor channel material located above a pillar of a sacrificial III-V compound semiconductor material. Each semiconductor channel material comprises a semiconductor material that is substantially lattice matched to, but different from, the sacrificial III-V compound semiconductor material, and each suspended and stacked nanosheets of semiconductor channel material has a chevron shape. A functional gate structure can be formed around each suspended and stacked nanosheet of semiconductor channel material.

Abstract: A semiconductor device includes an extremely thin semiconductor-on-insulator substrate (ETSOI) having a base substrate, a thin semiconductor layer and a buried dielectric therebetween. A device channel is formed in the thin semiconductor layer. Source and drain regions are formed at opposing positions relative to the device channel. The source and drain regions include an n-type material deposited on the buried dielectric within a thickness of the thin semiconductor layer. A gate structure is formed over the device channel.

Abstract: A method includes providing a semiconductor substrate having first and second regions that are doped with first and second dopants respectively. The first and second dopants are of opposite types. The method further includes epitaxially growing a first semiconductor layer that is doped with a third dopant. The first and third dopants are of opposite types. The method further includes depositing a dielectric hard mask (HM) layer over the first semiconductor layer; patterning the dielectric HM layer to have an opening over the first region; extending the opening towards the semiconductor substrate; and epitaxially growing a second semiconductor layer in the opening. The second semiconductor layer is doped with a fourth dopant. The first and fourth dopants are of a same type. The method further includes removing the dielectric HM layer; and performing a first CMP process to planarize both the first and second semiconductor layers.

Abstract: A semiconductor device includes a substrate, fin-shaped structures, a protection layer, epitaxial layers, and a gate electrode. The fin-shaped structures are disposed in a first region and a second region of the substrate. The protection layer conformally covers the surface of the substrate and the sidewalls of fin-shaped structures. The epitaxial layers respectively conformally and directly cover the fin-shaped structures in the first region. The gate electrode covers the fin-shaped structures in the second region, and the protection layer is disposed between the gate electrode and the fin-shaped structures.

Abstract: A semiconductor device for simultaneous operation at two temperature ranges includes a substrate, a first transistor, and a second transistor. The substrate has a first active region and a second active region. The first transistor includes a plurality of gate stacks disposed in the first active region. The second transistor includes a plurality of gate stacks disposed in the second active region. A ratio of the number of the gate stacks of the second transistor to an area size of the second active region is less than a ratio of the number of the gate stacks of the first transistor to an area size of the first active region.

Abstract: A method comprises forming one or more fins in a first region on an insulated substrate. The method also comprises forming one or more fins formed in a second region on the insulated substrate. The insulated substrate comprising a silicon substrate, and an insulator layer deposited on the silicon substrate. The one or more fins in the first region comprising a first material layer deposited on the insulator layer. The one or more fins in the second region comprising a second material layer deposited on the insulator layer.

Abstract: A first channel structure includes SixGe1-x and a second channel structure includes a group III-V compound material. First and second gate stacks are formed on the first and second channel structures. An insulating layer is formed on the gate stacks and the channel structures and is removed from the first channel structure to form a spacer on sidewalls of the first gate stack. First raised source and drain layers are formed on the first channel structure. The insulating layer is removed from the second channel structure to form a spacer on sidewalls of the second gate stack. The surfaces of the first and second channel structures and first source and drain layers are oxidized. The oxide layers are treated by a cleaning process that selectively removes the second native oxide layer only. Second raised source and drain layers are formed on the second channel structure. A CMOS structure is disclosed.

Abstract: A semiconductor device includes: a first active region defined by a recess contained in a device isolation film of a semiconductor substrate belonging to a first region and a second region, in a peripheral region including the first region, the second region, and a third region; a second active region defined by the device isolation film contained in the semiconductor substrate of the third region; a buried metal layer buried in the recess; a first conductive layer formed over the semiconductor substrate of the first region; and a second conductive layer formed over the semiconductor substrate of the second region, wherein the first conductive layer or the second conductive layer is formed over the semiconductor substrate of the third region. A three-dimensional dual gate is formed in a peripheral region, such that performance or throughput of transistors is maximized even in the peripheral region.

Abstract: A semiconductor process includes the following step. A metal gate strip and a cap layer are sequentially formed in a trench of a dielectric layer. The cap layer and the metal gate strip are cut off to form a plurality of caps on a plurality of metal gates, and a gap isolates adjacent caps and adjacent metal gates. An isolation material fills in the gap. The present invention also provides semiconductor structures formed by said semiconductor process. For example, the semiconductor structure includes a plurality of stacked structures in a trench of a dielectric layer, where each of the stacked structures includes a metal gate and a cap on the metal gate, where an isolation slot isolates and contacts adjacent stacked structures at end to end, and the isolation slot has same level as the stacked structures.

Abstract: A structure includes a substrate and a tunnel field effect transistor (TFET). The TFET includes a source region disposed in the substrate having an overlying source contact, the source region containing first semiconductor material having a first doping type; a drain region disposed in the substrate having an overlying drain contact, the drain region containing second semiconductor material having a second, opposite doping type; and a gate structure that overlies a channel region between the source and the drain. The source region and the drain region are asymmetric with respect to one another such that one contains a larger volume of semiconductor material than the other one. A method is disclosed to fabricate a plurality of the TFETs using a plurality of spaced apart mandrels having spacers. A pair of the mandrels and the associated spacers is processed to form four adjacent TFETs without requiring intervening lithographic processes.

Abstract: Vertical field effect transistors (FETs) with minimum pitch and methods of manufacture are disclosed. The structure includes at least one vertical fin structure and gate material contacting with the at least one vertical fin structure. The structure further includes metal material in electrical contact with the ends of the at least one vertical fin.

Abstract: Directed self-assembly (DSA) material, or di-block co-polymer, to pattern features that ultimately define a channel region a gate electrode of a vertical nanowire transistor, potentially based on one lithographic operation. In embodiments, DSA material is confined within a guide opening patterned using convention lithography. In embodiments, channel regions and gate electrode materials are aligned to edges of segregated regions within the DSA material.

Abstract: A three-dimensional stacked fin complementary metal oxide semiconductor (CMOS) device having dual work function metal gate structures is provided. The stacked fin CMOS device includes a fin stack having a first semiconductor fin over a substrate, a dielectric fin atop the first semiconductor fin and a second semiconductor fin atop the dielectric fin, and a gate sack straddling the fin stack. The gate stack includes a first metal gate portion surrounding a channel portion of the first semiconductor fin and a second metal gate portion surrounding a channel portion of the second semiconductor fin. The first metal gate portion has a first work function suitable to reduce a threshold voltage of a field effect transistor (FET) of a first conductivity type, while the second gate portion has a second work function suitable to reduce a threshold voltage of a FET of a second conductivity type opposite the first conductivity type.

Abstract: Methods of fabricating semiconductor structures involve the formation of fins for finFET transistors having different stress/strain states. Fins of one stress/strain state may be employed to form n-type finFETS, while fins of another stress/strain state may be employed to form p-type finFETs. The fins having different stress/strain states may be fabricated from a common layer of semiconductor material. Semiconductor structures and devices are fabricated using such methods.

Abstract: A gate insulating film and a gate electrode of non-single crystalline silicon for forming an nMOS transistor are provided on a silicon substrate. Using the gate electrode as a mask, n-type dopants having a relatively large mass number (70 or more) such as As ions or Sb ions are implanted, to form a source/drain region of the nMOS transistor, whereby the gate electrode is amorphized. Subsequently, a silicon oxide film is provided to cover the gate electrode, at a temperature which is less than the one at which recrystallization of the gate electrode occurs. Thereafter, thermal processing is performed at a temperature of about 1000° C., whereby high compressive residual stress is exerted on the gate electrode, and high tensile stress is applied to a channel region under the gate electrode. As a result, carrier mobility of the nMOS transistor is enhanced.

Abstract: One illustrative method disclosed herein includes, among other things, forming a plurality of initial fins that have the same initial axial length and the same initial strain above a substrate, performing at least one etching process so as to cut a first fin to a first axial length and to cut a second fin to a second axial length that is less than the first axial length, wherein the cut first fin retains a first amount of the initial strain and the cut second fin retains about zero of the initial strain or a second amount of the initial strain that is less than the first amount, and forming gate structures around the first and second cut fins to form FinFET devices.

Abstract: Tunneling field effect transistors (TFETs) for CMOS architectures and approaches to fabricating N-type and P-type TFETs are described. For example, a tunneling field effect transistor (TFET) includes a homojunction active region disposed above a substrate. The homojunction active region includes a relaxed Ge or GeSn body having an undoped channel region therein. The homojunction active region also includes doped source and drain regions disposed in the relaxed Ge or GeSn body, on either side of the channel region. The TFET also includes a gate stack disposed on the channel region, between the source and drain regions. The gate stack includes a gate dielectric portion and gate electrode portion.