Abstract: A method for manufacturing a fin field-effect transistor (FinFET) device comprises forming a plurality of fins on a substrate, epitaxially growing a sacrificial epitaxy region between the fins, stopping growth of the sacrificial epitaxy region at a beginning of merging of epitaxial shapes between neighboring fins, and forming a dielectric layer on the substrate including the fins and the sacrificial epitaxy region, wherein a portion of the dielectric layer is positioned between the sacrificial epitaxy region extending from fins of adjacent transistors.

Abstract: A three-dimensional stacked fin complementary metal oxide semiconductor (CMOS) device having dual work function metal gate structures is provided. The stacked fin CMOS device includes a fin stack having a first semiconductor fin over a substrate, a dielectric fin atop the first semiconductor fin and a second semiconductor fin atop the dielectric fin, and a gate sack straddling the fin stack. The gate stack includes a first metal gate portion surrounding a channel portion of the first semiconductor fin and a second metal gate portion surrounding a channel portion of the second semiconductor fin. The first metal gate portion has a first work function suitable to reduce a threshold voltage of a field effect transistor (FET) of a first conductivity type, while the second gate portion has a second work function suitable to reduce a threshold voltage of a FET of a second conductivity type opposite the first conductivity type.

Abstract: A semiconductor structure provided having: a dielectric; a non-column III-V doped semiconductor layer disposed over the dielectric; and an isolation barrier comprising column III-V material disposed vertically through the semiconductor layer to the dielectric. In one embodiment, the semiconductor layer is silicon and has CMOS transistors disposed in the semiconductor layer above a first region of the dielectric and a III-V transistor disposed above a different region of the dielectric. The barrier electrically isolates the column III-V transistor from the CMOS transistors. In one embodiment, the structure includes a passive device disposed over the semiconductor layer and a plurality of laterally spaced III-V structures, the III-V structures being disposed under the passive device, the III-V structures passing vertically through the semiconductor layer to the insulating layer.

Abstract: An organic light-emitting display device and a method of manufacturing the same. The organic light-emitting display device includes: a substrate; an active layer on the substrate; a gate electrode insulated from the active layer and overlapping the active layer; a source electrode including a first source electrode layer connected to the active layer and a second source electrode layer connected to the first source electrode layer and being larger than the first source electrode layer; a drain electrode including a first drain electrode layer connected to the active layer and a second drain electrode layer connected to the first drain electrode layer and being larger than the first drain electrode layer; a first electrode electrically connected to the source electrode or the drain electrode; an intermediate layer on the first electrode and including an organic emission layer; and a second electrode on the intermediate layer.

Abstract: A thin film transistor includes: a substrate, a semiconductor layer disposed on the substrate, a first gate electrode and a second gate electrode disposed on the semiconductor layer, a gate insulating layer disposed between the semiconductor layer and the first and second gate electrodes and having a first through hole between the first and second gate electrodes and a capping layer covering the first gate electrode and contacting the semiconductor layer via the first through hole. The capping layer includes a conductive material.

Abstract: Systems and methods are provided for fabricating semiconductor device structures on a substrate. For example, a substrate including a first region and a second region is provided. One or more first semiconductor device structures are formed on the first region. One or more semiconductor fins are formed on the second region. One or more second semiconductor device structures are formed on the semiconductor fins. A top surface of the semiconductor fins is higher than a top surface of the first semiconductor device structures.

Abstract: An object of the present invention is to provide a semiconductor device having a fin-type transistor that is excellent in characteristics by forming a fin-shaped semiconductor portion and a gate electrode with high precision or by making improvement regarding variations in characteristics among elements. The present invention is a semiconductor device including a fin-shaped semiconductor portion having a source region formed on one side thereof and a drain region formed on the other side thereof, and a gate electrode formed between the source region and the drain region to surround the fin-shaped semiconductor portion with a gate insulating film interposed therebetween. One solution for solving the problem according to the invention is that the gate electrode uses a metal material or a silicide material that is wet etchable.

Abstract: A CMOS device with transistors having different gate dielectric materials and a method of manufacture thereof. A CMOS device is formed on a workpiece having a first region and a second region. A first gate dielectric material is deposited over the second region. A first gate material is deposited over the first gate dielectric material. A second gate dielectric material comprising a different material than the first gate dielectric material is deposited over the first region of the workpiece. A second gate material is deposited over the second gate dielectric material. The first gate material, the first gate dielectric material, the second gate material, and the second gate dielectric material are then patterned to form a CMOS device having a symmetric Vt for the PMOS and NMOS FETs.

Abstract: Directed self-assembly (DSA) material, or di-block co-polymer, to pattern features that ultimately define a channel region a gate electrode of a vertical nanowire transistor, potentially based on one lithographic operation. In embodiments, DSA material is confined within a guide opening patterned using convention lithography. In embodiments, channel regions and gate electrode materials are aligned to edges of segregated regions within the DSA material.

Abstract: A semiconductor device in one embodiment includes a semiconductor substrate, a fin disposed on a surface of the semiconductor substrate, an insulator including a gate insulator disposed on a side surface of the fin, and a gate electrode disposed on the insulator that is disposed on side surfaces of the fin and an upper surface of the fin. The device further includes a plurality of epitaxial stripe shaped layers disposed horizontally on the side surface of the fin at different heights, and an interlayer dielectric disposed on the semiconductor substrate to cover the fin and applying a stress to the fin and the epitaxial layers. Any two adjacent epitaxial layers along the fin height direction determine a gap and the gaps between adjacent layers increase or decrease with increasing distance from the substrate.

Abstract: The present disclosure discloses a metal-oxide-semiconductor field-effect transistor (MOSFET) and a method for manufacturing the same. The MOSFET includes: a silicon on insulator (SOI) wafer which comprises a semiconductor substrate, a buried insulating layer, and a semiconductor layer, the buried insulating layer being on the semiconductor substrate, and the semiconductor layer being on the buried insulating layer; a gate stack on the semiconductor layer; a source region and a drain region, which are in the semiconductor layer and on opposite sides of the gate stack; and a channel region, which is in the semiconductor layer and sandwiched by the source region and the drain region, wherein the MOSFET further comprises a back gate, the back gate being located in the semiconductor substrate and having a first doped region in a lower portion of the back gate and a second doped region in an upper portion of the back gate.

Abstract: A device including a p-type semiconductor device and an n-type semiconductor device on a semiconductor substrate. The n-type semiconductor device includes a gate structure having a high-k gate dielectric. A carbon dopant in a concentration ranging from 1×1016 atoms/cm3 to 1×1021 atoms/cm3 is present at an interface between the high-k gate dielectric of the gate structure for the n-type semiconductor device and the semiconductor substrate. Methods of forming the aforementioned device are also disclosed.

Abstract: A FinFET having a backgate and a barrier layer beneath the fin channel of the FinFET, where the barrier layer has a bandgap greater than that of the backgate. The barrier layer serves as an etch stop layer under the fin channel, resulting in reduced fin channel height variation. The backgate provides improved current control. There is less punchthrough due to the higher bandgap barrier layer. The FinFET may also include deeply embedded stressors adjacent to the source/drain diffusions through the high bandgap barrier layer.

Abstract: The present disclosure provides a semiconductor device and a method for manufacturing the same. The semiconductor device comprises: an SOI wafer comprising a semiconductor substrate, an insulating buried layer, and a semiconductor layer, wherein the insulating buried layer is disposed on the semiconductor substrate, and the semiconductor layer is disposed on the insulating buried layer; adjacent MOSFETs formed in the SOI wafer, wherein each of the adjacent MOSFETs comprises a back gate formed in the semiconductor substrate and a back gate isolation region formed completely under the back gate; and a shallow trench isolation, wherein the shallow trench isolation is formed between the adjacent MOSFETs to isolate the adjacent MOSFETs from each other, wherein a PN junction is formed between the back gate and the back gate isolation region of each of the adjacent MOSFETs. According to embodiments of the present disclosure, a PN junction is formed between the back gate isolation regions of the adjacent MOSFETs.

Abstract: A semiconductor memory device comprises a memory cell array. The memory cell array comprises a plurality of first wiring lines, a plurality of second wiring lines extending crossing the first wiring lines, and a plurality of memory cells disposed at intersections of the first and second wiring lines. The memory cells are stacked in a direction perpendicular to a substrate, and each memory cell comprises a variable resistance element. The semiconductor memory device also includes a select transistor layer comprising a plurality of select transistors, each select transistor being operative to select any one of the first wiring lines or one of the second wiring lines. Two select transistors are connected to two different respective first wiring lines, stacked in a direction perpendicular to the substrate, and configured to share one gate electrode.

Abstract: A dual channel transistor includes a semiconductor island isolated by a first shallow trench isolation (STI) extending along a first direction and a second STI extending along a second direction, wherein the first direction intersect the second direction. The dual channel transistor further includes a gate trench recessed into the semiconductor island and extending along the second direction. A gate is located in the gate trench. A first U-shaped channel region is formed in the semiconductor island. A second U-shaped channel region is formed in the semiconductor island, wherein the second U-shaped channel region is segregate from the first U-shaped channel region by the gate. During operation, the gate controls two U-shaped channel regions simultaneously.

Abstract: An integrated circuit includes four electronic components, a buried UTBOX layer under and plumb with the electronic components, and two pairs of oppositely doped ground planes plumb with corresponding components under the layer. A first isolation trench mutually isolates the ground planes from corresponding wells made plumb and in contact with the ground planes and exhibiting the first doping type. Bias electrodes contact respective wells and ground planes. One pair of electrodes is for connecting to a first bias voltage and the other pair is for connecting to a second bias voltage. Also included are a semiconductor substrate exhibiting the first type of doping and a deeply buried well exhibiting the second type of doping. The deeply buried well contacts the other wells and separates them from the substrate. Finally, a control electrode couples to the deeply buried well.

Abstract: A complementary fin field-effect transistor (FinFET) includes a p-type device having a p-channel fin. The p-channel fin may include a first material that is lattice mismatched relative to a semiconductor substrate. The first material may have a compressive strain. The FinFET device also includes an n-type device having an re-channel fin. The n-channel fin may include a second material having a tensile strain that is lattice mismatched relative to the semiconductor substrate. The p-type device and the n-type device cooperate to form the complementary FinFET device.

Abstract: A field effect device comprises a substrate of semiconductor on insulator type successively provided with a support substrate, an electrically insulating layer and a semiconductor material film. First and second source/drain electrodes are formed in the semiconductor material layer. A conduction channel is formed in the semiconductor material layer and separates the first and second source/drain electrodes. A counter-electrode is formed in the support substrate and faces the first and second source/drain electrodes and the conduction channel. The counter-electrode is formed by a doped area of the support substrate having a first doping impurity concentration which decreases from an interface between the electrically insulating layer and the support substrate.

Abstract: A semiconductor substrate includes a substrate, an insulating layer, and a semiconductor layer. The insulating layer is over and in contact with the substrate. The insulating layer includes at least one of an amorphous metal oxide and an amorphous metal nitride. The semiconductor layer is over and in contact with the insulating layer. The semiconductor layer is formed by crystal growth.

Abstract: A new type of Metal Oxide Semiconductor (MOS) transistor that works on the basis of the Quantum Interference Depression (QID) effect is disclosed. QID occurs inside an n-type semiconductor source-drain electrode of special geometry. Due to QID the Fermi level of said semiconductor increases locally inside the source drain electrode, thereby creating a localized potential energy barrier in the path of electrons moving from source to drain regions. The height of the barrier depends on the degree of QID. QID is in turn regulated by the gate voltage via the charge depletion and hence change in effective dimensions of the special geometry of the semiconductor electrode. A gate voltage modulated potential energy barrier and is thus formed whereby current in said MOS transistor is controlled.

Abstract: A method and apparatus for forming a CMOS device are provided. The CMOS device may include an N-type channel region formed of an III-V material and a P-type channel region formed of a germanium material. Over each channel may be formed corresponding gates and source/drain regions. The source/drain regions may be formed of a germanium material and one or more metallization layers. An anneal may be performed to form ohmic contacts for the source/drain regions. Openings may be formed in a dielectric layer covering the device and conductive plugs may be formed to provide contact to the source/drain regions.

Abstract: Directed self-assembly (DSA) material, or di-block co-polymer, to pattern features that ultimately define a channel region a gate electrode of a vertical nanowire transistor, potentially based on one lithographic operation. In embodiments, DSA material is confined within a guide opening patterned using convention lithography. In embodiments, channel regions and gate electrode materials are aligned to edges of segregated regions within the DSA material.

Abstract: Embodiments of the present invention provide an improved structure and method for forming CMOS field effect transistors. In embodiments, silicon germanium (SiGe) is formed on a PFET side of a semiconductor structure, while silicon is disposed on an NFET side of a semiconductor structure. A narrow isolation region is formed between the PFET and NFET. The NFET fins are comprised of silicon and the PFET fins are comprised of silicon germanium.

Abstract: A semiconductor device includes a first planar semiconductor (e.g., silicon) layer, first and second pillar-shaped semiconductor (e.g., silicon) layers, a first gate insulating film, a first gate electrode, a second gate insulating film, a second gate electrode, a first gate line connected to the first and second gate electrodes, a first n-type diffusion layer, a second n-type diffusion layer, a first p-type diffusion layer, and a second p-type diffusion layer. A center line extending along the first gate line is offset by a first predetermined amount from a line connecting a center of the first pillar-shaped semiconductor layer and a center of the second pillar-shaped semiconductor layer.

Abstract: A semiconductor device includes a first planar semiconductor (e.g., silicon) layer, first and second pillar-shaped semiconductor (e.g., silicon) layers, a first gate insulating film, a first gate electrode, a second gate insulating film, a second gate electrode, a first gate line connected to the first and second gate electrodes, a first n-type diffusion layer, a second n-type diffusion layer, a first p-type diffusion layer, and a second p-type diffusion layer. A center line extending along the first gate line is offset by a first predetermined amount from a line connecting a center of the first pillar-shaped semiconductor layer and a center of the second pillar-shaped semiconductor layer.

Abstract: The present invention relates to a floating body memory cell comprising: a first MOS transistor and a second MOS transistor, wherein at least the second MOS transistor has a floating body; and wherein the first and second MOS transistors are configured such that charges can be moved to/from the floating body of the second MOS transistor via the first MOS transistor.

Abstract: An apparatus and a method for creating a CMOS with a dual raised source and drain for NMOS and PMOS. The spacers on both stack gates are of equal thickness. In this method, a first insulating layer is formed on the surface. The first region is then masked while the other region has the first layer etched away and has an epitaxial source and drain grown on the region. A second layer is formed to all exposed surfaces. The second region is then masked while the first region is etched away. The epitaxial source and drain is formed on the first region. The second region can also be masked by adding a thin layer of undoped silicon and then oxidize it. Another way to mask the second region is to use a hard mask. Another way to form the second source and drain is to use amorphous material.

Abstract: A semiconductor device includes a p-type metal oxide semiconductor device (PMOS) and an n-type metal oxide semiconductor device (NMOS) disposed over a substrate. The PMOS has a first gate structure located on the substrate, a carbon doped n-type well disposed under the first gate structure, a first channel region disposed in the carbon doped n-type well, and activated first source/drain regions disposed on opposite sides of the first channel region. The NMOS has a second gate structure located on the substrate, a carbon doped p-type well disposed under the second gate structure, a second channel region disposed in the carbon doped p-type well, and activated second source/drain regions disposed on opposite sides of the second channel region.

Abstract: A multilayer semiconductor device structure having different circuit functions on different semiconductor device layers is provided. The semiconductor structure comprises a first semiconductor device layer fabricated on a bulk substrate. The first semiconductor device layer comprises a first semiconductor device for performing a first circuit function. The first semiconductor device layer includes a patterned top surface of different materials. The semiconductor structure further comprises a second semiconductor device layer fabricated on a semiconductor-on-insulator (“SOI”) substrate. The second semiconductor device layer comprises a second semiconductor device for performing a second circuit function. The second circuit function is different from the first circuit function. A bonding surface coupled between the patterned top surface of the first semiconductor device layer and a bottom surface of the SOI substrate is included.

Abstract: A semiconductor device with an SRAM memory cell having improved characteristics. Below an active region in which a driver transistor including a SRAM is placed, an n type back gate region surrounded by an element isolation region is provided via an insulating layer. It is coupled to the gate electrode of the driver transistor. A p well region is provided below the n type back gate region and at least partially extends to a position deeper than the element isolation region. It is fixed at a grounding potential. Such a configuration makes it possible to control the threshold potential of the transistor to be high when the transistor is ON and to be low when the transistor is OFF; and control so as not to apply a forward bias to the PN junction between the p well region and the n type back gate region.

Abstract: A semiconductor structure having multiple semiconductor-device layers is provided. The semiconductor structure comprises a first buried oxide and a first semiconductor device layer fabricated above the first buried oxide. The first semiconductor device layer comprises a patterned top surface. A blanket layer comprising insulator material is fabricated over the patterned surface. The semiconductor structure further comprises a second buried oxide bonded to the blanket layer and a second semiconductor device layer fabricated above the second buried oxide.

Abstract: Fabrication methods are disclosed that facilitate the production of electronic structures that are both flexible and stretchable to conform to non-planar (e.g. curved) surfaces without suffering functional damage due to excessive strain. Electronic structures including CMOS devices are provided that can be stretched or squeezed within acceptable limits without failing or breaking. The methods disclosed herein further facilitate the production of flexible, stretchable electronic structures having multiple levels of intra-chip connectors. Such connectors are formed through deposition and photolithographic patterning (back end of the line processing) and can be released following transfer of the electronic structures to flexible substrates.

Abstract: A multilayer semiconductor device structure comprising a first buried oxide and a first semiconductor device layer fabricated above the first buried oxide is provided. The first semiconductor device layer comprises a patterned top surface. The patterned surface comprises insulator material and conductor material. The surface density of the insulator material is greater than 40 percent. The multilayer semiconductor device structure further comprises a second buried oxide bonded to the patterned surface of the first semiconductor device layer and a second semiconductor device layer fabricated above the second buried oxide.

Abstract: An integrated circuit includes an NMOS transistor and a PMOS transistor on different regions of an SOT substrate. Each transistor includes a gate region, multilayer lateral insulating regions against the sides of the gate region while also on the substrate. Each multilayer lateral insulating region includes an inclined portion sloping away from the substrate. Source and drain regions are on the substrate and are separated from the sides of the gate region by the corresponding multilayer lateral insulating region. The source and drain regions have an inclined portion resting against the inclined portion of the the lateral insulating region.

Abstract: A multilayer semiconductor structure having a layout footprint with a first region and a non-overlapping second region and different transistor types fabricated using different channel material. The semiconductor structure comprises a first transistor layer comprising a first type of channel material in the first region but no channel material in the second region. The semiconductor structure further comprises a second transistor layer comprising a second type of channel material in the second region but no channel material in the first region. The second transistor layer is vertically elevated above the first transistor layer. A first transistor is fabricated on the first transistor layer. A second transistor is fabricated on the second transistor layer, and the first transistor is interconnected with the second transistor to form a circuit.

Abstract: A shallow trench isolation structure containing a first shallow trench isolation portion comprising the first shallow trench material and a second shallow trench isolation portion comprising the second shallow trench material is provided. A first biaxial stress on at least one first active area and a second bidirectional stress on at least one second active area are manipulated separately to enhance charge carrier mobility in middle portions of the at least one first and second active areas by selection of the first and second shallow trench materials as well as adjusting the type of the shallow trench isolation material that each portion of the at least one first active area and the at least one second active area laterally abut.

Abstract: In an n-channel HK/MG transistor including: a gate insulating film made of a first high dielectric film containing La and Hf; and a gate electrode which is formed of a stacked film of a metal film and a polycrystalline Si film and which is formed in an active region in a main surface of a semiconductor substrate and surrounded by an element separation portion formed of an insulating film containing oxygen atoms, a second high dielectric film which contains Hf but whose La content is smaller than a La content of the first high dielectric film is formed below the gate electrode which rides on the element separation portion, instead of the first high dielectric film.

Abstract: A method for making a semiconductor device may include forming, on a first semiconductor layer of a semiconductor-on-insulator (SOI) wafer, a second semiconductor layer comprising a second semiconductor material different than a first semiconductor material of the first semiconductor layer. The method may further include performing a thermal treatment in a non-oxidizing atmosphere to diffuse the second semiconductor material into the first semiconductor layer, and removing the second semiconductor layer.

Abstract: A method for making a semiconductor device includes forming a buried oxide stack on a semiconductor wafer. The buried oxide stack includes a first oxide layer, a nitride layer on the first oxide layer, and a second oxide layer on the nitride layer. A semiconductor layer is formed on the second oxide layer. First and second channel regions are formed in the semiconductor layer.

Abstract: A method for preparing a multilayer substrate includes the step of deposing an epitaxial ?-Al2O3 Miller index (001) layer on a Si Miller index (001) substrate.

Abstract: An embodiment method of controlling fin bending in a fin field-effect transistor (FinFET) includes forming an isolation region over a substrate, performing a first annealing process, the first annealing process including a first wet anneal, the first wet anneal removing impurities from the isolation region; a second wet anneal, the second wet anneal forming silanol in the isolation region; and a first dry anneal, the first dry anneal dehydrating the isolation region. In an embodiment, the first annealing process is followed by a chemical mechanical planarization (CMP) process, an etching process, and a second annealing process for the isolation region.

Abstract: A multi-gate semiconductor device is formed including a semiconductor substrate. The multi-gate semiconductor device also includes a first transistor including a first fin portion extending above the semiconductor substrate. The first transistor has a first channel region formed therein. The first channel region includes a first channel region portion doped at a first concentration of a first dopant type and a second channel region portion doped at a second concentration of the first dopant type. The second concentration is higher than the first concentration. The first transistor further includes a first gate electrode layer formed over the first channel region. The first gate electrode layer may be of a second dopant type. The first dopant type may be N-type and the second dopant type may be P-type. The second channel region portion may be formed over the first channel region portion.

Abstract: High voltage three-dimensional devices having dielectric liners and methods of forming high voltage three-dimensional devices having dielectric liners are described. For example, a semiconductor structure includes a first fin active region and a second fin active region disposed above a substrate. A first gate structure is disposed above a top surface of, and along sidewalls of, the first fin active region. The first gate structure includes a first gate dielectric composed of a first dielectric layer disposed on the first fin active region, and a second, different, dielectric layer disposed on the first dielectric layer. The semiconductor structure also includes a second gate structure disposed above a top surface of, and along sidewalls of, the second fin active region. The second gate structure includes a second gate dielectric composed of the second dielectric layer disposed on the second fin active region.

Abstract: A semiconductor device and method of making the same are provided. The method of forming semiconductor device uses non-implant process to form doped layers, and thus is applicable for large-size display panel. The method of forming semiconductor device uses annealing process to reduce the resistance of the doped layers, which improves the electrical property of the semiconductor device. A first dielectric layer of the semiconductor device is able to protect a semiconductor layer disposed in a first region of the substrate from being damaged during the process, and an etching stop layer of the semiconductor device is able to protect the semiconductor layer disposed in a second region of the substrate from being damaged when defining second doped layers. The first dielectric layer and the etching stop layer are formed by the same patterned dielectric layer, thus no extra process is required, fabrication cost is reduced, and yield is increased.

Abstract: First and second template epitaxial semiconductor material portions including different semiconductor materials are formed within a dielectric template material layer on a single crystalline substrate. Heteroepitaxy is performed to form first and second epitaxial semiconductor portions on the first and second template epitaxial semiconductor material portions, respectively. At least one dielectric bonding material layer is deposited, and a handle substrate is bonded to the at least one dielectric bonding material layer. The single crystalline substrate, the dielectric template material layer, and the first and second template epitaxial semiconductor material portions are subsequently removed. Elemental semiconductor devices and compound semiconductor devices can be formed on the first and second semiconductor portions, which are embedded within the at least one dielectric bonding material layer on the handle substrate.

Abstract: The invention relates to a semiconductor device and a method for manufacturing such a semiconductor device. A semiconductor device according to an embodiment of the invention comprises: a substrate which comprises a base layer, an insulating layer on the base layer, and a semiconductor layer on the insulating layer; and a first transistor and a second transistor formed on the substrate, the first and second transistors being isolated from each other by a trench isolation structure formed in the substrate. Wherein at least a part of the base layer under at least one of the first and second transistors is strained, and the strained part of the base layer is adjacent to the insulating layer. The semiconductor device according to the invention increases the speed of the device and thus improves the performance of the device.

Abstract: An integrated circuit includes a stack having a semiconductor substrate with a first type of dopant, an UTBOX type buried insulating layer, electronic components, formed in the substrate, ground planes disposed beneath the buried insulating layer so as to be respectively plumb with corresponding components, wells with the first type of dopant, the wells being respectively beneath corresponding ground planes, and a bias circuit enabling distinct voltages to be applied to the ground planes by the wells. The wells are separated from the substrate by a deep well with a second type of dopant. The wells are separated from each other by a separating structure, which is either a lateral well having a second type of dopant or a block of insulating material.

Abstract: An efficient strain-inducing mechanism may be provided on the basis of a piezoelectric material so that performance of different transistor types may be enhanced by applying a single concept. For example, a piezoelectric material may be provided below the active region of different transistor types and may be appropriately connected to a voltage source so as to obtain a desired type of strain.

Abstract: A semiconductor device includes an n channel conductivity type FET having a channel formation region formed in a first region on a main surface of a semiconductor substrate and a p channel conductivity type FET having a channel formation region formed in a second region of the main surface, which second region is different from the first region. An impurity concentration of a gate electrode of the n channel FET has an impurity concentration greater than an impurity concentration of the gate electrode of the p channel FET to thereby create a tensile stress in the direction of flow of a drain current in the channel forming region of the n channel FET. The tensile stress in the flow direction of the drain current in the channel forming region of the n channel FET is greater than a tensile stress in the direction of flow of a drain current in the channel forming region of the p channel FET.