Abstract: A method is disclosed which produces a high voltage MOS transistor with a deep retrograde N-well region, which includes a buried layer, said deep retrograde well region acting to increase the breakdown voltage of the MOS transistor and reduce the current gain of the inherent parasitic bipolar transistor. To achieve a high degree of control over the impurity concentration of the buried layer without affecting the impurity concentration in the N-well region, two dopants species are diffused or implanted in the N+ buried layer: one, a slow diffusing dopant, such as antimony or arsenic, and the other, a more rapidly diffusing dopant, such as phosphorus. A P- type epitaxial layer is grown over the buried layer and an N-well is formed in the epitaxial layer over the buried layer.

Abstract: According to the present invention, a control gate is formed on an n-type Si substrate, and a p-type source-drain region is formed in the surface of the substrate on both the sides of the control gate. A p-type Si.sub.x Ge.sub.1-x (0.ltoreq.x<1) layer and an Al electrode are sequentially formed in the source-drain region. The energy difference between the valence band of the SiGe layer and a vacuum level is smaller than the energy difference between the valence band of an Si layer constituting the source-drain region and the vacuum level, and the energy difference of the conduction band of the SiGe layer and the vacuum level is larger than the energy difference of the conduction band of the Si layer and the vacuum level. For this reason, a Schottky barrier height is decreased, and resistances between the semiconductor layers and the Al electrode are reduced.

Abstract: A semiconductor integrated circuit device having a structure in which each of the following regions, that is, a first region for forming the base and emitter regions of each of the bipolar transistors, a second region for forming the collector lead-out region of the bipolar transistor, and a third region for forming each of the MISFETs, is projected from the main surface of a semiconductor substrate, whereby it is possible to effect isolation between the MISFETs and between these MISFETs and the bipolar transistors with the same isolation structure and in the same manufacturing step as those for the isolation between the bipolar transistors. In this device, furthermore, the base region of the bipolar transistor is electrically and self-alignedly connected to a base electrode which is formed over the main surface so as to surround the emitter region.

Abstract: The BiMOS devices are compact 3D devices having a coupled bipolar and MOS mechanisms integrated in one single cell. The gates cover over the bipolar regions. The bipolar regions are the tubs of the MOS mechanisms. The MOS mechanisms make the connection between the base, emitter and collector to charge and discharge the base voltage. The input applies on the gate to switch on/off the base current of the bipolar mechanism. There are P-PNP, N-NPN, N-PNP, P-NPN, PN-PNP, PN-NPN, NP-PNP and NP-NPN BiMOS devices. The BiMOS inverter, NOR, NAND logic gates are the single stage circuit having the same circuit configuration as CMOS circuits. They are made of P-PNP, N-NPN, NP-PNP and NP-NPN BiMOS devices. The digital BiMOS buffer, OR, AND logic gates are the single stage circuits made of N-PNP, P-NPN, PN-PNP and PN-NPN BiMOS devices. Furthermore, the BiMOS technologies are applied to SRAM, EPROM and EEPROM to generate the BiMOS SRAM, BiMOS EPROM and BiMOS EEPROM memory devices.

Abstract: For providing a semiconductor integrated circuit device including CCD type, bipolar type and MOS type integrated circuits in only one chip, island-shaped epitaxial layers of opposite conductivity type are disposed in a semiconductor substrate of one conductivity type having a low impurity concentration. A field oxide layer is provided so as to surround a periphery of an exposed surface of each epitaxial layer. A buried layer of opposite conductivity type having a high impurity concentration is is interposed between the semiconductor substrate and each epitaxial layer in such a manner that at least one edge thereof terminates to the lower surfaace of the field oxide layer. The CCD type integrated circuit is provided in the semiconductor substrate, and the bipolar type and MOS type integrated circuits are arranged in the epitaxial layers.

Abstract: A first polysilicon layer (18) is initially deposited onto a layer of field oxide (16). A dielectric (26) is formed on a portion of the first polysilicon layer (18). A second polysilicon layer (28) is deposited over the dielectric (26) and the first polysilicon layer (18). After the selective deposition of a mask (30) on to the second polysilicon layer (28), the polysilicon layers (18, 28) are anistropically etched to form a polysilicon to polysilicon capacitor (34) and a contact (36) of the capacitor (34). The dielectric (26) functions as an insulator for the capacitor (34) and as a barrier during anisotropic etching for protecting the underlying polysilicon layer (18).

Abstract: A BICMOS device and manufacturing method wherein the gates of PMOS and NMOS transistors are formed by forming a first polysilicon layer which is not implanted by an impurity and forming a second polysilicon layer on the first polysilicon layer which is impurity implanted, so that the impurity doped in the second polysilicon layer is prevented from diffusing into the channel region and the voltage characteristic is prevented from changing. Emitter regions of vertical PNP and NPN bipolar transistors are self-aligned in a small chip area, and thereby the performance of the BICMOS device is improved due to the stable threshold voltage characteristic of the PMOS and NMOS transistors and high density is achieved together with improved operation speed clue to the self-alignment formation of the emitter region of the vertical PNP and NPN bipolar transistors.

Abstract: A semiconductor device having a semiconductor substrate of a first conductivity type, an epitaxial layer of a second conductivity type formed on a major surface of the semiconductor subtrate, an isolation layer of the first conductivity type formed in the epitaxial layer and extending from a surface thereof to the major surface of the semiconductor substrate. The isolation layer divides the epitaxial layer into first, second, and third islands. The device further has two wells of the first conductivity type, formed in the first and second islands, respectively, and extending to the substrate, a charge transfer device having a back gate formed of the first well, an insulated-gate FET of the first conductivity type, having a back gate formed of the second island, an insulated-gate FET of the second conductivity type, having a back gate formed of the second well, and a bipolar transistor having a collector formed of the third island.

Abstract: A method for forming a BICMOS integrated circuit having MOS field-effect devices and bipolar junction transistors formed in a silicon substrate is disclosed. The process comprises the steps of first defining separate active areas in a substrate for each of the transistors. Next, a gate dielectric layer is formed over the surface of the wafer. Above the gate dielectric, a first layer of polysilicon is deposited. This first layer of polysilicon is then selectively etched to form a plurality of first polysilicon members each of which is equally-spaced apart from one another. The polysilicon members comprise the gates of the MOS transistors and the extrinsic base contacts of the NPN transistors. After the first polysilicon members have been defined, the base regions of the NPN transistors are formed. After insulating the first polysilicon members, an additional layer of polysilicon is deposited over the substrate to replanarize the entire wafer surface.

Abstract: An integrated circuit device of a first N-type epitaxial layer over a substrate, a second P-type epitaxial layer over the first epitaxial layer, and a third N-type epitaxial layer over the second epitaxial layer, with a P-type buried ground region formed in a portion of the substrate, the ground region extending from the substrate to the third epitaxial layer in a first tank region and extending through the first and second epitaxial layers. A power bipolar transistor is formed in the first tank region. P isolation areas extending from the surface of the third epitaxial layer to the P ground region isolate the bipolar transistor from other tank region on the same substrate in which N and P channel MOSFETS are formed.

Abstract: Herein disclosed is a bipolar-CMOS semiconductor circuit having a semiconductor substrate, an N.sup.- epitaxial layer formed on the semiconductor substrate, an N well formed in the N.sup.- epitaxial layer, a P well formed in the N.sup.- epitaxial layer, a power supply terminal to which the positive potential is to be supplied, a ground potential terminal, an input terminal, an output terminal, an NPN bipolar transistor formed in the N.sup.- epitaxial layer, the NPN bipolar transistor having the N.sup.- epitaxial layer as the collector thereof and having an emitter connected to the output terminal, a P-channel type MOS transistor formed in the N well and being connected between the power supply terminal and the base of the NPN bipolar transistor, the gate of the P-channel type MOS transistor being connected to the input terminal, and both the N well for the P-channel type MOS transistor and the N.sup.

Abstract: A monolithic complementary semiconductor device comprising n-type and p-type well regions separated by a dielectric isolation region extending from the surface into the substrate region. The well region includes a highly doped buried region which is located at the bottom of the well region and separates an active region in the wall from the substrate region. The isolation region is deeper than the buried region. The well-to-well isolation is enhanced by the combination of the buried region and the deep dielectric isolation region. Packing density and the high speed operation can also be improved.