Abstract: A semiconductor device, more particularly, an intelligent power integrated circuit formed on a substrate where a power device and a control device are formed is provided. The intelligent power integrated circuit includes a handling substrate for a first conductivity type, a substrate for a power device of a second conductivity type where a first buffer layer of a concentration higher than that of the substrate for the power device is formed around a surface contacting with the handling substrate, a substrate for a control device formed on an insulating layer partially formed on the substrate for the power device, a control device formed on the substrate for the control device, and a power device vertically formed through the substrate for the power device and the handling substrate.

Abstract: A semiconductor structure (10) having device isolation structures (43, 44) and shielding structures (39, 40). The shielding structures (39, 40) are formed in a semiconductor material (11) and the device isolation structures (43, 44) are formed within the corresponding shielding structures (39, 40). A noise generating device is formed within a first shielding structure (43) and a noise sensitive device is formed within a second shielding structure (44). The two shielding structures (39, 40) are grounded and prevent noise from the noise generating device from interfering with the noise sensitive device.

Abstract: An inexpensive semiconductor device in which an insulated gate bipolar transistor and a terminal, capable of drawing out a limited current or voltage from a collector of the insulated gate bipolar transistor, are mounted on a semiconductor substrate, and a semiconductor circuit using the same. The semiconductor device comprising an insulated gate bipolar transistor having a gate formed through a gate insulator on an n-type semiconductor layer formed on a p-type semiconductor substrate, and a thyristor, the thyrister comprising a p-type region where a p-type impurity diffuses over a part of the n-type semiconductor layer, an n-type region where an n-type impurity diffuses over a part of the p-type region, an emitter electrode formed contiguously to the n-type region, a base electrode formed contiguously to the p-type region, and a collector electrode which is used in common with the insulated gate bipolar transistor.

Abstract: A semiconductor device with a reduced insulating capacitance between an emitter electrode and a base layer, and a manufacturing method thereof are disclosed. In the semiconductor device, at least first and second insulating layers are interposed between the emitter electrode and the base layer. Preferably, the first insulating layer, a semiconductor layer having insulation characteristics, and the second insulating layer are interposed between the emitter electrode and the base layer.

Abstract: Disclosed is a semiconductor device, such as a semiconductor memory device, having structure wherein invasion of minority carriers from the semiconductor substrate into components of the device, formed on the substrate, can be avoided. The semiconductor memory device can be an SRAM or DRAM, for example, and includes a memory array and peripheral circuit on a substrate. In one aspect of the present invention, a buried layer of the same conductivity type as that of the substrate, but with a higher impurity concentration than that of the substrate, is provided beneath at least one of the peripheral circuit and memory array. A further region can extend from the buried layer, for example, to the surface of the semiconductor substrate, the buried layer and further region in combination acting as a shield to prevent minority carriers from penetrating to the device elements.

Abstract: A BiCMOS structure and a method for making the same is disclosed, where the dielectric layer between the emitter electrode and the base region is formed of a deposited dielectric. After definition of the bipolar and MOS moat regions, a layer of polysilicon is deposited thereover, and removed from the bipolar region. The base implant is performed either prior to or after the etch of the polysilicon layer. A layer of TEOS oxide is formed thereover and is etched to remain in portions of the bipolar region, with an emitter contact formed therethrough and a portion of the bipolar region exposed at which the extrinsic base is formed. An alternative embodiment of the invention includes scaling the emitter contact by forming sidewall oxide filaments therewithin. A second layer of polysilicon is disposed thereover to form the emitter electrode, and to merge with the first layer to form the gates of the MOS transistors.

Abstract: The structure in this present invention includes a substrate having a buried-in oxide layer near the surface of the substrate and a silicon surface layer of base over the buried-in oxide layer. After that the structure further includes a conductive layer of gate on the substrate, a dielectric layer on the conductive layer of gate, a metal plug penetrates through the conductive layer and the dielectric layer and reach down to the silicon surface layer but not through. The metal plug, the conductive layer of gate and the silicon surface of base are electrically coupled together.

Abstract: A CMOS arrangement is described which has at least one NMOS region (2) and at least one PMOS region (3) and which is provided at its surface with substrate contacts (24, 34), via which it is possible to apply predetermined voltage values to respective substrate sections (1, 30) of the CMOS arrangement. The CMOS arrangement described is distinguished by the fact that the average number of substrate contacts (24, 34) per unit area and/or the average substrate contact area per unit area within the at least one NMOS region (2) is significantly smaller than within the at least one PMOS region (3).

Abstract: A Bi-CMOS semiconductor device having a CMOS device region and a bipolar transistor region is provided wherein the bipolar transistor has a collector region of a first conductivity type and the CMOS region has at least one element region of a second conductivity type which is positioned adjacent to the collector region as well as wherein a single buried layer of the first conductivity type is provided which extends under the element region of the CMOS region and the collector region.

Abstract: A semiconductor component having a control structure for modulating the conductivity of a channel region wherein a small-area gate electrode of the proposed component covers the substrate only over a length L.sub.gd .apprxeq.L.sub.dep (L.sub.dep :=width of the space-charge zone in the substrate). An auxiliary electrode conductively connected to the source metallization and extending up to the edge of the symmetry unit is embedded in the gate oxide and is arranged spaced from the gate electrode. It sees to a comparatively uniform field distribution in the edge region of the gate electrode and thus prevents the electrical field strength in the semiconductor from reaching the critical value of approximately 10.sup.5 V/cm that triggers surge ionization.

Abstract: A semiconductor device is provided in its base region with an emitter region consisting of a p-type first impurity layer having a first impurity concentration peak at a first depth and a p-type second impurity layer having an impurity concentration peak at a second depth, and ohmic contact is provided in the p-type second impurity layer. Due to this structure, the operability of an SRAM memory cell defining an emitter region of a bipolar transistor by a source/drain region of a MOS transistor can be improved.

Abstract: A bipolar transistor has a semiconductor region of a first conductivity type. A collector region of the first conductivity type and a base region of a second conductivity type are disposed within the semiconductor region. An emitter region of the first conductivity type and a base electrode region of the second conductivity type are disposed within a surface of the base region in self-alignment arrangement. At least one polycrystalline silicon layer is disposed on the entire surface of the base region except for portions of the surface of the base region overlying the emitter region and the base electrode region.

Abstract: An improved bipolar transistor (202) has an increased Early voltage and can be integrated on a semiconductor die with MOS transistors (201) and other types of devices to form an integrated circuit (200). A p-type base region (240) is disposed in an n-type collector region (252). An n-type emitter region (244) is disposed within the base region, and a p-type enhancement region (250) is formed to extend under the emitter region to a depth greater than the base depth. The improved bipolar transistor can be fabricated without significantly affecting the operation of other devices on the integrated circuit.

Abstract: A semiconductor device includes a semiconductor layer used as a substrate formed on an insulating film, a plurality of MOS transistors arranged on the semiconductor layer and each having a gate, a source, and a drain, a pair of MOS transistors of the plurality of MOS transistors constituting a detection circuit for detecting magnitudes of potentials applied to the gates as a difference between conductances of the pair of transistors, and a diffusion layer region of the same conductivity type as that of the semiconductor layer, arranged on one of portions of the sources and drains of the pair of MOS transistors constituting the detection circuit, for connecting portions serving as the substrates of the pair of MOS transistors to each other.

Abstract: An improved method for simultaneously forming low voltage and high voltage devices is disclosed. The method includes using gradient doping to generate the gradient concentration in a semiconductor such that can tolerate higher threshold voltage. The device can get higher driving current by using gradient doping only in drain regions in metal-oxide-semiconductor field effect transistor (MOSFET). In addition, the invention can simultaneously generate higher current gain bipolar junction transistor (BJT) for applied integrated circuit. Further more, the invention can meet small layout rule of low voltage device and the only drain region to be operated in a high voltage device.

Abstract: An N-type buried diffusion layer as a portion of the collector region of a bipolar transistor and an N-type buried diffusion layer of a memory cell region are simultaneously formed, and the buried diffusion layer of the memory cell region serves as a potential groove for electrons. The threshold voltage of a MOS transistor in the memory cell region is higher than the threshold voltage of a MOS transistor in a peripheral circuit region, preventing an increase in the standby current in the memory cell region. This increases the soft error resistance of the memory cell and prevents a decrease in the operating speed and an increase in the consumption power.

Abstract: A dynamic threshold voltage MOSFET to provide increase drain-to-source saturation current (I.sub.DSsat) and lower off current (I.sub.off) is described. The dynamic threshold voltage MOSFET has a first diffusion-well of a material of a first conductivity type formed at the surface of the substrate to form a bulk region. A source region and a drain region of a material of a second conductivity type are diffused into the diffusion-well. A first gate is then placed on a first oxide surface above the substrate between the source and drain regions. An accumulated base bipolar transistor is then placed on the semiconductor substrate. The base of the accumulated base bipolar transistor is connected to the gate, the emitter is connected to the diffusion-well. A resistor is connected between the emitter of the accumulated base bipolar transistor and a substrate biasing voltage source.

Abstract: A method of forming an intermediate semiconductor structure as part of a BiCMOS process to provide for improved anti-punch-through (APT) protection and improved threshold-voltage (Vt) adjustment for the MOS devices of the structure. The method includes the fabrication of a split polysilicon layer and the introduction of APT and Vt related carriers after formation of the gate oxide layer. The intermediate structure includes the gate oxide layer and a protective amorphous silicon layer formed on the surface of the gate oxide layer in an in situ process. The protective amorphous structure is formed to protect the integrity of the gate oxide layer during subsequent acid washes associated with the BiCMOS process. The amorphous layer may be deposited in a thickness substantially less than that associated with prior spilt polycrystalline silicon processes. This allows for introduction of the APT and Vt related carriers using relatively standard implanting equipment.

Abstract: A method for forming bipolar junction transistor with high gain via formulation of high voltage device in deep submicron process is disclosed. A substrate including a first part, a second part, and a third part is primarily provided; then, a first well in the first part and a second well in the second part are formed. A plurality of field oxide regions are formed on said substrate; subsequently, two third wells are formed in said third part. The following steps are to form a fourth well in said first well in said first part and two fifth wells in said second well in said second part; and to form a first gate on said first part between said two third wells, and a second gate on said second part between said two fifth wells. Next, a first spacer against said first gate and a second spacer against said second gate are formed. Further, first ions are introduced into said first part to serve as a collector region, and into said third part to serve as a first source/drain region.

Abstract: Wells of a semiconductor device suitable for achieving high integration, and a method for forming the same are disclosed. The wells of a semiconductor device include a first conductivity type semiconductor substrate where a cell region and a periphery region are defined, a second conductivity type shield region in the entire cell region and in the entire periphery region at a depth below surface of the semiconductor substrate, a first conductivity type well on the second conductivity type shield region beneath the surface of the semiconductor substrate, a second conductivity type shield sidewall formed in the second conductivity type shield region and the first conductivity type well at border of the cell and periphery regions, a first conductivity type buried region formed at the second conductivity type shield region in the periphery region, and a second conductivity type well on the first conductivity type buried region in the first conductivity type well.

Abstract: An improved circuit and method for gate-body transistors is provided. The improved circuit and method can accord a faster switching speed and low power consumption. The present invention capitalizes on opposing sidewalls and adjacent conductive sidewall members to conserve available surface space on the semiconductor chips. The gate and body of the transistors are biased to modify the threshold voltage of the transistor (V.sub.t). Additionally, the conductive sidewall members and a gate are biased from a single source. The structure offers performance advantages from both metal-oxide semiconductor (MOS) and bipolar junction transistor (BJT) designs. The device can be used in a variety of applications, digital and analog, wherever a more compact structure with low power consumption and fast response time is needed.

Abstract: A bipolar transistor (3) is provided with a first main surface (4) in contact with a conductive mounting surface (2), and with an opposed second main surface (12) having connection pads (5, 6, 40) for an emitter, base, and collector. The lateral dimensions of the conductive mounting surface (2) are practically equal to the dimensions of the first main surface (4) of the transistor (3), and may thus be relatively small. The high-frequency properties of the transistor (3) are strongly determined by the size of the conductive mounting surface (2), which through an insulating substrate (1) forms a parasitic capacitance with a conductive ground surface (18), which capacitance is connected to the transistor (3). This parasitic capacitance is very important especially for high-frequency applications. Furthermore, the bonding wires (E, B) for the connection pads of emitter and base are shorter than in the prior art because they need not pass over a relatively large conductive mounting surface (2).

Abstract: A repeating cell structure in a semiconductor substrate for a BiCMOS logic gate array. The cell structure has three regions shaped as columns. The first columnar region is a P-well and has four vertically aligned active areas of N-type material formed within the columnar region. Each of the active areas has two gate electrodes to form two NMOS transistors. Similarly the second columnar region is a N-well and has four vertically aligned active areas of P-type material. Each such active region forms two PMOS transistors. The third column has two bipolar transistors, each with collector, base and emitter regions vertically aligned. The resulting BiCMOS logic array permits a flexible location of macrocells, which results in a compact implementation of the resulting integrated circuit.

Abstract: An integrated circuit using high-performance bipolar and CMOS transistor elements on a single chip is fabricated by a simplified process requiring minimal, if any, changes in the process used for forming either type of device in accordance with a variety of possible device designs. The method according to the invention makes maximal use of self-aligned and self-masking processes to reduce the number of processing steps. The number of processing steps is further reduced by performing some steps concurrently on different device types. Further, the masking steps which are employed are reasonably misregistration tolerant, resulting in high manufacturing yield for the process. Consequently, the process according to the invention substantially eliminates the existence of trade-offs between element performance, integration density and process complexity and cost when plural technologies are integrated on the same chip.

Abstract: A semiconductor flash memory device includes floating gate type field effect transistors serving as memory cells, field effect transistors for forming peripheral circuits and bipolar transistors for forming other peripheral circuits expected to drive heavy load at high speed, and both of the floating gate electrodes and the emitter electrodes and both of the control gate electrodes and the gate electrodes are patterned from a first doped polysilicon and a second doped polysilicon so as to simplify a process sequence for fabricating the semiconductor flash memory device.

Abstract: A circuit and method for an improved inverter is provided. The present invention capitalizes on opposing sidewalls and adjacent conductive sidewall members to conserve available surface space on the semiconductor chips. Additionally, the gate and body of the transistors are biased to modify the threshold voltage of the transistor (V.sub.t). The conductive sidewall member configuration conserves surface space and achieves a higher density of surface structures per chip. This design provides fast switching capability for low power battery operated CMOS circuits and systems. The transistor structure offers performance advantages from both metal-oxide semiconductor (MOS) and bipolar junction transistor (BJT) designs. The devices can be used in a variety of applications, digital and analog, wherever a more compact structure with low power consumption and fast response time is needed.

Abstract: A MOSFET wherein the formation of a channel in a channel formation region is controlled by a voltage applied to an insulated gate, comprising: a semiconductor substrate; a first semiconductor layer (drain region) of a first conductivity type formed on a surface of the semiconductor substrate; a second semiconductor layer (body region) of a second conductivity type provided within the first semiconductor layer, where a part thereof forms the channel formation region; a third semiconductor layer (source region) of the first conductivity type provided selectively in the second semiconductor layer; and a body contact region in electrical contact with the second semiconductor layer. The body contact region is formed in an area that is separated from an active region by a non-active region. With this structure, parasitic bipolar transistors operate simultaneously throughout the entire device so that a uniform breakdown current is generated, thus preventing element destruction due to current concentrations.

Abstract: A semiconductor layer is formed on a semiconductor substrate. A digital circuit region, in which a digital circuit is formed, and an analog circuit region, in which an analog circuit is formed, are separately formed by an isolation region at the surface of the semiconductor layer. At this time, a width of the semiconductor layer in the isolation region is greater than a thickness of the semiconductor substrate. Also, a region having high electrical resistance with low concentration of impurity is formed at the surface of the semiconductor substrate in the isolation region. Furthermore, conductive layers connected to a grounding potential is formed on the backside of the semiconductor substrate in the digital circuit region and on the backside of the semiconductor substrate of the analog region.

Abstract: An oxidation layer 44 for masking is formed on a PNP type transistor formation region 46a together with a field oxidation layer 42 for device separation. The oxidation layer 44 for masking is formed so as to cover an upper part of an active base formation region 52a located between the emitter/collector formation region 50a. The upper part of the active base formation region 52a which is not possible to adjust impurity concentration at processes carried out later is covered with the oxidation layer 44 for masking being formed relatively thick when boron B is implanted into a PMOS type transistor formation region 48a as channel ion. So that, boron is not implanted ionically to the active base formation region 52a. Therefore, it is not necessary to carry out masking process using photo resist layer in prior to boron implantation process.

Abstract: A semiconductor device having a substrate with a first conductivity type. The substrate has a top substrate region that also has the first conductivity type. A first doped region, a second doped region and a third doped region are located in the top substrate region where the first and second doped regions have a second conductivity type opposite the first conductivity type while the third doped region has the first conductivity type and where the third doped region is between the first and second doped regions. A doped well region is also in the top substrate region and has the second conductivity type and has the second doped region and at least a portion of the third doped region located therein. A method of forming the device is also provided herein.

Abstract: A BiCMOS integrated circuit is fabricated using a minimum number of wafer processing steps and yet offers the IC circuit designer five (5) different transistor types. These types include P-channel and N-channel MOS transistors and three different bipolar transistors whose emitters are all formed by a different process and all are characterized by different current gains and different breakdown voltages. A differential silicon dioxide/silicon nitride masking technique is used in the IC fabrication process wherein both P-type buried layers (PBL) and N-type buried layers (NBL) are formed in a silicon substrate using a single mask set and further wherein P-type wells and N-type wells are formed above these buried layers in an epitaxial layer, also using a single SiO.sub.2 /Si.sub.3 N.sub.4 differential mask set. Two of the bipolar transistor emitters are formed by out diffusion from first and second levels of polysilicon, whereas the emitter of the third bipolar transistor is formed by ion implantation doping.

Abstract: In a semiconductor integrated circuit device wherein a BiCMOS logical gate circuit and a CMOS logical gate circuit are used in combination, a lower power consumption than that of CMOS and a higher integration density than that of CMOS are realized without sacrificing the operating speed. The BiCMOS semiconductor integrated circuit device of the present invention is realized by logical function macros using the output portion, of logical function realized by a CMOS gate constituted by an MOS transistor having a gate width determined by the minimum value in the design criteria, as a BiCMOS buffer having a very small input capacity. In the BiCMOS buffer, the gate width of the MOS transistor, wherein a gate is connected to the input terminal, is set at a small value by incorporation of a base potential clamp circuit or the like.

Abstract: A semiconductor device comprises: a substrate; a first buried layer of a first conduction type formed in the substrate; a second buried layer of the first conduction type formed in the substrate; a third buried layer of the first conduction type formed in the substrate; an epitaxial layer of the first conduction type formed on the substrate; a well region of a second conduction type formed in the epitaxial layer above the third buried layer; source/drain regions of the first conduction type formed in the well region; a first base region of the second conduction type formed in the epitaxial layer above the first buried layer; a first impurity region of the first conduction type formed on the first base region; a second base region of the second conduction type formed in the epitaxial layer above the second buried layer; a second impurity region of the first conduction type formed on the second base region; a first lead-out layer of the first conduction type connected to the first buried layer; and a second lea

Abstract: A method for making an isolated NMOS transistor (10) in a BiCMOS process includes forming an N- conductivity type DUF layer (19) in a P conductivity type semiconductor substrate (12), followed by forming alternate contiguous N+ and P conductivity type buried regions (30,26) in the substrate (12). A layer of substantially intrinsic semiconductor material (32) is then formed on the substrate (12) in which alternate and contiguous N and P conductivity type wells (35,36) are formed, respectively above and extending to the N+ and P conductivity type buried regions (30,26). Finally, NMOS source and drain regions (48) are formed in at least one of the P conductivity type wells (35). The method is preferably performed concurrently with the construction of a bipolar transistor structure (11) elsewhere on the substrate (12).

Abstract: There is provided a method of fabricating a semiconductor device, including the steps of, in consequence, (a) partially forming a buried layer in a semiconductor substrate and also forming an epitaxial layer on the buried layer, (b) forming a collector region in the epitaxial layer by selectively introducing impurities into the epitaxial layer so that the collector region reaches the buried layer, (c) forming an insulating film on the epitaxial layer, (d) forming a polysilicon film on the insulating film, (e) patterning the polysilicon film to form a base electrode, (f) forming an interlayer insulating film over the base electrode and the insulating film, (g) patterning both the interlayer insulating film and the base electrode to form a base opening at a region at which a base region is to be formed and a collector opening above the collector region, (h) side-etching portions of the insulating film located below the base electrode to form undercut hollow portions in the insulating film, (i) filling the under

Abstract: A semiconductor device, and corresponding method of fabrication, includes a device isolation region formed in a semiconductor layer of a SOI substrate, the semiconductor layer having a first type of conductivity, a first impurity region made of portions of the semiconductor layer, and second and third impurity regions formed in the semiconductor layer outside of the first impurity region, the second and third impurity regions having a second type of conductivity. A base electrode is electrically connected to the first impurity region, a bit line electrode is electrically connected to the second impurity region and a capacitor is electrically connected to the third impurity region. The base electrode may be formed by etching a first contact hole through a first interlayer insulating film formed over the semiconductor layer and filling the first contact hole with an electrically conductive material.

Abstract: A semiconductor wafer having an SOI (Silicon-On-Insulator) structure and capable of being accurately aligned without undesirable contrast appearing in an infrared transmission image. The wafer is implemented as a laminate SOI wafer including an SOI layer. An aligning oxide film pattern and an oxide film pattern are buried in the SOI layer. The aligning oxide film pattern and oxide film pattern are respectively aligned with an aligning mask pattern and a mask pattern provided on a masking quartz wafer. In this condition, the laminate wafer is subjected to preselected processing. One of opposite major surfaces of the SOI wafer facing the quartz wafer is smoothed over its regions containing at least the aligning oxide film pattern and through which infrared rays are to be transmitted with respect to photoresist. The other major surface is smoothed over the above regions by having a polycrystal silicon film thereof removed.

Abstract: A bipolar semiconductor device includes an npn transistor using a base outlet electrode in the form of a polycrystalline Si film and one or more other devices using an electrode in the form of a polycrystalline Si film supported on a common p-type Si substrate, the sheet resistance of the polycrystalline Si film forming the base outlet electrode of the npn transistor is decreased to two thirds of the sheet resistance of the polycrystalline Si film forming at least one electrode of at least one other device. The base outlet electrode can be made by first making the polycrystalline Si film on the entire surface of the substrate, then applying selective ion implantation of Si to a selective portion of the polycrystalline Si film for making the base outlet electrode to change it into an amorphous state, and then annealing the product to grow the polycrystalline Si film by solid-phase growth.

Abstract: An SRAM memory cell is provided having a pair of cross-coupled CMOS inverters. The sources of the pull-up transistors forming each of the CMOS inverters are coupled to V.sub.cc through parasitic resistance of the substrate in which each is formed. The source of the p-type pull-up transistor is therefore always at a potential less than or equal to the potential of the N-well such that the emitter-base junction of the parasitic PNP transistor cannot become forward biased and latch-up cannot occur.

Abstract: A bipolar fabrication process, illustratively suited for integration into a conventional CMOS process to thereby form a BiCMOS integrated circuits is disclosed. The collector and base are formed through multiple implants and a single masking step to thereby provide a continuous low resistance collector region.

Abstract: A semiconductor device includes complementary first and second MOS transistors of different conductivity types and a bipolar transistor which are formed on a common substrate. The first MOS transistor has a first gate electrode of a polysilicon layer doped with impurities of a first conductivity type and a second conductivity type. A concentration of the impurities of the first conductivity type is higher than that of the second conductivity type. The second MOS transistor has a second gate electrode of a polysilicon layer doped with impurities of the second conductivity type, and the bipolar transistor has an emitter electrode of a polysilicon layer doped with impurities of the second conductivity type.

Abstract: A DRAM cell structure having charge amplification is disclosed. The DRAM cell has a capacitor to store an electrical charge. The DRAM cell further has a MOS transistor. The gate of the MOS transistor is coupled to a word line control to activate and deactivate the MOS transistor. The drain MOS transistor is coupled to one plate of the capacitor. The DRAM cell has a bipolar transistor to amplify the electrical charge stored on the capacitor. The bipolar transistor has a base that is the source for the MOS transistor. The base of the bipolar transistors is formed by masking and implanting a material of the first conductivity type adjacent to the gate to form the base. The collector of the bipolar transistor is the semiconductor substrate. The bipolar transistor has an emitter coupled to a bit-lines control which when activated will sense the charge amplified by the bipolar transistor.

Abstract: An integrated circuit device comprising an active layer of a first conductivity type insulatively disposed over a semiconductor substrate, a lateral bipolar transistor fabricated in the active layer, the lateral bipolar transistor comprising a first base layer of a second conductivity type which is formed in the active layer, an emitter layer of the first conductivity, and a collector of the first conductivity which is formed in the active layer on a lateral side of the first base layer, a MOS transistor fabricated in the active layer, the MOS transistor comprising a second base layer of the second conductivity type, a source layer of the first conductivity type which is formed in the second base layer, a drain layer of the first conductivity type which is formed in the active layer, and a gate electrode insulatively disposed over the second base layer between the source layer and the drain layer, and an isolation layer formed in the active layer for separating the bipolar transistor and the MOS transistor fr

Abstract: An analog switching circuit comprises an insulated-gate field-effect transistor (Q20) having two n-type input-side and outpu-side semiconductor regions (201, 202) and a p-type semiconductor substrate region 203, for controlling conductiveness between an input terminal (IN) and an output terminal (OUT) based on a gate potential. A surge pulse detecting circuit (1020), responsive to an electric potential (Vi) of the input terminal (IN), produces a detection signal of a surge pulse equivalent to a forward bias of a PN junction formed between the semiconductor substrate region (203) and the input-side semiconductor region (201). A substrate potential setting circuit (1010) varies an electric potential of the semiconductor substrate region (203) in response to the electric potential (Vi) of the input terminal (IN) when aby detection signal is produced.

Abstract: A power integrated circuit including a substrate of semiconductor material having a first conductivity type on which is formed a first epitaxial layer of the same conductivity type. In a first portion of the first epitaxial layer are formed first and second diffused regions having respectively first and second conductivity type. The first and the second diffused regions are isolated from a power stage included partially in a second portion of the first epitaxial layer by an annular region having the second conductivity type. Over the first epitaxial layer is formed a second epitaxial layer having the first conductivity type in which are extended the first and the second diffused regions to permit forming a control circuitry for the power stage.

Abstract: A layout structure of an SRAM for reductions in the number of interconnect layers and in the number of connection holes with conventional advantages maintained is disclosed. Contact holes and fields which have been shared between cells vertically adjacent to each other in plan view are divided between the cells. The cells are then positioned in translated relation also in a bit line direction (D1). In a resultant region, first-level polysilicon interconnect layers (1G(G)) for a GND line and first-level polysilicon interconnect layers (1G(W)) for a word line are formed in parallel in a word line direction (D2). Connection holes (GK2, GK1) for connecting gate electrodes of driver transistors (DTr1, DTr2) and fields (FL) are also used for connection holes (GK3) for connecting the fields (FL) and the GND interconnect layers (1G(G)). Further, interconnect layers having a high power supply potential is formed on the interconnect layers (1G(G)).

Abstract: A substantially concentric lateral bipolar transistor and the method of forming same. A base region is disposed about a periphery of an emitter region, and a collector region is disposed about a periphery of the base region to form the concentric lateral bipolar transistor of the invention. A gate overlies the substrate and at least a portion of the base region. At least one electrical contact is formed connecting the base and the gate, although a plurality of contacts may be formed. A further bipolar transistor is formed according to the following method of the invention. A base region is formed in a substrate and a gate region is formed overlying at least a portion of the base region. Emitter and collector terminals are formed on opposed sides of the base region. The gate is used as a mask during first and second ion implants.

Abstract: A bipolar transistor is formed by forming a base region continuing from a source/drain region of an MOS transistor, as a link base region, and forming an emitter region at a bit line contact hole by impurity implantation. Alternatively, the bipolar transistor is formed by forming an intrinsic base region and an emitter region at a bit line contact hole by impurity implantation. The intrinsic base region is made deeper than the source/drain region. Further, the impurity of the intrinsic base region is made different from that of the link base region.

Abstract: A method is provided for forming a planar transistor of a semiconductor integrated circuit, and an integrated circuit formed according to the same. A plurality of field oxide regions are formed overlying a substrate electrically isolating a plurality of transistors encapsulated in a dielectric. LDD regions are formed in the substrate adjacent the transistors and the field oxide regions. Doped polysilicon raised source and drain regions are formed overlying the LDD regions and a tapered portion of the field oxide region and adjacent the transistor. These polysilicon raised source and drain regions will help to prevent any undesired amount of the substrate silicon from being consumed, reducing the possibility of junction leakage and punchthrough as well as providing a more planar surface for subsequent processing steps.

Abstract: Disclosed is a method for manufacturing a BiCMOS in which a complementary MOS transistor and a bipolar transistor are formed on the same substrate, comprising the steps of: providing a semiconductor substrate with impurities of a first conductivity type; forming field oxides for device isolation at the substrate to define a first group active region having two active regions and a second group active region having five active regions in series arrangement; forming a first mask pattern to expose three central active regions of the second group active region; forming a buried layer of a second conductivity type at a first depth from surfaces of the three central active regions using the first mask pattern; forming a second mask pattern to expose either one active region of the first group active region and two active regions at both edge portions of the second group active region; forming first well regions of the second conductivity type in which the impurities of the second conductivity type are distributed t