Abstract: A method of forming a local interconnect for a semiconductor integrated circuit, the local interconnect comprising a refractory silicide contact having a substantially small sheet resistance formed at an exhumed surface of a gate stack, wherein the local interconnect electrically couples a gate electrode of the gate stack with an active region of the semiconductor substrate. The method of forming the local interconnect comprises depositing a gate oxide layer over the substrate, a first polysilicon layer over the gate oxide layer, a laterally conducting layer over the polysilicon layer, a second polysilicon layer over the laterally conducting layer, and an insulating layer over the second polysilicon layer. The intermediate structure is then etched so as to form a plurality of gate stacks. A surface of the second polysilicon layer of a gate stack is exhumed so as to allow subsequent formation of the refractory silicide contact at the exhumed surface.

Abstract: Methods of forming MOS transistors include forming lightly and heavily doped source/drain regions adjacent to one another in a substrate and a gate electrode with a sidewall spacer thereon. A salicide process is performed on a surface of the heavily doped source/drain region to provide a first suicide layer self-aligned to the sidewall spacer. At least a portion of the sidewall spacer is removed to expose a portion of the lightly doped source/drain region adjacent to the first silicide layer. A salicide process in performed on the exposed portion of the lightly doped source/drain region to provide a second silicide layer adjacent to the first suicide layer. Related devices are also disclosed.

Abstract: To provide a semiconductor device restraining high frequency impedance and restraining deterioration of a semiconductor layer, a gate wiring 26 is extended while meandering and intersects with a substantially straight line portion of a semiconductor layer 02 by a plurality of times thereby providing a plurality of gates.

Abstract: A high density wordline strapping arrangement is obtained by routing three primary metal-2 wordline straps in the same space as four polysilicon wordline, and routing the fourth wordline strap in a metal-4 layer over the primary metal-2 wordline straps. Stitches in metal-3 connect metal-2 primary wordline straps to metal-4 wordline straps. Therefore, contact spacing and metal pitch limitations are relaxed to allow four metal wordline straps to occupy the same pitch as four polysilicon wordlines. The wordlines are twisted to keep the fully balanced and to minimise coupling between wordline straps and neighbouring power and signal lines. Hence, a smaller memory cell array can be formed according to the wordline packing arrangement of the present invention.

Abstract: An aspect of the present invention includes a first MOSFET having a first gate electrode formed on a first semiconductor layer in a first region of a semiconductor substrate, a first channel region formed immediately below the first gate electrode in the first semiconductor layer, a first diffusion layer constituting source/drain regions formed at both the sides of the first channel region in the first semiconductor layer, a first epitaxial layer formed on the first diffusion layer, and a first silicide layer formed on the first epitaxial layer, and a second MOSFET having a second gate electrode formed on a second semiconductor layer in a second region of the semiconductor substrate, a second channel region formed immediately below the second gate electrode in the second semiconductor layer, a second diffusion layer constituting source/drain regions formed at both the sides of the second channel region in the second semiconductor layer, and a second silicide layer formed on the second diffusion layer.

Abstract: Disclosed is a semiconductor integrated circuit device (e.g., an SRAM) having memory cells each of a flip-flop circuit constituted by a pair of drive MISFETs and a pair of load MISFETs, the MISFETs being cross-connected by a pair of local wiring lines, and having transfer MISFETs, wherein gate electrodes of all of the MISFETs are provided in a first level conductive layer, and the pair of local wiring lines are provided respectively in second and third level conductive layers. The local wiring lines can overlap and have a dielectric therebetween so as to form a capacitance element, to increase alpha particle soft error resistance. Moreover, by providing the pair of local wiring lines respectively in different levels, integration of the device can be increased.

Abstract: A field effect transistor comprises a silicon layer formed on an insulator, a diffused layer formed by diffusing dopant from a part of a surface of the silicon layer up to the insulator, a silicide layer formed toward the insulator side from a surface of the diffused layer so as to have a thickness less than or equal to that of the diffused layer, a contact conductive layer formed on the surface of the silicide layer, a gate insulating layer formed on the silicon layer, a gate electrode formed on the gate insulating layer and a sidewall formed on a side surface of the gate electrode.

Abstract: A metal oxide semiconductor field effect transistor structure is disclosed. A p-shape gate, disposed over a semiconductor substrate. A gate dielectric layer is disposed in between the p-shape gate and the semiconductor substrate. A drain region is disposed within the semiconductor substrate, wherein the drain region is surrounded by the p-shape gate. A source region is disposed within the semiconductor substrate, wherein the source region surrounds the p-shape gate. A silicide structure is disposed on the source/drain regions and the p-shape gate.

Abstract: A semiconductor device having active regions connected by an interconnect line, which includes first and second transistors each having active regions and formed spaced apart from each other in a semiconductor substrate, an isolation region for isolating the first and second transistors from each other, a slit formed in the isolation region to allow those paired active regions of the first and second transistors which are opposed to each other with the isolation region interposed therebetween to communicate with each other through it, a conductive film formed on the inner walls of the slit, and an interconnect layer having first and second portions, each of which is electrically connected with a corresponding one of the paired active regions, and a third portion which is formed along the slit on the isolation region to connect the first and second portions with each other.

Abstract: When an arsenic ion (As+) large in mass is injected, polysilicon films are covered with a fifth resist mask so as to cover an end of the resist mask covering the polysilicon films to form a PMOS forming region. Through this process, a silicide non-forming region is arranged not to overlap with a pn junction to prevent the silicide non-forming region from increasing in resistance.

Abstract: Terminal regions of source/drain zones of an MOS transistor are configured over the substrate in the form of conductive structures, are separated from the substrate by separating layers, and exhibit a larger horizontal cross-section than doped regions forming the source/drain zones that are arranged in the substrate.

Abstract: The present invention discloses a thin film transistor with sub-gates and Schottky source/drain and a method of manufacturing the same. Doping of source/drain, and the following annealing steps used conventionally are omitted and the complexity of process and process costs are reduced. The temperature of the process is also decreased. A thin film transistor with sub-gates and Schottky source/drain of the invention is able to operate in both the n type and p type channel modes on the same transistor element depending on the biased voltage of the sub-gate. Moreover, an electric junction is formed by induction, using bias voltage applied on the sub-gate, which takes the place of the conventional source/drain extensions. Consequently, the off-state leakage current is reduced.

Abstract: This invention relates to a method and resulting structure, wherein a DRAM may be fabricated by using silicon midgap materials for transistor gate electrodes, thereby improving refresh characteristics of access transistors. The threshold voltage may be set with reduced substrate doping requirements. Current leakage is improved by this process as well.

Abstract: A semiconductor device having a low channel resistance without degrading transistor characteristics even for the 0.1 &mgr;m generation or later, and also: a manufacturing method of the device. The method includes fabricating source/drain electrodes and a gate electrode without using selective metal growth methods. Further, after forming the gate electrode, a semiconductor film is temporarily formed selectively in source/drain regions. A dielectric film is next deposited on the substrate and then, the surface is etched by chemical/mechanical polish (CMP) techniques to the extent that the semiconductor film is exposed on the surface. The semiconductor film is then partly etched until its midway portion along the thickness is removed. Thereafter, a desired metal or silicide is deposited on the entire surface. Next, CMP etching is performed to form electrodes, while letting the electrodes reside on or over the source/drain semiconductor layers and a gate insulation layer.

Abstract: A semiconductor device includes a semiconductor substrate, a barrier film in a field region of the semiconductor substrate, first and second conductivity-type well regions in the semiconductor substrate and divided by the barrier film in a surface of the semiconductor substrate, a gate insulating film on an entire surface of the semiconductor substrate, a gate electrode on a region of the gate insulating film, a lightly-doped first conductivity-type impurity region formed in the second conductivity-type well region at a first side of the gate electrode, a lightly-doped second conductivity-type impurity region formed in the first conductivity-type well region at a second side of the gate electrode, a conductive pattern connected with the lightly-doped first and second conductivity-type impurity regions and having a constant distance from the gate electrode, an insulating film formed on the semiconductor substrate exposing upper portions of the gate electrode and the conductive pattern, and heavily-doped first

Abstract: In a semiconductor device having a wire structure, the thickness of a first insulation film substantially corresponds to the depth of a contact hole. A surface of a second insulation film serves as a bottom face of a wire groove. Regarding the contact hole, only a side wall portion intersecting a direction of the wire groove has a substantial taper angle. This configuration can be attained under conditions where an etching selectivity of the first insulation film to the second insulation film is set to be slightly lower and a portion of the second insulation film where a opening edge of an opening portion is exposed is slightly etched during etching process of the wire groove. With a semiconductor device having this structure, a conductive material embedding characteristic can be enhanced, while preventing possibility of short-circuit even when an interval between wires is reduced.

Abstract: A method is provided for forming damascene gates and local interconnects a single process. By combining the formation of a damascene gate and local interconnect into a single process, a low cost solution is provided, having the advantages of low resistance wordlines and reduced gate length while reducing or eliminating the local interconnect to gate contact resistance. Further, the present invention provides flexible layout of active area to form small memory cells based upon the damascene gate and local interconnect structure. As such, the present invention is particularly suited for the fabrication of SRAM memory devices.

Abstract: A method of fabricating a DRAM integrated circuit structure (30) and the structure so formed, in which a common interconnect material (42, 48) is used as a first level interconnection layer in both an array portion (30a) and periphery portion (30p) is disclosed. The interconnect material (42, 48) consists essentially of titanium nitride, and is formed by direct reaction of titanium metal (40) in a nitrogen ambient. Titanium silicide (44) is formed at each contact location (CT, BLC) as a result of the direct react process. Storage capacitor plates (16, 18) and the capacitor dielectric (17) are formed over the interconnect material (42, 48), due to the thermal stability of the material. Alternative processes of forming the interconnect material (42, 48) are disclosed, to improve step coverage.

Abstract: A MOSFET having a new source/drain (S/D) structure is particularly adapted to smaller feature sizes of modern CMOS technology. The S/D conductors are located on the shallow trench isolation (STI) to achieve low junction leakage and low junction capacitance. The S/D junction depth is defined by an STI etch step (according to a first method of making the MOSFET) or a silicon etch step (according to a second method of making the MOSFET). By controlling the etch depth, a very shallow junction depth is achieved. There is a low variation of gate length, since the gate area is defined by etching crystal silicon, not by etching polycrystalline silicon. There is a low aspect ratio between the gate and the S/D, since the gate conductor and the source and drain conductors are aligned on same level. A suicide technique is applied to the source and drain for low parasitic resistance; however, this will not result in severe S/D junction leakage, since the source and drain conductors sit on the STI.

Abstract: A semiconductor device and a method of forming same are disclosed. The device includes an SOI wafer including a semiconductor layer, a substrate and a buried insulator layer therebetween. The semiconductor layer includes a source region, a drain region, and a body region disposed between the source and drain regions. At least one of the source and drain regions includes an epitaxially raised region. A gate is on the semiconductor layer, the gate being operatively arranged with the source, drain, and body regions to form a transistor. The at least one of the source and drain regions including the epitaxially raised region includes a silicide region spaced apart from the body region by about 200 to about 1000 Angstroms.

Abstract: An N-channel radiation-hardened transistor has source and drain regions that are fully enclosed by an intrinsically radiation-hardened thin gate-oxide, which substantially reduces radiation-induced intra-device and inter-device leakage currents. The width of the polysilicon gate directly between the source and drain can be the minimum feature size allowed by the design rules of a given process. The width of the polysilicon surrounding the device is chosen by design rules from the minimum allowed to some wider value to allows the polysilicon overlap to be sufficient to self-align the source and drain without compromising the doping under the field region. The polysilicon should be sufficiently wide so that it completely overlaps any transitional oxide such as LOCOS or trench oxide. The gate capacitance of the N-channel transistor can be tuned to balance SEU hardness and switching performance.

Abstract: Short channel effects are effectively suppressed by steep impurity concentration gradients which can be placed with improved accuracy of location and geometry while relaxing process tolerances by implanting impurities in a polysilicon seed adjacent a conduction channel of a transistor and diffusing impurities therefrom into the conduction channel. The polysilicon seed also allows the epitaxial growth of polysilicon source/drain contacts therefrom having a configuration which minimizes current density and path length therein while providing further mechanical advantages.

Abstract: A MOSFET having a new source/drain (S!D) structure is particularly adapted to smaller feature sizes of modern CMOS technology. The S/D conductors are located on the shallow trench isolation (STI) to achieve low junction leakage and low junction capacitance. The S/D junction depth is defined by an STI etch step (according to a first method of making the MOSFET) or a silicon etch step (according to a second method of making the MOSFET). By controlling the etch depth, a very shallow junction depth is achieved. There is a low variation of gate length, since the gate area is defined by etching crystal silicon, not by etching polycrystalline silicon. There is a low aspect ratio between the gate and the S/D, since the gate conductor and the source and drain conductors are aligned on same level. A suicide technique is applied to the source and drain for low parasitic resistance; however, this will not result in severe S/D junction leakage, since the source and drain conductors sit on the STI.

Abstract: A flash memory device comprising an epitaxial silicon floating gate containing conductive ions and overlying a tunnel oxide material; an inner-dielectric material overlying the epitaxial silicon floating gate, a polycide material overlying the inner-dielectric material, the tunnel oxide material, the epitaxial silicon floating gate, the inner-dielectric material and the polycide material forming a transistor gate, and source and drain electrodes on opposing sides of the transistor gate.

Abstract: A semiconductor processing method of forming a contact pedestal includes, a) providing a node location to which electrical connection is to be made; b) providing insulating dielectric material over the node location; c) etching a contact opening into the insulating dielectric material over the node location to a degree insufficient to outwardly expose the node location, the contact opening having a base; d) providing a spacer layer over the insulating dielectric material to within the contact opening to a thickness which less than completely fills the contact opening; e) anisotropically etching the spacer layer to form a sidewall spacer within the contact opening; f) after forming the sidewall spacer, etching through the contact opening base to outwardly expose the node location; g) filling the contact opening to the node location with electrically conductive material; h) rendering the sidewall spacer electrically conductive; and i) etching the electrically conductive material to form an electrically conducti

Abstract: The present invention provides a semiconductor device in which the gate is self-aligned to the device isolation film and a fabricating method thereof. A device isolation film restricting an active region is disposed on a portion of a semiconductor substrate, and a word line is across over the device isolation film. A gate pattern is disposed between the word line and the active region, and a tunnel oxide film is disposed between the gate pattern and the active region. The gate pattern comprises a floating gate pattern, a gate interlayer dielectric film pattern and a control gate electrode pattern deposited in the respective order, and has a sidewall self-aligned to the device isolation film. To form the gate pattern having the sidewall self-aligned to the device isolation film, a gate insulation film and a gate material film are formed in the respective order on the semiconductor substrate.

Abstract: Wiring for a semiconductor device which is suitable for high density device packing, and a method for forming the same, are disclosed. The wiring includes: impurity regions formed in a substrate on both sides of an insulated gate electrode; a first conduction layer formed on the impurity regions; and a second conduction layer formed in contact with the first conduction layer on one side of the gate electrode. The method includes the steps of: forming impurity regions in a substrate on both sides of an insulated gate electrode; forming a first conduction layer on the impurity regions; and forming a second conduction layer in contact on one side of the gate electrode with the first conduction layer.

Abstract: A semiconductor device improved to suppress a leakage current of a transistor is provided. A gate electrode is disposed on a semiconductor substrate. A pair of p type source/drain layers are provided on the surface of the semiconductor substrate, on both sides of the gate electrode in the gate length direction Y. An n type gate width determining layer is provided on the surface of the semiconductor substrate to sandwich the source/drain layers in the width direction X of the gate electrode, which determines a gate width of the gate electrode. The source/drain layers and the gate width determining layer are isolated by PN junction.

Abstract: A field effect transistor is formed with a sub-lithographic conduction channel and a dual gate which is formed by a simple process by starting with a silicon-on-insulator wafer, allowing most etching processes to use the buried oxide as an etch stop. Low resistivity of the gate, source and drain is achieved by silicide sidewalls or liners while low gate to junction capacitance is achieved by recessing the silicide and polysilicon dual gate structure from the source and drain region edges.

Abstract: A semiconductor device is provided with an SRAM memory cell. The semiconductor device includes a first gate-gate electrode layer, a second gate-gate electrode layer, a first drain-drain wiring layer, a second drain-drain wiring layer, a first drain-gate wiring layer and second drain-gate wiring layers. The first drain-gate wiring layer and an upper layer and a lower layer of the second drain-gate wiring layer are located in different layers, respectively. The width of the first gate-gate electrode layer in the first load transistor is larger than the width of the first gate-gate electrode layer in the first driver transistor.

Abstract: A semiconductor device is provided with an SRAM memory cell. The semiconductor device includes a first gate-gate electrode layer, a second gate-gate electrode layer, a first drain-drain wiring layer, a second drain-drain wiring layer, a first drain-gate wiring layer and a second drain-gate wiring layer. The first drain-gate wiring layer and an upper layer and a lower layer of the second drain-gate wiring layer are located in different layers, respectively. The diameter of a through hole in the first interlayer dielectric layer is equal to or less than the diameter of through holes in the second and third interlayer dielectric layers.

Abstract: Raised structures comprising overlying silicon layers formed by controlled selective epitaxial growth, and methods for forming such raised-structure on a semiconductor substrate are provided. The structures are formed by selectively growing an initial epitaxial layer of monocrystalline silicon on the surface of a semiconductive substrate, and forming a thin film of insulative material over the epitaxial layer. A portion of the insulative layer is removed to expose the top surface of the epitaxial layer, with the insulative material remaining along the sidewalls as spacers to prevent lateral growth. A second epitaxial layer is selectively grown on the exposed surface of the initial epitaxially grown crystal layer, and a thin insulative film is deposited over the second epitaxial layer.

Abstract: Semiconductor structures such as the trench and planar MOSFETs (UMOS), trench and planar IGBTs and trench MCTs using trenches to establish a conductor. Improved control of the parasitic transistor in the trench MOSFET is also achieved and cell size and pitch is reduced relative to conventional structures.

Abstract: Nickel silicidation of a gate electrode is controlled using a tungsten silicide barrier layer. Embodiments include forming a gate electrode structure comprising a lower polycrystalline silicon layer, a layer of tungsten silicide thereon and an upper polycrystalline silicon layer on the tungsten silicide layer, depositing a layer of nickel and silicidizing, whereby the upper polycrystalline silicon layer is converted to nickel silicide and the tungsten silicide barrier layer prevents nickel from reacting with the lower polycrystalline silicon layer.

Abstract: A semiconductor device according to the present invention includes a semiconductor substrate; device isolation regions provided in the semiconductor substrate; a first conductivity type semiconductor layer provided between the device isolation regions; a gate insulating layer provided on an active region of the first conductivity type semiconductor layer; a gate electrode provided on the gate insulating layer; gate electrode side wall insulating layers provided on side walls of the gate electrode; and second conductivity type semiconductor layers provided adjacent to the gate electrode side wall insulating layers so as to cover a portion of the corresponding device isolation region, the second conductivity type semiconductor layers acting as a source region and/or a drain region. The gate electrode and the first conductivity type semiconductor layer are electrically connected to each other.

Abstract: A width of a circuit device isolation region and a width of a device region formed on a semiconductor substrate are determined in such a manner as to satisfy a condition which prevents the occurrence of dislocation due to thermal oxidation for forming the isolation region. A semiconductor device can be fabrication which includes a semiconductor substrate, a plurality of circuit regions formed on a device formation region in the semiconductor substrate and having a width of 0.1 to 125 &mgr;m and device isolation regions so formed on the semiconductor substrate as to isolate a plurality of circuit regions from one another and having a width of 0.05 to 2.5 &mgr;m, and wherein a ratio of the width of the device isolation region to the width of a plurality of circuit regions adjacent to the device isolation region is from 2 to 50.

Abstract: A field-effect transistor and a method for its fabrication is described. The transistor includes a monocrystalline semiconductor channel region overlying and epitaxially continuous with a body region of a semiconductor substrate. First and second semiconductor source/drain regions laterally adjoin opposite sides of the channel region and are electrically isolated from the body region by an underlying first dielectric layer. The source/drain regions include both polycrystalline and monocrystalline semiconductor material. A conductive gate electrode is formed over a second dielectric layer overlying the channel region. The transistor is formed by patterning the first dielectric layer to selectively cover a portion of the substrate and leave an exposed portion of the substrate.

Abstract: A transistor and a method for making a transistor are described. A metal layer is formed upon a semiconductor substrate, and a masking layer is formed upon the metal layer. The masking layer is patterned to form an opening therein, and portions of the metal layer not covered by the masking layer are removed. A gate dielectric layer is formed within the opening upon the semiconductor substrate; in an embodiment, spacers are also formed upon opposed sidewall surfaces of the masking layer. A conductive material is then deposited upon the dielectric material to form a gate conductor. The masking material is then removed, source and drain and lightly doped drain impurity areas are formed in the semiconductor substrate, and the metal layer is annealed to form a silicide in close proximity to the channel region. By depositing the metal layer prior to forming the gate conductor, the process described herein allows formation of a metal silicide adjacent or in close proximity to the channel region of the transistor.

Abstract: A method of forming a transistor and a semiconductor-metal-oxide transistor. The method at least includes provides a substrate; covers the substrate by a doped amorphous polysilicon layer and a barrier layer in sequence, and removes part of the barrier layer and part of the doped amorphous polysilicon layer to form a hole which expose part of the substrate; forms a dielectric layer on both the barrier layer and the hole, wherein the hole is not totally filled by the dielectric layer; forms a conductor layer on the dielectric layer, wherein the hole is not totally filled by both the conductor layer and the dielectric layer; forms a metal layer on the conductor layer; performs a planarizing process by using the barrier layer as a stop layer; and removing the barrier layer.

Abstract: In a bipolar transistor block, a base layer (20a) of SiGe single crystals and an emitter layer (26) of almost 100% of Si single crystals are stacked in this order over a collector diffused layer (9). Over both edges of the base layer (20a), a base undercoat insulating film (5a) and base extended electrodes (22) made of polysilicon are provided. The base layer (20a) has a peripheral portion with a thickness equal to that of the base undercoat insulating film (5a) and a center portion thicker than the peripheral portion. The base undercoat insulating film (5a) and gate insulating films (5b and 5c) for a CMOS block are made of the same oxide film. A stress resulting from a difference in thermal expansion coefficient between the SiGe layer as the base layer and the base undercoat insulating film 5a can be reduced, and a highly reliable BiCMOS device is realized.

Abstract: A method of forming a contact opening including removing a residual carbon/halide layer which may form in the contact opening during the etching of the dielectric layer, or which may be intentionally deposited in the contact opening, wherein the removal of the carbon/halide layer also advantageously removes an adjacent portion of the active-device region of the semiconductor substrate which has become damaged or dopant depleted during the fabrication process. The removal of the carbon/halide layer is effected by a directional, energetic ion bombardment to activate the halides in the carbon/halide layer which, in turn, removes both the carbon/halide layer and a portion of the active-device region in a substantially anisotropic manner. The method of present invention is self-limiting because, once the halides within the carbon/halide layer are activated and thereby depleted, the removal of material in the adjacent active-device region ceases.

Abstract: A semiconductor device with a gate spacer containing a conductive layer, and a manufacturing method. A first spacer insulation layer is formed on a semiconductor substrate where a gate electrode is formed. Then, the first spacer insulation layer is etched to cover the side walls of the gate electrode. A conductive spacer film is subsequently formed on the resultant structure and is over-etched to form a conductive spacer that covers the first spacer insulation layer. In this step, the gate electrode is partially consumed to make the top of the first spacer insulation layer higher than the gate electrode. Also, an upper portion of the first spacer insulation layer is not comparatively etched due to an etching selectivity. This structure avoids shorts between the conductive spacer and the gate electrode. A second spacer insulation layer is then formed on the conductive spacer.

Abstract: Field effect transistor 22 comprises a gate insulator layer 12 formed on an outer surface of substrate 10. Composite gate stack 24 comprises the gate insulator layer 12, a silicide layer 18 and a polycrystalline semiconductor layer 20. Silicide layer 18 is formed by reacting an inner polycrystalline semiconductor layer 16 and a metal layer 14. Silicide layer 18 reduces carrier depletion effect because of its higher carrier density.

Abstract: A fabrication process of a non-volatile semiconductor memory device includes the step of forming a plurality of openings in a device isolation structure defining an active region in a memory cell region such that each opening exposes the substrate surface extends from the active region to the outside thereof. Further, silicide regions are formed in the openings by a self-aligned process such that the silicide regions are mutually separated. Further a contact hole is formed in an interlayer insulation film in correspondence to the silicide regions.

Abstract: An CMOS interconnection method that permits small source/drain surface areas has been provided. The interconnection is applicable to both strap and via type connections. The surface areas of the small source/drain regions are extended into neighboring field oxide regions by forming a silicide film from the source/drain regions to the field oxide. Interconnections on the same metal level, or to another metal level are made by contact to the silicide covered field oxide. The source/drain regions need only be large enough to accept the silicide film. Transistors with small source/drain regions have smaller drain leakage currents and less parasitic capacitance. A CMOS transistor interconnection apparatus has also been provided.

Abstract: In one implementation, a substrate is provided which has at least two nodes to be electrically connected. A first conductivity type semiconductive material is formed over and in electrical connection with one of the nodes. A conductive diffusion barrier material is formed over and in electrical connection with the first conductivity type semiconductive material. A second conductivity type semiconductive material is formed over and in electrical connection with the first conductivity type semiconductive material through the conductive diffusion barrier material, and over and in electrical connection with another of the nodes. The first conductivity type semiconductive material, the conductive diffusion barrier material and the second conductivity type semiconductive material are formed into a local interconnect electrically connecting the one node and the another node. Local interconnects fabricated by this and other methods are also contemplated.

Abstract: A semiconductor transistor which includes a silicon base layer, a gate dielectric formed on the silicon base layer, first and second silicon source/drain structures, first and second spacer structures, and a silicon gate structure is provided. A method for forming the semiconductor transistor may include a semiconductor process in which a dielectric layer is formed on an upper surface of a semiconductor substrate which includes a silicon base layer. Thereafter, an upper silicon layer is formed on an upper surface of the dielectric layer. The dielectric layer and the upper silicon layer are then patterned to form first and second silicon-dielectric stacks on the upper surface of the base silicon layer. The first and second silicon-dielectric stacks are laterally displaced on either side of a channel region of the silicon substrate and each include a proximal sidewall and a distal sidewall. The proximal sidewalls are approximately coincident with respective boundaries of the channel region.

Abstract: The invention is about a method for forming a MOS device. A substrate is provided first. A field oxide layer is formed on the substrate to define an active region. A gate structure is formed on the active region, where the gate structure has a gate oxide layer, a first gate layer, and a cap layer on the gate layer. The field oxide layer has a height substantially equal to the cap layer. The cap layer is thicker than the first gate layer, such as about three times of the first gate layer. A lightly doped region is formed in the substrate. A spacer is formed on a sidewall of the gate structure. A source/drain region is formed at each side of the gate. An epitaxial silicon layer is selectively formed on the source/drain region with a height substantially equal to the height of the first gate layer. The cap layer is removed to form a trench that exposes the first gate layer. A conductive layer is deposited on the first gate layer and the epitaxial silicon layer within the source/drain region.

Abstract: A gate electrode is formed on a semiconductor substrate with a gate insulating film interposed therebetween, and a sidewall spacer is then formed at the lateral sides of the gate electrode on the semiconductor substrate. Epitaxial growth is conducted at a lower growth rate to form, at both lateral sides of the sidewall spacer on the semiconductor substrate, first semiconductor layers made of first single-crystal silicon films superior in crystallinity. Then, epitaxial growth is conducted at a higher growth rate to form, on the first semiconductor layers, second semiconductor layers made of single-crystal films or polycrystalline films, which are inferior in crystallinity, or amorphous films. The upper areas of the first semiconductor layers and the whole areas of the second semiconductor layers are doped with impurity, thus forming impurity diffusion layers respectively serving as a source and a drain.

Abstract: A method of forming a temporary overhang structure to shield the source/drain edges near the gate electrode from the deposition of silicidation metal is provided. The growth of silicide on the source/drain regions remains controlled, without the presence of silicidation metal on the gate electrode sidewalls near the source/drain edges. The resulting silicide layer does not have edge growths interfering with the source/drain junction areas. The overhang structure is formed by covering the gate electrode with two insulators having differing etch selectivities. The top insulator is anisotropically etched so that only the top insulator covering the gate electrode vertical sidewalls remains. The exposed bottom insulator is isotropically etched to form a gap between the top insulator and the source/drain region surfaces. When silicidation metal is deposited, the gap prevents the deposition of metal between the gate electrode and the source/drain region surfaces.