Abstract: A semiconductor processing method of forming a contact pedestal includes, a) providing a node location to which electrical connection is to be made; b) providing insulating dielectric material over the node location; c) etching a contact opening into the insulating dielectric material over the node location to a degree insufficient to outwardly expose the node location, the contact opening having a base; d) providing a spacer layer over the insulating dielectric material to within the contact opening to a thickness which less than completely fills the contact opening; e) anisotropically etching the spacer layer to form a sidewall spacer within the contact opening; f) after forming the sidewall spacer, etching through the contact opening base to outwardly expose the node location; g) filling the contact opening to the node location with electrically conductive material; h) rendering the sidewall spacer electrically conductive; and i) etching the electrically conductive material to form an electrically conducti

Abstract: A novel transistor with a low resistance ultra shallow tip region and its method of fabrication. The novel transistor of the present invention has a source/drain extension or tip comprising an ultra shallow region which extends beneath the gate electrode and a raised region.

Abstract: The present invention provides a semiconductor device, comprising a semiconductor substrate, a gate insulating film formed on the semiconductor substrate, a gate electrode formed on the gate insulating film, and source-drain diffusion layer formed within the semiconductor substrate in the vicinity of the gate electrode. A silicide film is formed on each of the gate electrode and the source-drain diffusion layer. The silicide film positioned on the gate electrode is thicker than the silicide film positioned on the source-drain diffusion layer. The present invention also provides a method of manufacturing a semiconductor device, in which a gate electrode is formed on a gate insulating film covering a semiconductor substrate, followed by forming a source-drain diffusion layer within the semiconductor substrate.

Abstract: A method of fabricating a semiconductor device is provided. In this method, a gate insulating layer and a gate are sequentially formed on a semiconductor substrate of a first conductivity type. A first active region of a second conductivity type is formed by ion-implanting a first impurity of the second conductivity type at a first dose, using the gate as a mask. Sidewall spacers are formed of an insulating material on the sidewalls of the gate. A second active region of the second conductivity type is formed by masking a narrow region between gates and ion-implanting a second impurity of the second conductivity type at a second dose higher than the first dose. Finally, a silicide layer is formed on the exposed first and second active regions and gate. There exist no impurities in excess of their solid solubility limit, which could block the diffusion of silicon in the narrow region. As a result, a reliable silicidation is ensured.

Abstract: A first contact hole for a bit line is formed in an interlayer insulating film, and a polysilicon film is formed on the inner surface of the contact hole and on the interlayer insulating film. Subsequently, the polysiliccon film is subjected to isotropic dry etching using a resist as a mask, and the interlayer insulating film is subjected to RIE etching, thereby forming a second contact hole in the interlayer insulating film in a peripheral circuit region. Then, a laminated film is formed on the inner surface of the second contact hole and on the polysilicon film, and the second contact hole is filled with a filling member. The laminated film and the polysilicon film are patterned, thereby forming a bit line in a memory cell region.

Abstract: In a semiconductor device including a semiconductor substrate, a well formed on the semiconductor substrate, and a thick field insulating layer for surrounding an active area of the well, a contact structure is buried in a contact hole provided in the thick field insulating layer and connected to the well, so as to fix a voltage at the well.

Abstract: A gate insulator layer is formed over the semiconductor substrate and a first silicon layer is then formed over the gate insulator layer. An first dielectric layer is formed over the first silicon layer. A gate region is defined by removing a portion of the gate insulator layer, of the first silicon layer, and of the first dielectric layer. A doping step using low energy implantation or plasma immersion is carried out to dope the substrate to form an extended source/drain junction in the substrate under a region uncovered by the gate region. An undoped spacer structure is formed on sidewalls of the gate region and a second silicon layer is formed on the semiconductor substrate. The first silicon layer is then removed and another doping step is performed to dope the first silicon layer and the second silicon layer. A series of process is then performed to form a metal silicide layer on the first silicon layer and the second silicon layer and also to diffuse and activate the doped dopants.

Abstract: Self-aligned contacts to the source and drain regions of a MOS device are formed by selectively removing portions of sidewall spacers from polysilicon source and drain electrodes. Metal silicide layers are then formed in contact with the exposed polysilicon portions and extending over and in contact with respective source and drain regions formed in a semiconductor substrate surface.

Abstract: A method of fabricating a semiconductor device is provided. In this method, a gate insulating layer and a gate are sequentially formed on a semiconductor substrate of a first conductivity type. A first active region of a second conductivity type is formed by ion-implanting a first impurity of the second conductivity type at a first dose, using the gate as a mask. Sidewall spacers are formed of an insulating material on the sidewalls of the gate. A second active region of the second conductivity type is formed by masking a narrow region between gates and ion-implanting a second impurity of the second conductivity type at a second dose higher than the first dose. Finally, a silicide layer is formed on the exposed first and second active regions and gate. There exist no impurities in excess of their solid solubility limit, which could block the diffusion of silicon in the narrow region. As a result, a reliable silicidation is ensured.

Abstract: A semiconductor structure comprising a plurality of gates located on a semiconductor substrate; wherein insulating spacer is provided on sidewalls of the gates; and metallic silicide located between the gates is provided along with a method for its fabrication. A partially disposable spacer permits increased area for silicide formation without degrading the device short channel behavior.

Abstract: In a trench capacitor type semiconductor memory device including a semiconductor substrate having a trench and first and second impurity diffusion source/drain regions, a capacitor electrode buried in the trench, and a substrate-side capacitor electrode and a capacitor insulating layer within the semiconductor substrate and adjacent to a lower portion of the capacitor electrode, a buried insulating layer is formed between the semiconductor substrate and an upper portion of the capacitor electrode. The buried insulating layer is thicker than the capacitor insulating layer. However the buried insulating layer on a surface of the second impurity diffusion source/drain region is thin, or in direct contact with the capacitor electrode. A silicide layer is formed on the second impurity diffusion source/drain region and the capacitor electrode.

Abstract: The invention concerns a BI-CMOS process, in which Field-Effect Transistors (FETs) and Bipolar Junction Transistors (BJTs) are manufactured on a common substrate. In several processing steps, FET structures are formed simultaneously with BJT structures. For example, in one step, polysilicon gate electrodes for the FETs and polysilicon emitters for the BJTs are formed simultaneously. In another aspect of the invention, a polysilicon layer is used to reduce channeling which would otherwise occur during an implant step.

Abstract: A method for annealing amorphous silicon film to produce polycrystalline film suitable for thin-film transistors fabricated on glass substrates is provided. The method involves using the selective location of nickel on a predetermined region of silicon to define the pattern of the lateral growth front as the silicon is crystallized. The method defines the resistivity of the silicide formed. The method also defines a specific range of nickel thicknesses to form the nickel silicide. A minimum thickness ensures that a continuous layer of nickel silicide exists on the growth front to promote an isotropic lateral growth front to form a crystalline film having high electron mobility. A maximum thickness limit reduces the risk of nickel silicide enclaves in the crystalline film to degrade the leakage current. Strategic placement of the nickel helps prevent nickel silicide contamination of the transistor channel regions, which degrade the leakage current.

Abstract: A structure of a polysilicon via that includes a semiconductor substrate, a conducting layer on the substrate, a dielectric layer on the conducting layer, a polysilicon plug formed in the dielectric layer, a polysilicon layer on the polysilicon plug, and a silicide layer formed on the polysilicon layer. The polysilicon layer is electrically connected to the conducting layer through the polysilicon plug. The structure of a polysilicon via according to the invention prevents the occurrence of leakage currents in the presence of misalignment in the follow-up photolithography process.

Abstract: A semiconductor device includes a semiconductor substrate having a first and a second region, a first wiring layer including a lower layer having polycrystal silicon portions including impurities at a high concentration and formed over the first region of the semiconductor substrate via an insulating film. An upper layer of the first wiring layer is a metal silicide having a first film thickness. A second wiring layer includes a lower layer formed over the second region of the semiconductor substrate via an insulating film and is formed of either a non-doped polycrystal portion or a polycrystal silicon portion having a resistivity of at least 10 &OHgr;cm. An upper layer of the second wiring layer is a metal silicide portion having a second film thickness thicker than the first film thickness.

Abstract: A semiconductor thin film structure includes source/drain regions and a channel region positioned between the source/drain regions. The semiconductor thin film structure extends directly on and in contact with a surface of an insulation region. At least one of the source/drain regions includes a semiconductor material region extending directly over and in contact with the surface of the insulation region and a refractory metal silicide layer extending directly on and in contact with the semiconductor material region. The refractory metal silicide layer has a first thickness which is equal to or thicker than a half of a second thickness of the channel region, thereby suppressing any substantive kink effect.

Abstract: A method of forming a field effect transistor relative to a semiconductor substrate, where the transistor has a gate which defines a resultant lateral expense of semiconductive material therebeneath for provision of a transistor channel region, includes a) providing a conductive gate layer over a semiconductor substrate; b) patterning the conductive gate layer into a first gate block, the first gate block having a first lateral expanse which is greater than the resultant lateral expanse; c) providing an insulating dielectric layer over the first gate block; d) providing a patterned layer of photoresist over the first gate block and the insulating dielectric layer, the patterned photoresist comprising a photoresist block positioned over and within the first lateral expanse of the first gate block; e) with the patterned photoresist in place, etching the insulating dielectric layer selectively relative to the first gate block; f) after etching the insulating dielectric layer and with the patterned photoresist in

Abstract: A method for use in the fabrication of semiconductor devices includes forming a titanium nitride film and depositing a silicon hard mask over the titanium nitride film. The silicon hard mask is used to pattern a titanium nitride interconnect from the titanium nitride film and the silicon hard mask is also used as a contact etch stop for forming a contact area. In forming the interconnect, the silicon hard mask is dry etched stopping selectively on and exposing portions of the titanium nitride film and the exposed portions of the titanium nitride film are etched resulting in the titanium nitride interconnect. In using the silicon hard mask as a contact etch stop, an insulating layer is deposited over the silicon hard mask and the insulating layer is etched using the silicon hard mask as an etch stop to form the contact area. The silicon hard mask is then converted to a metal silicide contact area. Interconnects formed using the method are also described.

Abstract: A process for making a MOS transistor. The transistor includes a source, a channel and drain formed on a portion of silicon film in a silicon-on-insulator type structure. A field insulation layer surrounds the film. A grid structure with insulated flanks is formed above the channel. Source and drain contacts are formed on the portion of the silicon film between the field insulation layer and the grid structure. The source and drain contacts are self-aligned on the grid structure and the field insulation layer is placed directly adjacent to the grid structure.

Abstract: A method for forming a polycide/oxide/polysilicon capacitor on a silicon wafer with improved dielectric stability and reliability is described wherein an in-situ high temperature anneal is applied to the wafer within a CVD reactor immediately prior to the deposition of the silicon oxide capacitor dielectric layer. The in-situ anneal causes sufficient fluorine outgassing of the polycide layer to prevent fluorine degradation of the subsequently deposited oxide capacitor dielectric. The capacitance of the completed capacitor is increased by as much as 10% when compared to a comparable not in-situ anneal conducted prior to the insertion of the wafer into the CVD reactor.

Abstract: A semiconductor topography including integrated circuit gate conductors incorporating dual polysilicon layers is provided. The semiconductor topography includes a semiconductor substrate. A first gate conductor is arranged upon a first gate dielectric and above the semiconductor substrate, and a second gate conductor is arranged upon a second gate dielectric and above the semiconductor substrate. The semiconductor substrate may contain a first active region laterally separated from a second active region by a field region. The first gate conductor may be arranged within the first active region, and the second gate conductor may be arranged within the second active region. Each gate conductor preferably includes a second polysilicon layer portion arranged upon a first polysilicon layer portion. The thicknesses of the first gate conductor and the second gate conductor are preferably equal.

Abstract: A semiconductor device and a fabricating method thereof are provided. In the semiconductor device, active regions of first and second conductivity types are formed on a semiconductor substrate, apart from each other by a predetermined distance, and a silicide layer is formed on the active regions, for connecting the active regions to one another. By forming an offset area between active regions or gates of opposite conductivity types to space them from each other by a predetermined distance, there exists no area having an increased dopant concentration and a reliable silicidation is ensured.

Abstract: At least one patterned dielectric layer is provided within a transistor arrangement to prevent a local interconnect from electrically contacting the gate conductor due to misalignments during the damascene formation of etched openings used in forming local interconnects. By selectively etching through a plurality of dielectric layers during the local interconnect etching process, the patterned dielectric layer is left in place to prevent short-circuiting of the gate to an adjacent local interconnect that is slightly misaligned.

Abstract: A semiconductor device having a gate electrode with a sidewall air gap is provided. In accordance with this embodiment, at least one gate electrode is formed over a substrate. A spacer is then formed adjacent an upper sidewall portion of the gate electrode such that an open area is left beneath the spacer. Next, a dielectric layer is formed over the spacer and the gate electrode, thereby leaving an air gap in the open area. In accordance with one aspect of the invention, both the gate electrode and the spacer adjacent the gate electrode are formed from polysilicon. This, for example, allows the formation of a wider contact area to the gate electrode.

Abstract: A static random access memory (SRAM) is disclosed. The SRAM includes a shared contact. A gate oxide layer is firstly formed on a semiconductor substrate, and a polysilicon layer is then formed on the gate oxide layer. A dielectric spacer abuts surface of the polysilicon layer of the SRAM except on a top surface of the expect on a top surface of the polysilicon layer of the SRAM. Moreover, first ions of a first conductive type are implanted between the substrate. And second ions of the first conductive type are implanted into substrate to form a source/drain region of a first gate, and a second gate without the source/drain region using the dielectric spacers as a mask. The SRAM has at least three silicidation regions abutting top surface of the source/drain region, and the first and second gate, and the side wall second gate with no space is also covered a silicidation region. Finally, an inter-layer dielectric (ILD) is deposited over the substrate.

Abstract: P.sup.+ -type source/drain regions for load transistors and N.sup.+ -type source/drain regions for driver transistors are connected by means of P.sup.+ -type source/drain region outgoing lead and N.sup.+ -type source/drain region outgoing lead via direct contact holes. The drain region outgoing lead for the load transistors and ground lead are formed in a three-dimensionally overlapping manner, and the drain region outgoing lead for the driver transistors connected to memory nodes on one side and the drain region outgoing lead for the load transistors connected to memory nodes on the other side are also formed in a three-dimensionally overlapping manner, whereby memory node charge accumulators are constituted.

Abstract: A method of manufacturing a semiconductor device comprising the following steps: forming first, second, and third wiring layers on a semiconductor substrate; forming first, second, and third cover dielectric layers for covering these wiring layers; forming a first impurity diffusion layer of a P type and a second impurity diffusion layer of an N type in an active region, and forming a third impurity diffusion layer of a P type and a fourth impurity diffusion layer cf an N type in an active region; self-alignably forming a first local wiring layer for connecting the first impurity diffusion layer with the second wiring layer, and self-alignably forming a second local wiring layer for connecting the fourth impurity diffusion layer with the third wiring layer; in an interlayer dielectric layer, self-alignably forming a first contact hole by using the first and third cover dielectric layers as masking layers, and self-alignably forming a second contact hole by using the second cover dielectric layer as a masking

Abstract: A gate insulating film and gate electrodes are formed on a substrate containing N-type impurities such as P or As. Under the gate insulating film is a gate region on both sides of which are a first and a second source drain region. The gate region is furnished in its central part with a high-concentration channel injection region containing N-type impurities at a concentration higher than that of the substrate. Between the high-concentration channel injection region on the one hand and the first and the second source drain region and on the other hand, there are formed a first and a second low-concentration channel injection region and having substantially the same impurity concentration as that of the substrate.

Abstract: In the method of manufacturing a semiconductor device, according to the present invention, first, a dummy gate electrode consisting of a semiconductor layer and a non-metal cap layer formed on the semiconductor layer, is formed above a substrate. Then, diffusion layers are formed respectively on both sides of the dummy gate electrode. The dummy gate is used as a mask here, and thus the diffusion layers are self-aligned respectively with both sides of the dummy gate electrode. The formation of these diffusion layers requires a high-temperature heat treatment, however since the cap layer is made of a non-metal material, it is not melted down even in the high-temperature heat treatment. Next, the cap layer formed on the semiconductor layer is removed, and a gate groove made by the removal is filled with metal. Thus, a metal gate electrode made of a semiconductor layer and a metal layer is completed.

Abstract: A technique for fabricating an integrated circuit device 100 using an inverse-T tungsten gate structure 121 overlying a silicided layer 119 is provided. This technique uses steps of forming a high quality gate oxide layer 115 overlying a semiconductor substrate 111. The silicided layer 119 is defined overlying the gate oxide layer 115. The silicided layer 119 does not substantially react to this layer. The technique defines the inverse-T tungsten gate electrode layer 121 overlying the silicided layer 119. A top surface of this gate electrode may also be silicided 127 to further reduce the resistance of this device element.

Abstract: A complementary device consisting of a PMOS TFT transistor and an NMOS FET transistor uses a conducting layer to shunt drain regions of the transistors to eliminate any detrimental diode or p-n junction effects. The use of the conducting layer significantly improves the current drive capabilities of the PMOS TFT when the complementary device is used to design SRAM cells with NMOS pull-down transistors.

Abstract: In a semiconductor device such as a thin film transistor a semiconductor region is formed and an insulating film is formed on the semiconductor region to have a contact hole extending to the semiconductor region. An electrically conductive metal layer is formed of aluminum to fill the contact hole. An electrically conductive protection layer is formed on the metal layer to prevent oxidation of the metal layer during manufacturing of the semiconductor device. Material of the protection layer is more difficult to be oxidized than aluminum. A transparent electrode is formed on the protection layer such that the electrode is electrically connected to the semiconductor region. The protection layer may be formed of titanium or a laminate layer of a titanium layer and a titanium nitride layer.

Abstract: A method for forming a semiconductor device comprises the steps of forming first and second conductive lines having a space therebetween over a substrate, said first and second conductive lines each having a sidewall. A conductive spacer is formed over each sidewall, and an insulation layer is formed over the conductive spacers. First and second portions of the insulation is removed to form first and second openings therein, thereby exposing the spacers. The exposed portions of the spacers are removed. The conductive spacers form a conductive path between the first and second openings which would short any conductor formed in the first and second openings. To prevent shorting, a second protective layer is formed within the first and second openings which covers a portion of the spacers to remove the conductive path.

Abstract: In the manufacture of a planar channel-type MOS transistor, an n-well is formed in a predetermined region of a p-type semiconductor substrate to define a p-channel transistor region in which element forming regions are located as a p-type active region and a p-type gate electrode. A p-type substrate region adjacent to the p-channel transistor region defines an n-channel transistor region in which element forming regions are located as an n-type active region and an n-type gate electrode. Titanium silicide is formed in self-alignment as an upper layer of each of the p- and n-type active regions and p- and n-type gate electrodes. A boundary of the p- and n-type gate electrodes is a nondoped region where the titanium silicide is formed in an increased thickness as compared to that of the titanium silicide formed on the remaining portion of the gate electrodes.

Abstract: There is disclosed an active matrix liquid crystal display comprising pixels having an improved aperture ratio. A metallization layer makes contact with an active layer through openings. Inside the openings, the active layer is patterned into the same geometry as the metallization layer. That is, the active layer is patterned in a self-aligned manner according to the pattern of the metallization layer. This can enlarge the contact area. Also, the metallization layer does not required to be specially patterned for making contacts. A high aperture ratio can be obtained.

Abstract: Semiconductor structures such as the trench and planar MOSFETs (UMOS), trench and planar IGBTs and trench MCTs using trenches to establish a conductor. Improved control of the parasitic transistor in the trench MOSFET is also achieved and cell size and pitch is reduced relative to conventional structures.

Abstract: A semiconductor apparatus formed on a semiconductor substrate includes a first active region in the substrate, and a second active region adjacent to the surface of the substrate separated from the first active region by a channel region. A gate oxide region may overlie at least a portion of the first and second active regions. The apparatus further includes a gate positioned over the channel region and having a first end and a second end respectively associated with the first and second active regions. The gate includes a first low conductive region and a second low conduction region at said first and second ends, respectively.A method for making the transistor structure of the present invention is also provided.

Abstract: A semiconductor device comprises: a semiconductor substrate; a field oxide film formed in the semiconductor substrate, the field oxide film having element forming regions on both sides thereof; a pair of MOS transistors formed in the element forming regions on both sides of the field oxide film, each of the transistors having a gate oxide film, a gate electrode and a pair of source/drain regions; an interlayer insulating film covering the semiconductor substrate, the field oxide film and the transistors; a local interconnect formed by embedding a conductive material in a first opening formed in the interlayer insulating film, the first opening being arranged above the field oxide film and having a greater width than the field oxide film, an inner one of the pair of source/drain regions of each of the pair of transistors being exposed to the first opening, the inner one of the pair of source/drain regions of one of the pair of transistors being electrically connected to the inner one of the pair of source/drai

Abstract: In a semiconductor island structure with passive side isolation, a method and structure for reducing corner breakdown where a device conductor crosses the edge of the island. The decrease in the field strength at the island edge between the conductor and the adjacent conducting region may be achieved by increasing the depth of the insulator beneath the conductor where it crosses the island edge without the necessity for increasing the thickness of the layer of insulation applied directly to the surface of the island by the use of a second or higher level interconnect, e.g., the conventional deposition of one or more additional layers of insulation over the device terminal to increase the spacing between the conductor and the surface of the island. In this way the process by which the device is constructed may remain unchanged.

Abstract: A method of forming a field effect transistor relative to a monocrystalline silicon substrate, where the transistor has an elevated source and an elevated drain, includes: a) providing a transistor gate over the monocrystalline silicon substrate, the gate being encapsulated fin electrically insulative material; b) providing outer exposed monocrystalline silicon substrate surfaces adjacent the transistor gate; c) cleaning the outer exposed substrate surfaces to remove oxide and impurities therefrom; d) within a rapid thermal chemical vapor deposition reactor and after the cleaning step, chemical vapor depositing conductively doped non-polycrystalline silicon layer over the cleaned substrate surfaces adjacent the transistor gate, the non-polycrystalline silicon layer having an outer surface, the substrate not being exposed to oxidizing or contaminating conditions between the time of cleaning and the chemical vapor depositing; and e) after chemical vapor depositing, exposing the doped non-polycrystalline silicon

Abstract: A semiconductor device including a semiconductor substrate having thereon an element region having a surface, an element separating insulating film having an upper surface adjacent to opposing lateral sides of the element region, a silicon epitaxial layer having an upper surface formed on the surface of the element region, a polysilicon layer having an upper surface formed on the element separating film and connected to the silicon epitaxial layer, a gate insulating film and a gate electrode formed on the silicon epitaxial layer, and impurity doped source and drain regions formed in the silicon epitaxial layer. Furthermore, the upper surface of the silicon epitaxial layer is higher than or at the same level as the upper surface of the polysilicon layer. This is done by forming the polysilicon layer on a recessed portion of the element separating insulating film adjacent to the element region.

Abstract: The disclosed semiconductor memory cell can be formed in accordance with the standard process for the logic LSI, so that the manufacturing cost can be reduced and an increased node capacitance can be secured.

Abstract: A multi-dimensional transistor structure is fabricated which includes a base transistor substrate upon which transistors are formed. An elevated substrate is formed overlying the base transistor and having an oxide isolation formed in localized regions beneath the elevated substrate but overlying the base transistor substrate. A plurality of transistors are formed on a substrate wafer to form a base-level transistor formation. An intralevel dielectric (ILD) layer is deposited overlying the base-level transistor formation. Overlying the ILD layer, a "sandwich" structure is formed with the deposition of a first polysilicon layer, deposition of an oxide isolation layer, and deposition of a second polysilicon layer.

Abstract: A field effect transistor relative to a semiconductor substrate, where the transistor has a gate which defines a resultant lateral expanse of semiconductive material therebeneath for provision of a transistor channel region, includes a) providing a conductive gate layer over a semiconductor substrate; b) patterning the conductive gate layer into a first gate block, the first gate block having a first lateral expanse which is greater than the resultant lateral expanse; c) providing an insulating dielectric layer over the first gate block; d) providing a patterned layer of photoresist over the first gate block and the insulating dielectric layer, the patterned photoresist comprising a photoresist block positioned over and within the first lateral expanse of the first gate block; e) with the patterned photoresist in place, etching the insulating dielectric layer selectively relative to the first gate block; f) after etching the insulating dielectric layer and with the patterned photoresist in place, etching the

Abstract: First and second gate electrodes are formed spaced from each other on a semiconductor substrate. A pair of impurity diffusion layers are provided on both sides of the first gate electrode at the surface of the semiconductor substrate. The first gate electrode includes a first lower conductive film, a first protective conductive film provided on the first lower conductive film, and a first upper conductive film provided on the first protective conductive film. The second gate electrode includes a second lower conductive film, a second protective conductive film provided on the second lower conductive film, and a second upper conductive film provided on the second protective conductive film. The second upper conductive film extends to be in contact with one of the pair of impurity diffusion layers.

Abstract: A DRAM unit cell is disclosed which comprises a trench capacitor having a signal electrode, a bit line, a planar active word line overlapping the trench capacitor and a planar FET having a main conducting path coupled between the signal electrode of the trench capacitor and the bit line and a gate electrode formed by the active word line.

Abstract: A semiconductor device has a metal silicide on silicon conductor formed using a salicide process. The metal silicide layer of the conductor includes boron which improves the morphology and conductivity of the metal silicide layer. Implanting boron into the metal silicide layer or the metal to be silicided prevents the metal silicide from aggregating during a subsequent annealing or other heating process. This process allows narrower conductors to be formed without undesirable increases in the resistance of the metal silicide layer. The boron incorporating salicide process is compatible with CMOS processes.

Abstract: A method is provided for forming an improved landing pad of a semiconductor integrated circuit, and an integrated circuit formed according to the same. A first opening is formed through a first dielectric layer to expose a portion of a diffused region. A landing pad is formed over the first dielectric layer and in the opening. The landing pad preferably comprises a doped polysilicon layer disposed in the first opening and over a portion of the first dielectric layer. The landing pad will provide for smaller geometries and meet stringent design rules such as that for contact space to gate. A second dielectric layer having an opening therethrough is formed over the landing pad having an opening therethrough exposing a portion of the landing pad. A conductive contact, such as aluminum, is formed in the contact opening. The conductive contact will electrically connect with the diffused region through the landing pad.

Abstract: An integrated inductor-capacitor (L-C) structure can be formed on a semiconducting substrate (10) by depositing a metal layer in a pattern that contains an inductor coil (14) and a capacitor bottom electrode (12). A CuFe.sub.2 O.sub.4 film (16) is then deposited on the substrate and over the metal pattern to form the dielectric portion of the L-C structure. A via (17) created in the CuFe.sub.2 O.sub.4 film exposes a portion of the inductor coil. Another metal layer (18) is then deposited over the CuFe.sub.2 O.sub.4 film and in the via, such that this metal layer is electrically connected to the inductor coil through the via. A pattern is also made in the second metal layer to form a top electrode (19) for the capacitor, over the corresponding capacitor bottom electrode, and to form a circuit interconnect to the inductor coil through the via.

Abstract: An FET semiconductor substrate includes source/drain regions with an outer buried contact region overlapping the drain region, a gate oxide layer, and a polysilicon layer over the gate oxide layer. An inner buried contact opening through the polysilicon and the gate oxide layer reaches down to the substrate over the outer buried contact region. An inner buried contact region, within the outer buried contact region, is self-aligned with the buried contact opening. A second polysilicon layer formed over the gate oxide layer reaches down through the buried contact opening into contact with the inner buried contact region. An interconnect and a gate electrode are formed from the polysilicon layers. Source/drain regions are self-aligned with the gate electrode and whereas the drain region is spaced from the inner buried contact region, the outer buried contact region interconnects the drain region with the inner buried contact region.