Abstract: A semiconductor memory device includes a semiconductor substrate, and a memory cell formed on the semiconductor substrate and including two transfer transistors, two driver transistors and two thin film transistor loads. The thin film transistor load includes a first gate electrode, a first insulator layer formed on the first gate electrode, a semiconductor layer formed on the first insulator layer, a second insulator layer formed on the semiconductor layer, and a shield electrode formed on the second insulator layer. This shield electrode shields the thin film transistor.

Abstract: A process for forming low threshold voltage P-channel MOS transistors in semiconductor integrated circuits for analog applications, said circuits including high resistivity resistors formed in a layer of polycrystalline silicon and N-channel MOS transistors having active areas which have been obtained by implantation in a P-type well, comprises the steps of,providing a first mask over both said resistors and the semiconductor regions where the low threshold voltage P-channel transistors are to be formed,doping the polycrystalline layer uncovered by said first mask,providing a second mask for protecting the resistors and the semiconductor regions where said low threshold voltage P-channel transistors are to be formed, andN+ implanting the active areas of the N-channel transistors.

Abstract: A process for developing conductive interconnect regions between integrated circuit semiconductor devices formed on an insulating substrate utilizes the semiconductor material itself for formation of device interconnect regions.A patterned layer of semiconductor material is formed directly on the surface of an insulating substrate. The patterned layer includes regions where semiconductor devices are to be formed and regions which are to be used to interconnect terminals of predetermined ones of the semiconductor devices. After forming the semiconductor devices in selected regions of the semiconductor material, the regions of the semiconductor material patterned for becoming interconnects are converted to a metallic compound of the semiconductor material.

Abstract: A process for making a dual gated thin film transistor (TFT), having a sidewall channel and self-aligned gates and off-set drain is disclosed. A substrate having a top surface with insulating regions is provided. A bilayer having a polysilicon bottom layer and an insulating top layer, is patterned to form the bottom electrode of the TFT with an insulating layer over it. A first gate insulator is formed in contact with sides of the bottom electrode. A layer of second polysilicon having two end source and drain regions and a middle channel region is formed with the channel region being vertical along the side of the bottom electrode and overlying insulator layer and in contact with the first gate insulator. A second gate insulator is formed on the second polysilicon. A contact opening is etched in the insulating layers overlying the bottom electrode, in a region away from the second polysilicon to expose surface of part of the bottom electrode.

Abstract: Short channel MOS devices are provided with two distinct doped polysilicon contacts: (a) doped polysilicon layers in contact with the source or drain regions (the LDD regions) and extending underneath the oxide region to abut the oxide liner of the trench sidewalls; and (b) polysilicon source and drain contacts in contact with the doped polysilicon layers. The shallow channel doping region is self-aligned with the lightly doped source and drain regions; this ensures vertically engineered profiles that give high punchthrough voltages and an excellent short channel control. The use of the doped polysilicon layers ensures self-alignment of source/drain diffusions and channel and prevents etching of TEOS in the trenches, which prevents exposure of trench sidewalls and formation of parasitic devices in the sidewalls. Further, use of doped polysilicon layers to form the LDD regions by diffusion results in high currents and shallow junctions.

Abstract: A monolithic semiconductor device includes a field effect transistor and a bipolar junction transistor with an elevated emitter structure. An elevation structure raises the BJT emitter above the plane of the base. The elevation structure increases travel distance between a heavily doped base contact region and the emitter and protects against encroachment without increasing the total surface area allocated to the BJT device. A spacer oxide separates the polysilicon base contact and the elevation structure.

Abstract: Negative characteristic MISFETs, which are of the same channel conductivity type and which have different threshold voltages, are formed in a doped silicon thin film deposited over a substrate and are connected in channel-to-channel series with each other. The pair of series-connected negative characteristic MISFETs, a resistive element, an information storage capacitive element and a transfer MISFET constitute an SRAM memory cell. Equivalently, a negative characteristic MISFET having a current-voltage characteristic defined by a negative resistance curve can be used in lieu of the pair of series-connected negative characteristic MISFETs in the formation of the individual memory cells of the SRAM. The negative resistance curve of the negative characteristic MISFET is shaped such that the linear current-voltage characteristic curve corresponding to the resistive element of the memory cell intersects the negative resistance curve at at least three location points.

Abstract: A buried layer which is highly doped and implanted with high energy in a lightly doped isolated well in which an array of flash EPROM cells are provided. The buried layer is doped with the same conductivity dopant as the well in which it is provided, for example a p.sup.+ -type buried implant is provided in a p-type well. The buried layer enables channel size of the flash EPROM cells to be reduced providing a higher array density. Channels of the flash EPROM cells are reduced because the buried layer provides a low resistance path between channels of the flash EPROM cells enabling erase to be performed by applying a voltage potential difference between the gate and substrate of a cell.

Abstract: A compact MOS type active device is constructed at least partially in an opening in an insulation layer, such as an oxide layer, above a portion of a semiconductor substrate forming a first source/drain region of the MOS type active device. A semiconductor material, on the sidewall of the opening, and in electrical communication with the portion of the substrate forming the first source/drain region of the device, comprises the channel portion of the MOS device. A second source/drain region, in communication with an opposite end of the channel, is formed on the insulation layer adjacent the opening and in electrical communication with the channel material in the opening. A gate oxide layer is formed over the channel portion and at least partially in the opening, and a conductive gate electrode is then formed above the gate oxide.

Abstract: A poly-crystal silicon layer is formed on an N-type silicon substrate via an oxide film. A contact hole is formed on the poly-crystal silicon layer by applying a photoresist mask and further by patterning a predetermined contact portion between a polyside gate and a diffusion layer. Thereafter, a P.sup.+ diffusion layer is formed by ion implantation with the use of the same photoresist mask. Further, a tungsten siliside layer is deposited all over the substrate. Or else, after the contact hole has been formed, the tungsten siliside layer is deposited, and then the P.sup.+ diffusion layer is formed by ion implantation. Alternatively, after the contact hole has been formed, a first ion implantation is made; and after the tungsten siliside layer has been deposited, a second ion implantation is made to form the P.sup.+ diffusion layer.

Abstract: A power MOSFET is created from a semiconductor body (2000 and 2001) having a main active area and a peripheral termination area. A first insulating layer (2002), typically of substantially uniform thickness, lies over the active and termination areas. A main polycrystalline portion (2003A/2003B) lies over the first insulating layer largely above the active area. First and second peripheral polycrystalline segments (2003C1 and 2003C2) lie over the first insulating layer above the termination area.A gate electrode (2016) contacts the main polycrystalline portion. A source electrode (2015A/2015B) contacts the active area, the termination area, and the first polycrystalline segment. An optional additional metal portion (2019) contacts the second polycrystalline segment. In this case, the second polycrystalline segment extends over a scribe-line section of the termination area so as to be scribed during a scribing operation.

Abstract: A method of fabricating BiCMOS devices, and the resultant BiCMOS device, are disclosed. According to the present invention, over-etching to the substrate on the deposited polysilicon emitter is prevented by providing additional oxide beneath a polysilicon layer as an etch stop. Despite inclusion of an oxide to define an end-point during patterning of an emitter, fabrication complexity is reduced by avoiding additional SAT masking and oxidation steps.

Abstract: A semiconductor device includes a polycrystalline silicon layer formed on a silicon layer with an oxide film therebetween, an interlayer insulating layer formed to cover the surface of the silicon layer and the surface of the polycrystalline silicon layer, and a silicon plug layer formed in an embedded manner in a contact hole in the interlayer insulating layer to be directly connected to the surface of an end portion of the polycrystalline silicon layer and the surface of the silicon layer in the proximity of the end portion of the polycrystalline silicon layer. The polycrystalline silicon layer and the silicon plug layer have the same type of conductivity. By this interconnection structure, the semiconductor device is improved in the patterning accuracy of the contact portion of a multilayer stacked interconnection. Furthermore, an ohmic contact between conductive interconnection layers can be realized with relatively simple manufacturing steps without occurrence of a voltage drop caused by a pn junction.

Abstract: A charge pump (10) uses Schottky diodes (12) coupled to clock signals (o.sub.1 and o.sub.2) via respective capacitors (14a-d). Regulation and control circuitry 18 provides a stable voltage output and controls the clock circuitry (16).

Abstract: A CMOS integrated circuit uses self-aligned transistors combined with local planarization in the vicinity of the transistors so as allow local interconnects which are free of bridging, have good continuity over the planarized topography and are compatible with the self-alignment schemes, hence conserving chip real estate. After formation of self-aligned insulated transistor gates and active transistor regions, the integrated circuit structure is planarized by formation of an oxide layer and a reflowed overlying glass layer. The glass layer and underlying oxide layer are removed only in the area of the buried contact, while an overlying metal or polysilicon conductive layer contacts the upper surface of certain of the transistor gate structures, the topside insulating layer of which has been removed for this purpose.

Abstract: A silicon layer in a lower layer and an interconnection layer arranged in an upper layer are electrically connected through an opening for contact. A silicon plug layer having the same conductivity type as that of the silicon layer is embedded in the opening. The silicon plug layer is embedded in the opening by an etch back method after deposited using a CVD method. The interconnection layer in the upper layer has conductivity type different from that of the silicon plug layer. A refractory metal silicide layer is formed between the upper interconnection layer and the silicon plug layer.The refractory metal silicide layer prevents pn junction from being formed between the upper interconnection layer and the silicon plug layer.

Abstract: A semiconductor device comprises a semiconductor substrate of a first conductivity type and a pair of spaced diffused layers of a second conductivity type different from the first conductivity type formed in surface portions of the semiconductor substrate. A gate electrode is formed on a channel region between the pair of diffused layers in the semiconductor substrate with an intermediate gate oxide layer disposed therebetween, and then a silicon dioxide film is formed to cover an upper surface and side surfaces of the gate electrode and surface portions of the substrate in which the pair of diffused layers is formed. A side wall made of polycrystalline silicon is formed to cover the silicon dioxide film on each of the side surfaces of the gate electrode and an interlayer insulating film is formed to cover the silicon dioxide film, the side wall and the substrate.

Abstract: A semiconductor memory cell (10) includes first and second cross-coupled driver transistors (13, 19) each having a source-drain region and a channel region formed in a first thin-film layer (36, 36'). First and second parallel opposed wordlines (20, 22) overlie a single-crystal semiconductor substrate (12) and the channel region (46) of each driver transistor overlies a portion of an adjacent wordline. A portion of the thin-film layer (36, 36') makes contact to the single-crystal semiconductor substrate (12) adjacent to the opposite wordline. The channel and source-drain regions of first and second load transistors (15, 21) are formed in a second thin-film layer (64) which overlies the driver transistors (13, 19). The load transistors (15, 21) are cross-coupled to the driver transistors (13, 19) through common nodes (31, 33).

Abstract: A semiconductor device having an increased integration density. The semiconductor device includes a memory cell array, and a peripheral circuit region formed over the memory cell array and to be in electrical connection to the memory cell array for controlling the input/output of the data signals. A large part of a semiconductor chip area can therefore be used for the memory cell array, thereby increasing the integration density of the semiconductor device.

Abstract: In a semiconductor integrated circuit having a block of static memory cells using CMOS transistors and peripheral components using bipolar transistors, metal interconnections in a layer over the CMOS transistors on the substrate are simplified by using buried layers in the substrate as supply and ground lines for the CMOS transistors. This is accomplished by making buried contacts of a metal such as tungsten in each memory cell to make ohmic connection of the diffused layer of n-MOS transistors and the diffused layer of p-MOS transistors respectively to underlying buried layers of opposite conductivities and applying supply voltage or ground potential to each buried layer from the substrate surface by using additional buried contacts which are made at convenient locations outside the memory block. In the case of n-MOS memory cells using resistors or TFTs as load elements, ground potential is applied to the n-MOS transistors by the same method.

Abstract: A ROM array comprises orthogal sets of buried bit lines and polysilicon wordlines. The buried bit lines comprise trenches with insulating material on the side walls, the trenches then being filled with polysilicon. Theis reduces bit line sheet resistance and increases the punch through voltage between adjacent bit lines.

Abstract: A method for forming a vertical transistor (10) begins by providing a substrate (12). A conductive layer (16) is formed overlying the substrate (12). A first current electrode (26), a second current electrode (30), and a channel region (28) are each formed via one of either selective growth, epitaxial growth, in-situ doping, and/or ion implantation. A gate electrode or control electrode (34) is formed laterally adjacent the channel region (28). A selective/epitaxial growth step is used to connect the conductive layer (16) to the control electrode (34) and forms a control electrode interconnect which is reliable and free from electrical short circuits to the current electrodes (26 and 30). The transistor (10) may be vertically stacked to form compact inverter circuits.

Abstract: A power MOSFET is created from a semiconductor body (2000 and 2001) having a main active area and a peripheral termination area. A first insulating layer (2002) of substantially uniform thickness lies over the active and termination areas. A main polycrystalline portion (2003A/2003B) lies over the first insulating layer largely above the active area. First and second peripheral polycrystalline segments (2003C1 and 2003C2) lie over the first insulating layer above the termination area.A gate electrode (2016) contacts the main polycrystalline portion. A source electrode (2015A/2015B) contacts the active area, the termination area, and the first polycrystalline segment. An optional additional metal portion (2019) contacts the second polycrystalline segment. The MOSFET is typically created by a five-mask process. A defreckle etch is performed subsequent to metal deposition and patterning to define the two peripheral polycrystalline segments.

Abstract: A method of producing a ROM device wherein parallel spaced bit line regions are formed in a semiconductor substrate, blanket layers of (1) polysilicon, (2) etch stop material, and (3) polysilicon, are deposited, the layers etched to form orthogonal parallel word lines on the surface of the substrate, a thick insulating layer deposited over the word lines, a resist layer deposited, exposed and developed to define a desired code implant pattern, the exposed areas of the thick layer removed, and the underlie upper polysilicon layer of the bit line removed, and ion implanted into the substrate to form a code implant.

Abstract: A method of fabricating a semiconductor device, in particular of forming a polysilicon film on a step portion of an insulation film made by a trench or a contact hole is disclosed which includes the steps of depositing an amorphous silicon film on the step portion while doping impurities into the amorphous silicon film and carrying out heat treatment to convert the amorphous silicon film into a polycrystalline silicon film, thereby the polysilicon film on a step portion being formed.

Abstract: A semiconductor device comprising a semiconductor substrate, an insulating film formed on the semiconductor substrate, and a polycide film including a polysilicon layer and a silicide layer formed on the insulating film. The polysilicon layer includes a p-type region having p-type impurities diffused therein and an n-type region having n-type impurities diffused therein. The p-type impurities are implanted into the silicide layer in order to have a substantially uniform concentration over the entire potion thereof, so that the p-type impurities in the p-type region of the polysilicon layer do not diffuse into the silicide film by a poet heat treatment.

Abstract: A power semiconductor device which is integrable in an integrated circuit includes a semiconductor body having first and second major opposing surfaces with a first doped region of a first conductivity type therebetween, second and third doped regions of a second conductivity type formed in the first doped region, the second and third doped regions being spaced apart and abutting the first surface, and fourth and fifth doped regions of the first conductivity type respectively formed in the second and third doped regions and abutting the first surface. Sixth and seventh doped regions extend from the first surface into the first region, the sixth region being adjacent to the second and fourth regions and spaced therefrom by an electrically insulative layer, the seventh region being adjacent to the third and fifth regions and spaced therefrom by an insulative layer.

Abstract: A semiconductor device of the present invention includes a semiconductor substrate, a p-type impurity diffused region formed in the semiconductor substrate, and a polycide interconnection electrically connected to the p-type impurity diffused region. In the semiconductor device, the polycide interconnection includes a first polysilicon film, a refractory metal silicide film formed on the first polysilicon film, and a second polysilicon film formed on the refractory metal silicide film.

Abstract: An integrated circuit structure is suitable for use with SRAM memory devices. P-channel load devices are used in a 6-transistor SRAM cell. The P-channel devices are formed as polycrystalline silicon field effect transistors above the N-channel field effect transistors, which are formed in the substrate. In order to avoid formation of a P-N junction, a barrier layer is formed between P-type and N-type source/drain regions. The preferred barrier is a bilayer formed from a conductive material such as silicide over a doped polycrystalline silicon layer.

Abstract: The invention is directed to a thin film transistor (TFT) fabricated by using a recessed planarized poly plug as the bottom gate and a recessed planarized poly plug for the TFT drain connecting region. The TFT of the present invention can be used in any integrated circuit that uses such devices and in particular as a pullup device in a static random access memory (SRAM). The invention is directed to a process to fabricate a thin film transistor (TFT) having LDDs and/or high resistive regions (loads) that are self-aligned to a recessed plug that is used as the bottom gate for the TFT.

Abstract: A static type random access memory cell comprises two n-channel type driver transistors formed in a major surface portion of a p-type silicon substrate, two n-channel type transfer transistors formed in the major surface portion of the p-type silicon substrate, and two p-channel type load transistors stacked over the n-channel type driver transistors, and heavily doped n-type polysilicon gate electrodes of the n-channel type driver transistors are electrically connected with p-type polysilicon gate electrodes of the p-channel type load transistors, respectively, wherein metal films are inserted between the n-type polysilicon gate electrodes and the p-type polysilicon gate electrodes so that any undesirable diode never take place therebetween.

Abstract: An n-channel MOSFET, a p-channel MOSFET and a nonvolatile memory cell are provided for the same semiconductor substrate. The nonvolatile memory cell is formed on the semiconductor substrate, the n-channel MOSFET is formed in a p-type well region of the semiconductor substrate, and the p-channel MOSFET is formed in an n-type well region of the semiconductor substrate.

Abstract: Disclosed is a semiconductor device having complementary metal insulator semiconductor field-effect transistors (MISFETs) in which a plurality of basic cells having N-channel MOSs and P-channel MOSs are disposed. In this semiconductor device, a sub MISFET is disposed adjacently to a stopper layer in a region adjacent to other basic cell. An element such as a transmission gate composed of a single element can be actualized by use of the sub-MISFET. In the semiconductor device of this invention, a working efficiency thereof is improved. A response velocity of the P-channel MOS can also be improved using the sub-MISFET. A numerical quantity of the basic cells constituting a circuit can be reduced, resulting in a reduction in parasitic capacity. An operating time of the circuit is thereby decreased.

Abstract: A CMOS SRAM memory cell, and a method of making the same, is disclosed. The disclosed cell is configured as cross-coupled CMOS inverters, with the n-channel pull-down transistors in bulk, and with the p-channel load devices being accumulation mode p-channel transistors in a thin polysilicon film. The cross-coupling connection is made by way of an intermediate layer, which may include polysilicon at its top surface for performance enhancement, each of which makes contact to the drain region of an n-channel transistor, and to the opposite gate electrode, via a buried contact. The intermediate layer also serves as the gate for the thin-film p-channel transistor, which has its channel region overlying the intermediate layer. The p-channel transistors may be formed so as to overlie part of the n-channel transistor in its inverter, thus reducing active chip area required for implementation of the memory cell.

Abstract: There is provided a technique capable of reducing the electrode resistance by widening the effective area of an electrode in a cell for a standard potential supply connected to the memory cell. There is also provided a technique capable of reducing the memory cell area by reducing the area necessary for separation between the electrode in a cell for the standard potential supply and adjacent other electrodes. Two transfer MOS transistors of a first conductivity type and two driver MOS transistors are provided. A conductive layer for fixing the source potential of the driver MOS transistors to standard potential is so disposed above the transfer and driver MOS transistors as to the wholly cover the memory cell. Separation is carried out by using a photo-mask having an optically transparent substrate provided within the same transmissive portion with a pattern of a plurality of so-called phase shifter regions for inversion of the phase of transmitting light.

Abstract: A local interconnect comprises a doped, silicided amorphous or polysilicon layer 28. One interconnect 34, 35 extends between an isolated gate contact 60 and a source and drain 61 of an NMOS transistor 42. Another local interconnect 34,37 extends between a source and a drain 62, 63 of CMOS transistors.

Abstract: A new class of CMOS integrated circuits, wherein the PMOS and NMOS devices are both configured as vertical transistors. One trench can contain a PMOS device, an NMOS device, and a gate which is coupled to control both the PMOS device and the NMOS device. Latchup problems do not arise, and n+ to p+ spacing rules are not required.

Abstract: A method of making a silicided inverse T-gate with an L-shaped silicon spacer and nitride sidewall spacers is described. The L-shaped spacer is electrically connected to the gate.

Abstract: A semiconductor device includes a bipolar transistor and an IIL element fabricated on a single wafer. The emitter region of the bipolar transistor is formed by diffusing the impurity of an impurity layer formed in contact with the base region therein. The impurity layer is formed of a polycide layer formed of a polysilicon layer doped with an impurity and a metal silicide layer laminated on the polysilicon layer, a laminated layer of a polysilicon layer and a refractory metal layer, or a metal silicide layer.

Abstract: A method for producing a semiconductor device in which an electrode and an impurity-diffused layer formed on a semiconductor substrate are electrically connected to each other, includes the following steps: forming a first insulating film on the semiconductor substrate; forming a first mask layer on the first insulating film, and forming a second mask layer on the first mask layer, the first mask layer comprising a first opening for exposing a part of the surface of the semiconductor substrate, the second mask layer comprising a second opening, at least the exposed part of the surface of the semiconductor substrate being exposed by the second opening; removing at least a part of the first insulating film exposed through the first opening; implanting a first impurity into the semiconductor substrate using the second mask layer as a mask and employing an acceleration energy at which the first impurity can pass through the first mask layer; removing the second mask layer, and forming the electrode doped with a s

Abstract: A CMOS device and a method for its fabrication are disclosed. In one embodiment the CMOS device includes an NMOS transistor and a PMOS transistor each of which has silicided source and drain regions and a silicon gate electrode which includes a titanium nitride barrier layer. The NMOS transistor and PMOS transistors are coupled together by a silicon layer which is capped by a layer of titanium nitride barrier material. The source and drain regions are silicided with cobalt or other metal silicide which is prevented from reacting with the silicon gate electrode and interconnect by the presence of the titanium nitride barrier layer.

Abstract: A semiconductor device of the present invention capable of obtaining a proper output signal by absorbing an overshoot or an undershoot to reduce internal noises, comprises, a logical circuit portion including a transistor, a first diode disposed between a power line and an electrode of the logical circuit portion communicating with a power supply with its cathode being directed to the power line, and a second diode disposed between a ground line and an electrode of the logical circuit portion communicating with the ground with its anode being directed to the ground line. Another semiconductor device of the present invention includes a MOS transistor. An electrode portion of the device communicating with the power line and that of the device communicating with the ground line are formed by restricting impurity concentration of semiconductor portions in contact with the associated metal electrodes and have diode effect.

Abstract: A thin film transistor and method for forming the same are disclosed. The transistor comprises a gate conductor (14) and a gate insulator (16). A semiconductor channel layer (18) is formed adjacent the gate insulator (16). A mask block (22) is formed covering a channel region (30) in the channel layer (18). A source region (26) and a drain region (28) are formed in the channel layer (18) adjacent opposite ends of the mask block (22). Conductive bodies (32) and (34) are formed in contact with source region (26) and drain region (28), respectively. Electric contacts (42) and (44) are then formed in contact with conductive bodies (32) and (34), respectively.

Abstract: Disclosed herein is a thin film field effect transistor and a method for producing such a thin film transistor. The thin film transistor has a transistor gate and thin film active and channel regions. The transistor gate has a top surface and sidewalls which are coated with a thin gate insulating layer. A thin semiconductor film is provided over the transistor gate and thin gate insulating layer to form a conductively doped thin film channel region and conductively doped thin film active regions. The thin film channel region contacts the thin gate insulating layer opposite the transistor gate top surface and opposite the sidewalls. The transistor gate sidewalls in operation gate the opposite thin film channel region through the thin gate insulating layer. The thin film field effect transistor can be fabricated over an underlying MOSFET to form a CMOS inverter with the transistor gate being common to both the thin film transistor and the MOSFET.

Abstract: A memory cell layout achieves a reduced cell area. In one embodiment, a six transitor (6T) SRAM cell has two vertical thin-film transistors (18 and 20) as load transistors, two transfer transistors (10 and 12), two latch transistors (14 and 16), and two storage nodes. NODE 1 and NODE 2 of the cell each have a minimum feature defined by trenches (60). Four of five interconnects associated with each node are located within the respective trench. For example in NODE 1, a drain of latch transistor (14), a gate of latch transistor (16), a drain of load transistor (18), and a current electrode of transfer transistor (10) are electrically coupled within or beneath one trench (60). A remaining interconnection of NODE 1, a gate of load transistor 20, is located within the trench associated with NODE 2. Thus, ten interconnects of the memory cell are contained within areas defined by two minimum features.

Abstract: A BICMOS device and manufacturing method wherein the gates of PMOS and NMOS transistors are formed by forming a first polysilicon layer which is not implanted by an impurity and forming a second polysilicon layer on the first polysilicon layer which is impurity implanted, so that the impurity doped in the second polysilicon layer is prevented from diffusing into the channel region and the voltage characteristic is prevented from changing. Emitter regions of vertical PNP and NPN bipolar transistors are self-aligned in a small chip area, and thereby the performance of the BICMOS device is improved due to the stable threshold voltage characteristic of the PMOS and NMOS transistors and high density is achieved together with improved operation speed clue to the self-alignment formation of the emitter region of the vertical PNP and NPN bipolar transistors.

Abstract: A method for forming a BICMOS integrated circuit having MOS field-effect devices and bipolar junction transistors formed in a silicon substrate is disclosed. The process comprises the steps of first defining separate active areas in a substrate for each of the transistors. Next, a gate dielectric layer is formed over the surface of the wafer. Above the gate dielectric, a first layer of polysilicon is deposited. This first layer of polysilicon is then selectively etched to form a plurality of first polysilicon members each of which is equally-spaced apart from one another. The polysilicon members comprise the gates of the MOS transistors and the extrinsic base contacts of the NPN transistors. After the first polysilicon members have been defined, the base regions of the NPN transistors are formed. After insulating the first polysilicon members, an additional layer of polysilicon is deposited over the substrate to replanarize the entire wafer surface.

Abstract: A tunnel injection type semiconductor device having an MIS structure comprising a semiconductor region, a source, a drain and a gate electrode, wherein said source and said drain are composed of a metal or metal compound member, respectively, and wherein both have an overlapping portion with said gate electrode. A first conductivity type high impurity concentration semiconductor layer is formed in said semiconductor region in contact with and contiguous to said metalic member at the drain side. The source provides a Schottky barrier junction to said semiconductor region while said drain provides an ohmic contact to said semiconductor region. Using this structure a tunneling current flowing across a Schottky barrier junction between said source and said drain is controlled by a gate voltage.