Abstract: To provide a thin film transistor having an indium oxide-based semiconductor film which allows only a thin metal film on the semiconductor film to be selectively etched. A thin film transistor having a crystalline indium oxide semiconductor film which is composed mainly of indium oxide and contains a positive trivalent metal oxide.

Abstract: An integrated circuit includes a semiconductor substrate, a gate dielectric over the substrate, a metal gate structure over the semiconductor substrate and the gate dielectric, a dielectric film on the metal gate structure, the dielectric film comprising oxynitride combined with metal from the metal gate, and an interlayer dielectric (ILD) on either side of the metal gate structure.

Abstract: An amorphous oxide thin film containing amorphous oxide is exposed to an oxygen plasma generated by exciting an oxygen-containing gas in high frequency. The oxygen plasma is preferably generated under the condition that applied frequency is 1 kHz or more and 300 MHz or less and pressure is 5 Pa or more. The amorphous oxide thin film is preferably exposed by a sputtering method, ion-plating method, vacuum deposition method, sol-gel method or fine particle application method.

Abstract: To give stable electrical characteristics to and improve reliability of a semiconductor device including a transistor in which an oxide semiconductor film is used for a channel formation region. As a base film, an insulating film or an oxide semiconductor film is used. A single-layer metal film is formed over the base film. After that, a resist mask is formed, and etching is performed plural times. Accordingly, electrodes each including projecting portions when seen in cross-section are formed. Even when a gate insulating film over the source electrode layer and the drain electrode layer or an oxide semiconductor film has a small thickness, disconnection of the gate insulating film is unlikely to occur.

Abstract: Semiconductor devices may be configured to reduce noise in the devices. For example, a semiconductor device may be configured or made with a first doped region within a semiconductor substrate to operate as an extended drain region, a trench isolation region, a second doped region between the first doped region and the trench isolation region, wherein the trench isolation region and the second doped region may be at least partially formed within the first doped region. Additionally, or alternatively, the second doped region may be within the first doped region and at least partially surround the trench isolation region, the first and second doped regions may have the same conductivity type, and the second doped region may have a higher conductivity than the first doped region.

Abstract: In an embodiment, this invention discloses a top-drain lateral diffusion metal oxide field effect semiconductor (TD-LDMOS) device supported on a semiconductor substrate. The TD-LDMOS includes a source electrode disposed on a bottom surface of the semiconductor substrate. The TD-LDMOS further includes a source region and a drain region disposed on two opposite sides of a planar gate disposed on a top surface of the semiconductor substrate wherein the source region is encompassed in a body region constituting a drift region as a lateral current channel between the source region and drain region under the planar gate. The TD-LDMOS further includes at least a trench filled with a conductive material and extending vertically from the body region near the top surface downwardly to electrically contact the source electrode disposed on the bottom surface of the semiconductor substrate.

Abstract: A system and method for manufacturing a carbon layer is provided. An embodiment comprises depositing a first metal layer on a substrate, the substrate comprising carbon. A silicide is epitaxially grown on the substrate, the epitaxially growing the silicide also forming a layer of carbon over the silicide. In an embodiment the carbon layer is graphene, and may be transferred to a semiconductor substrate for further processing to form a channel within the graphene.

Abstract: A semiconductor device and a method of manufacturing a semiconductor device are provided. In a method of manufacturing a semiconductor device, a gate structure is formed on a substrate. An epitaxial layer is formed on a top surface of the substrate adjacent to the gate structure. An elevated source/drain (ESD) layer and an impurity region are formed by implanting impurities and carbon in the epitaxial layer and an upper portion of the substrate using the gate structure as an ion implantation mask. A metal silicide layer is formed on the ESD layer.

Abstract: According to one embodiment, an image sensor includes an image-sensing element region formed by arranging a plurality of image-sensing elements on a semiconductor substrate, and a logic circuit region formed in a region different from the image-sensing element region on the substrate and including a plurality of gate patterns. Further, dummy gate patterns are formed with a constant pitch on the image-sensing element region.

Abstract: Non-planar transistors and methods of fabrication thereof are described. In an embodiment, a method of forming a non-planar transistor includes forming a channel region on a first portion of a semiconductor fin, the semiconductor fin having a top surface and sidewalls. A gate electrode is formed over the channel region of the semiconductor fin, and an in-situ doped semiconductor layer is grown on the top surface and the sidewalls of the semiconductor fin on opposing sides of the gate electrode using a selective epitaxial growth process. At least a part of the doped semiconductor layer is converted to form a dopant rich region.

Abstract: Integrated circuits and methods for fabricating integrated circuits are provided. In an embodiment, a method for fabricating an integrated circuit includes providing a fin structure overlying a semiconductor substrate. The fin structure defines a fin axis extending in a longitudinal direction perpendicular to a lateral direction and has two fin sidewalls parallel to the fin axis. The method includes forming gate structures overlying the fin structure and transverse to the fin axis. Further, the method includes growing an epitaxial material on the fin structure and confining growth of the epitaxial material in the lateral direction.

Abstract: A semiconductor device includes an active region defined by a device isolation layer and including first and second sections or regions, a gate electrode extending in a first direction across the active region over a channel between the first region and the second region and including at least one first gate tab protruding in a second direction toward the first region, and first and second contact plugs. The first gate tab covers and extends along a boundary between the active region and the device isolation layer. The first contact plug is disposed over the first region, the second contact plug is disposed over the second region, and the second contact plug has an effective width, as measured in the first direction, greater than that of the first contact plug.

Abstract: The present disclosure provides a semiconductor device, which includes a compensation area which includes p-regions and n-regions, and a plurality of transistor cells on the compensation area. Each of the plurality of transistor cells includes a source region, a body region, a gate and an interlayer dielectric, and a source metallization layer arranged on the interlayer dielectric. The semiconductor device further includes an additional n-doping region that is provided on top of the n-regions between two neighboring body regions, and a source plug which fills a contact hole formed through the interlayer dielectric between the source and body region and the source metallization layer, so as to electrically connect the source and body region and the source metallization layer.

Abstract: An iridium interfacial stack (“IrIS”) and a method for producing the same are provided. The IrIS may include ordered layers of TaSi2, platinum, iridium, and platinum, and may be placed on top of a titanium layer and a silicon carbide layer. The IrIS may prevent, reduce, or mitigate against diffusion of elements such as oxygen, platinum, and gold through at least some of its layers.

Abstract: A semiconductor device includes a semiconductor substrate having a channel region therein, a gate structure above the channel region, and source and drain regions on opposite sides of the gate structure. A respective contact is on each of the source and drain regions. At least one of the source and drain regions has an inclined upper contact surface with the respective contact. The inclined upper contact surface has at least a 50% greater area than would a corresponding flat contact surface.

Abstract: A method for contacting MOS devices. First openings in a photosensitive material are formed over a substrate having a top dielectric in a first die area and a second opening over a gate stack in a second die area having the top dielectric, a hard mask, and a gate electrode. The top dielectric layer is etched to form a semiconductor contact while etching at least a portion the hard mask layer thickness over a gate contact area exposed by the second opening. An inter-layer dielectric (ILD) is deposited. A photosensitive material is patterned to generate a third opening in the photosensitive material over the semiconductor contact and a fourth opening inside the gate contact area. The ILD is etched through to reopen the semiconductor contact while etching through the ILD and residual hard mask if present to provide a gate contact to the gate electrode.

Abstract: A semiconductor device fabrication process includes forming insulating mandrels over replacement metal gates on a semiconductor substrate with first gates having sources and drains and at least one second gate being isolated from the first gates. Mandrel spacers are formed around each insulating mandrel. The mandrels and mandrel spacers include the first insulating material. A second insulating layer of the second insulating material is formed over the transistor. One or more first trenches are formed to the sources and drains of the first gates by removing the second insulating material between the insulating mandrels. A second trench is formed to the second gate by removing portions of the first and second insulating materials above the second gate. The first trenches and the second trench are filled with conductive material to form first contacts to the sources and drains of the first gates and a second contact to the second gate.

Abstract: A semiconductor structure and method of manufacturing the same are provided. The semiconductor structure includes a semiconductor substrate having an isolated area comprising a first region and a second region. A first raised RSD region is formed in the first region and a second RSD region is formed in the second region. The first RSD region and second RSD region is separated laterally by a portion of the isolated area. A continuous silicide interconnect structure is formed overlying the first RSD region, the second RSD region and the portion of the isolated area situated between RSD regions. A contact may be formed on the surface of the silicide interconnect.

Abstract: A method of fabricating a CMOS integrated circuit (IC) includes implanting a first n-type dopant at a first masking level that exposes a p-region of a substrate surface having a first gate stack thereon to form NLDD regions for forming n-source/drain extension regions for at least a portion of a plurality of n-channel MOS (NMOS) transistors on the IC. A p-type dopant is implanted at a second masking level that exposes an n-region in the substrate surface having a second gate stack thereon to form PLDD regions for at least a portion of a plurality of p-channel MOS (PMOS) transistors on the IC. A second n-type dopant is retrograde implanted including through the first gate stack to form a deep nwell (DNwell) for the portion of NMOS transistors. A depth of the DNwell is shallower below the first gate stack as compared to under the NLDD regions.

Abstract: An integrated circuit (IC) including a well region of the IC having a first doping level and a plurality of semiconductor regions implanted in the well region. Each of the plurality of semiconductor regions has a second doping level. The second doping level is greater than the first doping level. A plurality of polysilicon regions are arranged on the plurality of semiconductor regions. The polysilicon regions are respectively connected to the semiconductor regions. The plurality of semiconductor regions is a drain of a metal-oxide semiconductor field-effect transistor (MOSFET).

Abstract: A transistor includes a substrate, a gate over the substrate, a source and a drain over the substrate on opposite sides of the gate, a first silicide on the source, and a second silicide on the drain. Only one of the drain or the source has an unsilicided region adjacent to the gate to provide a resistive region.

Abstract: The present description relates to the field of fabricating microelectronic devices having non-planar transistors. Embodiments of the present description relate to the formation of source/drain contacts within non-planar transistors, wherein a titanium-containing contact interface may be used in the formation of the source/drain contact with a discreet titanium silicide formed between the titanium-containing interface and a silicon-containing source/drain structure.

Abstract: Gate to contact shorts are reduced by forming dielectric caps in replaced gate structures. Embodiments include forming a replaced gate structure on a substrate, the replaced gate structure including an ILD having a cavity, a first metal on a top surface of the ILD and lining the cavity, and a second metal on the first metal and filling the cavity, planarizing the first and second metals, forming an oxide on the second metal, removing the oxide, recessing the first and second metals in the cavity, forming a recess, and filling the recess with a dielectric material. Embodiments further include dielectric caps having vertical sidewalls, a trapezoidal shape, a T-shape, or a Y-shape.

Abstract: A switching device includes a substrate; a first electrode formed over the substrate; a second electrode formed over the first electrode; a switching medium disposed between the first and second electrode; and a nonlinear element disposed between the first and second electrodes and electrically coupled in series to the first electrode and the switching medium. The nonlinear element is configured to change from a first resistance state to a second resistance state on application of a voltage greater than a threshold.

Abstract: A semiconductor device includes a semiconductor substrate; a gate stack overlying the substrate, a spacer formed on sidewalls of the gate stack, and a protection layer overlying the gate stack for filling at least a portion of a space surrounded by the spacer and the top surface of the gate stack. A top surface of the spacer is higher than a top surface of the gate stack.

Abstract: Semiconductor devices are described, along with methods and systems that include them. One such device includes a diffusion region in a semiconductor material, a terminal coupled to the diffusion region, and a field plate coupled to the terminal and extending from the terminal over the diffusion region to shield the diffusion region. Additional embodiments are also described.

Abstract: A semiconductor device is disclosed. The semiconductor device includes: a substrate; a metal-oxide semiconductor (MOS) transistor disposed in the substrate; and a shallow trench isolation (STI) disposed in the substrate and around the MOS transistor, in which the STI comprises a stress material.

Abstract: A CMOS SGT manufacturing method includes a step of forming first and second fin-shaped silicon layers on a substrate, forming a first insulating film around the first and second fin-shaped silicon layers, and forming first and second pillar-shaped silicon layers; a step of forming n-type diffusion layers; a step of forming p-type diffusion layers; a step of forming a gate insulating film and first and second polysilicon gate electrodes; a step of forming a silicide in upper portions of the diffusion layers in upper portions of the first and second fin-shaped silicon layers; and a step of depositing an interlayer insulating film, exposing the first and second polysilicon gate electrodes, etching the first and second polysilicon gate electrodes, and then depositing a metal to form first and second metal gate electrodes.

Abstract: Novel processing methods for production of high-refractive index contrast and low loss optical waveguides are disclosed. In one embodiment, a “channel” waveguide is produced by first depositing a lower cladding material layer with a low refractive index on a base substrate, a refractory metal layer, and a top diffusion barrier layer. Then, a trench is formed with an open surface to the refractory metal layer. The open surface is subsequently oxidized to form an oxidized refractory metal region, and the top diffusion barrier layer and the non-oxidized refractory metal region are removed. Then, a low-refractive-index top cladding layer is deposited on this waveguide structure to encapsulate the oxidized refractory metal region. In another embodiment, a “ridge” waveguide is produced by using similar process steps with an added step of depositing a high-refractive-index material layer and an optional optically-transparent layer.

Abstract: A semiconductor device includes a source metallization and a semiconductor body. The semiconductor body includes a first field-effect structure including a source region of a first conductivity type electrically coupled to the source metallization and a second field-effect structure including a source region of the first conductivity type electrically coupled to the source metallization. A first gate electrode of the first field-effect structure is electrically coupled to a first gate driver circuit and a second gate electrode of the second field-effect structure is electrically coupled to a second gate driver circuit different from the first gate driver circuit. The first field-effect structure and the second field-effect structure share a common drain.

Abstract: The present invention provides a method for manufacturing a semiconductor structure, comprising: forming a first contact layer on an exposed active region of a first spacer; forming a second spacer at a region of the first contact layer close to a gate stack to partially cover the exposed active region; forming a second contact layer in the uncovered exposed active region, wherein when a diffusion coefficient of the first contact layer is the same as that of the second contact layer, the first contact layer has a thickness less than that of the second contact layer; and when the diffusion coefficient of the first contact layer is different from that of the second contact layer, the diffusion coefficient of the first contact layer is smaller than that of the second contact layer. Correspondingly, the present invention also provides a semiconductor structure.

Abstract: A device formed from a method of fabricating a fine metal silicide layer having a uniform thickness regardless of substrate doping. A planar vacancy is created by the separation of an amorphousized surface layer of a silicon substrate from an insulating layer, a metal source enters the vacancy through a contact hole through the insulating later connecting with the vacancy, and a heat treatment converts the metal in the vacancy into metal silicide. The separation is induced by converting the amorphous silicon into crystalline silicon.

Abstract: Semiconductor devices, transistors, and methods of manufacture thereof are disclosed. In one embodiment, a semiconductor device includes a gate dielectric disposed over a workpiece, a gate disposed over the gate dielectric, and a spacer disposed over sidewalls of the gate and the gate dielectric. A source region is disposed proximate the spacer on a first side of the gate, and a drain region is disposed proximate the spacer on a second side of the gate. A metal layer is disposed over the source region and the drain region. The metal layer extends beneath the spacers by about 25% or greater than a width of the spacers.

Abstract: Disclosed are methods for manufacturing floating gate memory devices and the floating gate memory devices thus manufactured. In one embodiment, the method comprises providing a monocrystalline semiconductor substrate, forming a tunnel oxide layer on the substrate, and depositing a protective layer on the tunnel oxide layer to form a stack of the tunnel oxide layer and the protective layer. The method further includes forming at least one opening in the stack, thereby exposing at least one portion of the substrate, and cleaning the at least one exposed portion with a cleaning liquid. The method still further includes loading the substrate comprising the stack into a reactor and, thereafter, performing an in-situ etch to remove the protective layer, using the at least one exposed portion as a source to epitaxially grow a layer comprising the monocrystalline semiconductor material, and forming the layer into at least one columnar floating gate structure.

Abstract: Techniques for forming a smooth silicide without the use of a cap layer are provided. In one aspect, a FET device is provided. The FET device includes a SOI wafer having a SOI layer over a BOX and at least one active area formed in the wafer; a gate stack over a portion of the at least one active area which serves as a channel of the device; source and drain regions of the device adjacent to the gate stack, wherein the source and drain regions of the device include a semiconductor material selected from: silicon and silicon germanium; and silicide contacts to the source and drain regions of the device, wherein an interface is present between the silicide contacts and the semiconductor material, and wherein the interface has an interface roughness of less than about 5 nanometers.

Abstract: A fin field-effect transistor structure comprises a substrate, a fin channel, a source/drain region, a high-k metal gate and a plurality of slot contact structures. The fin channel is formed on the substrate. The source/drain region is formed in the fin channel. The high-k metal gate formed on the substrate and the fin channel comprises a high-k dielectric layer and a metal gate layer, wherein the high-k dielectric layer is arranged between the metal gate layer and the fin channel. The slot contact structures are disposed at both sides of the metal gate.

Abstract: Elongated metal contacts with longitudinal axes that lie in a first direction are formed to make electrical connections to elongated source and drain regions with longitudinal axes that lie in the first direction, and elongated metal contacts with longitudinal axes that lie a second direction are formed to make electrical connections to elongated source and drain regions with longitudinal axes that lie the second direction, where the second direction lies orthogonal to the first direction.

Abstract: An integrated circuit configuration includes a substrate, a diffusion region, a gate structure, an extension conductor structure, a dielectric layer, a contact structure, and a metal conductor line. The diffusion region is formed in the substrate. The gate structure is formed over the substrate and spanned across the diffusion region. The extension conductor structure is formed over the semiconductor substrate and contacted with the diffusion region. The extension conductor structure is extended externally to a first position along a surface of the substrate, wherein the first position is outside the diffusion region. The dielectric layer is formed over the substrate, the gate structure and the extension conductor structure. The contact structure is penetrated through the dielectric layer to be contacted with the first position of the extension conductor structure. The metal conductor line is formed on the dielectric layer and contacted with the contact structure.

Abstract: A lateral bipolar junction transistor includes an emitter region; a base region surrounding the emitter region; a gate disposed at least over a portion of the base region; and a collector region surrounding the base region; wherein the portion of the base region under the gate does not under go a threshold voltage implant process.

Abstract: A method of manufacturing a semiconductor structure, which comprises the steps of: providing a substrate, forming a fin on the substrate, which comprises a central portion for forming a channel and an end portion for forming a source/drain region and a source/drain extension region; forming a gate stack to cover the central portion of the fin; performing light doping to form a source/drain extension region in the end portion of the fin; forming a spacer on sidewalls of the gate stack; performing heavy doping to form a source/drain region in the end portion of the fin; removing at least a part of the spacer to expose at least a part of the source/drain extension region; forming a contact layer on an upper surface of the source/drain region and an exposed area of the source/drain extension region. Correspondingly, the present invention also provides a semiconductor structure.

Abstract: The invention provides a semiconductor device that is thermally isolated from the printed circuit board such that the device operates at a higher temperature and radiates heat away from the printed circuit board. In another embodiment, the semiconductor is stacked onto a second device and optionally thermally isolated from the second device.

Abstract: The invention provides a semiconductor device comprising: a substrate; a gate, which is formed on the substrate; a source and a drain, which are located on opposite sides of the gate, respectively; a contact, which contacts with the source and/or the drain, wherein the contact has an enlarged end at an end which is in contact with the source and/or the drain. In the present invention, since the contact area of the contact is increased on the interface in contact with the source/the drain, the contact resistance can be reduced, and thus the performances of the semiconductor device can be guaranteed/improved. The present invention further provides a method of fabricating the semiconductor device (especially the contact therein) as previously described.

Abstract: Methods and associated structures of forming a microelectronic device are described. Those methods may include forming a structure comprising a first contact metal disposed on a source/drain contact of a substrate, and a second contact metal disposed on a top surface of the first contact metal, wherein the second contact metal is disposed within an IID disposed on a top surface of a metal gate disposed on the substrate.

Abstract: Each gate structure formed on the substrate includes a gate dielectric, a gate conductor, a first etch stop layer, and a gate cap dielectric. A second etch stop layer is formed over the gate structures, gate spacers, and source and drain regions. A first contact-level dielectric layer and a second contact-level dielectric layer are formed over the second etch stop layer. Gate contact via holes extending at least to the top surface of the gate cap dielectrics are formed. Source/drain contact via holes extending to the interface between the first and second contact-level dielectric layers are subsequently formed. The various contact via holes are vertically extended by simultaneously etching exposed gate cap dielectrics and exposed portions of the first contact-level dielectric layer, then by simultaneously etching the first and second etch stop layers. Source/drain contact vias self-aligned to the outer surfaces gate spacers are thereby formed.

Abstract: A semiconductor device, comprising a substrate, a plurality of polysilicon portions formed on the substrate, wherein the polysilicon portions are spaced apart from each other, a plurality of source/drain regions formed in the substrate between adjacent polysilicon portions, and a dielectric layer formed on the polysilicon portions and on the source/drain regions, wherein the dielectric layer includes a cavity filled with conductive material to form a contact area, the contact area overlapping part of a source/drain region and part of a polysilicon portion to electrically connect the polysilicon portion with the source/drain region, and wherein part of the contact area extends below an upper surface of the substrate to contact an implant region with the same doping as the source/drain region. The implant region is next to the source/drain region and includes part of a channel region in the substrate under the polysilicon portion.

Abstract: A CMOS SGT manufacturing method includes a step of forming first and second fin-shaped silicon layers on a substrate, forming a first insulating film around the first and second fin-shaped silicon layers, and forming first and second pillar-shaped silicon layers; a step of forming n-type diffusion layers; a step of forming p-type diffusion layers; a step of forming a gate insulating film and first and second polysilicon gate electrodes; a step of forming a silicide in upper portions of the diffusion layers in upper portions of the first and second fin-shaped silicon layers; and a step of depositing an interlayer insulating film, exposing the first and second polysilicon gate electrodes, etching the first and second polysilicon gate electrodes, and then depositing a metal to form first and second metal gate electrodes.

Abstract: A manufacturing method of a semiconductor device comprises the following steps. First, a substrate is provided, at least one fin structure is formed on the substrate, and a metal layer is then deposited on the fin structure to form a salicide layer. After depositing the metal layer, the metal layer is removed but no RTP is performed before the metal layer is removed. Then a RTP is performed after the metal layer is removed.

Abstract: A semiconductor memory device includes a plurality of memory blocks formed over a substrate including source regions and separated from each other by a slit, a plurality of bit lines coupled to the strings of the memory blocks and disposed over the memory blocks, and source contact lines formed within the slits, coupled to the source regions, respectively, and disposed in a direction to cross the plurality of bit lines.

Abstract: A storage node may include a lower electrode, a phase change layer on the lower electrode and an upper electrode on the phase change layer, and the lower electrode and the upper electrode may be composed of thermoelectric materials having a melting point higher than that of the phase change layer, and having different conductivity types. An upper surface of the lower electrode may have a recessed shape, and a lower electrode contact layer may be provided between the lower electrode and the phase change layer.

Abstract: The disclosure relates to spacer structures of a semiconductor device. An exemplary structure for a semiconductor device comprises a substrate having a first active region and a second active region; a plurality of first gate electrodes having a gate pitch over the first active region, wherein each first gate electrode has a first width; a plurality of first spacers adjoining the plurality of first gate electrodes, wherein each first spacer has a third width; a plurality of second gate electrodes having the same gate pitch as the plurality of first gate electrodes over the second active region, wherein each second gate electrode has a second width greater than the first width; and a plurality of second spacers adjoining the plurality of second gate electrodes, wherein each second spacer has a fourth width less than the third width.