Gate Electrode Consists Of Refractory Or Platinum Group Metal Or Silicide Patents (Class 257/388)
  • Patent number: 10490673
    Abstract: A microelectronic device includes a gated graphene component. The gated graphene component has a graphitic layer containing one or more layers of graphene. The graphitic layer has a channel region, a first contact region adjacent to the channel region and a second contact region adjacent to the channel region. A patterned hexagonal boron nitride (hBN) layer is disposed on the graphitic layer above the channel region. A gate is located over the patterned hBN layer above the channel region. A first connection is disposed on the graphitic layer in the first contact region, and a second connection is disposed on the graphitic layer in the second contact region. The patterned hBN layer does not extend completely under the first connection or under the second connection. A method of forming the gated graphene component in the microelectronic device is disclosed.
    Type: Grant
    Filed: March 2, 2018
    Date of Patent: November 26, 2019
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Archana Venugopal, Luigi Colombo
  • Patent number: 10483112
    Abstract: Gate stacks for improving integrated circuit device performance and methods for fabricating such gate stacks are disclosed herein. An exemplary method includes forming a gate stack over a substrate and at least partially removing the gate stack, thereby forming an opening. A multi-function layer is deposited in the opening and a work function layer is deposited over the multi-function layer. The multi-function layer includes nitrogen and one of titanium or tantalum. The work function layer includes nitrogen and one of titanium or tantalum. A concentration of the nitrogen of the work function layer is different than a concentration of the nitrogen of the multi-function layer. In some implementations, the concentration of the nitrogen of the work function layer from about 2% to about 5% and the concentration of the nitrogen of the multi-function layer from about 5% to about 15%.
    Type: Grant
    Filed: July 23, 2018
    Date of Patent: November 19, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD
    Inventors: Shiu-Ko Jangjian, Ting-Chun Wang, Chi-Cherng Jeng, Chi-Wen Liu
  • Patent number: 10438856
    Abstract: Methods and devices for enhancing mobility of charge carriers. An integrated circuit may include semiconductor devices of two types. The first type of device may include a metallic gate and a channel strained in a first manner. The second type of device may include a metallic gate and a channel strained in a second manner. The gates may include, collectively, three or fewer metallic materials. The gates may share a same metallic material. A method of forming the semiconductor devices on an integrated circuit may include depositing first and second metallic layers in first and second regions of the integrated circuit corresponding to the first and second gates, respectively.
    Type: Grant
    Filed: April 3, 2013
    Date of Patent: October 8, 2019
    Assignee: STMICROELECTRONICS, INC.
    Inventors: John H. Zhang, Chengyu Niu, Heng Yang
  • Patent number: 9978640
    Abstract: A method of manufacturing a semiconductor device includes fabricating a transistor, surrounding a gate of the transistor with a spacer, and applying an oxidation operation to a conductive item, e.g., a residue from the fabrication of the gate of the transistor, that extends through the spacer. As such, the occurrence of leak paths in the semiconductor device is reduced.
    Type: Grant
    Filed: April 1, 2016
    Date of Patent: May 22, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventor: Guan-Jie Shen
  • Patent number: 9853021
    Abstract: A method for fabricating semiconductor device includes the steps of: forming a first fin-shaped structure on a substrate; forming a shallow trench isolation (STI) adjacent to the first fin-shaped structure; and forming a gate structure on the first fin-shaped structure and the STI. Preferably, the gate structure comprises a left portion and the right portion and the work functions in the left portion and the right portion are different.
    Type: Grant
    Filed: June 6, 2017
    Date of Patent: December 26, 2017
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Kuan-Ti Wang, Ling-Chun Chou, Kun-Hsien Lee
  • Patent number: 9728620
    Abstract: The present disclosure provides a semiconductor device including a metal gate structure and formation method thereof. The semiconductor device includes a substrate and a dielectric layer disposed on the substrate. The dielectric layer includes a trench. A diffusion barrier layer is disposed over a bottom surface and sidewall surfaces of the trench in the dielectric layer. The diffusion barrier layer includes at least a titanium-nitride stacked layer. The titanium-nitride stacked layer includes a TiNx layer disposed over the bottom surface and the sidewall surfaces of the trench, a TiN layer on the TiNx layer, and a TiNy layer on the TiN layer, x<1 and y>1. A metal gate is filled in the trench and disposed on the diffusion barrier layer.
    Type: Grant
    Filed: August 20, 2015
    Date of Patent: August 8, 2017
    Assignee: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATION
    Inventor: Ming Zhou
  • Patent number: 9704988
    Abstract: A transistor may include a source region and a drain region separately formed in a substrate, a trench defined in the substrate between the source region and the drain region, and a buried gate electrode formed. The buried gate electrode includes a high work function liner layer having a bottom portion which is positioned over a bottom of the trench and sidewall portions which are positioned on lower sidewalls of the trench; a low work function liner layer positioned on upper sidewalls of the trench, and overlapping with the source region and the drain region; and a low resistance layer contacting the high work function liner layer and the low work function liner layer, and partially filling the trench.
    Type: Grant
    Filed: July 2, 2014
    Date of Patent: July 11, 2017
    Assignee: SK Hynix Inc.
    Inventor: Tae-Kyung Oh
  • Patent number: 9484411
    Abstract: A method to design an IC is disclosed to provide a uniform deposition of strain-inducing composites is disclosed. The method to design the IC comprises, determining a total strain-inducing deposition area on an IC design. Then, the total strain inducing deposition area is compared with a predefined size. A dummy diffusion area is modified to increase the total strain-inducing deposition area, when the total strain-inducing deposition area is below the predefined size. Finally, the strain-inducing deposition area is optimized. A method to manufacture the IC and the IC is also disclosed.
    Type: Grant
    Filed: June 17, 2014
    Date of Patent: November 1, 2016
    Assignee: Altera Corporation
    Inventors: Girish Venkitachalam, Che Ta Hsu, Fangyun Richter, Peter J. McElheny
  • Patent number: 9324710
    Abstract: A semiconductor structure with improved gate planarity and method of fabrication are provided. In a replacement gate scheme, an array of sacrificial gate structures of substantially uniform pitch and spacing formed over a semiconductor substrate is removed and replaced with functional gate structures. Portions of functional gate structures that are accounted as extraneous features in a circuit design are subsequently removed and the removed portions of the functional gate structures are filled with a dielectric material. Because the functional gate structures of substantially uniform pitch and spacing are formed before removal of unwanted portions of the functional gate structures, the chemical mechanical polishing process can be accomplished uniformly across the semiconductor substrate. The functional gate structures thus formed have a substantially uniform height across the substrate.
    Type: Grant
    Filed: February 24, 2014
    Date of Patent: April 26, 2016
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventor: Effendi Leobandung
  • Patent number: 9312352
    Abstract: A method for fabricating a field-effect transistor is provided. The method includes: forming a gate dielectric layer and a barrier layer on a substrate in sequence; forming a first silicon layer on and in contact with the barrier layer; performing a thermal treatment to form a silicide layer between the barrier layer and the first silicon layer; and forming a second silicon layer on and in contact with the first silicon layer.
    Type: Grant
    Filed: October 2, 2015
    Date of Patent: April 12, 2016
    Assignee: UNITED MICROELECTRONICS CORPORATION
    Inventors: Kun-Yuan Lo, Chih-Wei Yang, Cheng-Guo Chen, Rai-Min Huang, Jian-Cun Ke
  • Patent number: 9275904
    Abstract: A method for fabricating a semiconductor device, including forming gate patterns over a substrate, forming conductive layer covering top and sidewalls of each gate pattern, forming a metal layer for a silicidation process over the conductive layer, and silicifying the conductive layer and the gate patterns using the metal layer.
    Type: Grant
    Filed: November 9, 2009
    Date of Patent: March 1, 2016
    Assignee: Hynix Semiconductor Inc.
    Inventors: Sung-Jin Whang, Moon-Sig Joo, Yong-Seok Eun, Kwon Hong, Bo-Min Seo, Kyoung-Eun Chang, Seung-Woo Shin
  • Patent number: 9263277
    Abstract: The disclosure relates to integrated circuit fabrication, and more particularly to a metal gate structure. An exemplary structure for a semiconductor device comprises a substrate comprising an isolation region separating and surrounding both a P-active region and an N-active region; a P-work function metal layer in a P-gate structure over the P-active region, wherein the P-work function metal layer comprises a first bottom portion and first sidewalls, wherein the first bottom portion comprises a first layer of metallic compound with a first thickness; and an N-work function metal layer in an N-gate structure over the N-active region, wherein the N-work function metal layer comprises a second bottom portion and second sidewalls, wherein the second bottom portion comprises a second layer of the metallic compound with a second thickness less than the first thickness.
    Type: Grant
    Filed: August 30, 2012
    Date of Patent: February 16, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Pei-Shan Chien, Andrew Joseph Kelly
  • Patent number: 9219125
    Abstract: A semiconductor device having five gate stacks on different regions of a substrate and methods of making the same are described. The device includes a semiconductor substrate and isolation features to separate the different regions on the substrate. The different regions include a p-type field-effect transistor (pFET) core region, an input/output pFET (pFET IO) region, an n-type field-effect transistor (nFET) core region, an input/output nFET (nFET IO) region, and a high-resistor region.
    Type: Grant
    Filed: April 11, 2014
    Date of Patent: December 22, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Po-Nien Chen, Jin-Aun Ng, Ming Zhu, Bao-Ru Young, Harry-Hak-Lay Chuang
  • Patent number: 9029253
    Abstract: Nitrogen-containing phase-stabilized films, methods of forming phase-stabilized films, and structures and devices including the phase-stabilized films are disclosed. The phase-stabilized films include a matrix material and a phase stabilizer, which provides a morphologically stabilizing effect to a matrix material within the films. The phase-stabilized films may be used as, for example, gate electrodes and similar films in microelectronic devices.
    Type: Grant
    Filed: May 1, 2013
    Date of Patent: May 12, 2015
    Assignee: ASM IP Holding B.V.
    Inventors: Robert Brennan Milligan, Fred Alokozai
  • Patent number: 8901670
    Abstract: A method of forming a semiconductor device is provided that in some embodiments encapsulates a gate silicide in a continuous encapsulating material. By encapsulating the gate silicide in the encapsulating material, the present disclosure substantially eliminates shorting between the gate structure and the interconnects to the source and drain regions of the semiconductor device.
    Type: Grant
    Filed: September 5, 2012
    Date of Patent: December 2, 2014
    Assignee: International Business Machines Corporation
    Inventors: Sivananda K. Kanakasabapathy, Hemanth Jagannathan, Soon-Cheon Seo
  • Patent number: 8900899
    Abstract: Novel processing methods for production of high-refractive index contrast and low loss optical waveguides are disclosed. In one embodiment, a “channel” waveguide is produced by first depositing a lower cladding material layer with a low refractive index on a base substrate, a refractory metal layer, and a top diffusion barrier layer. Then, a trench is formed with an open surface to the refractory metal layer. The open surface is subsequently oxidized to form an oxidized refractory metal region, and the top diffusion barrier layer and the non-oxidized refractory metal region are removed. Then, a low-refractive-index top cladding layer is deposited on this waveguide structure to encapsulate the oxidized refractory metal region. In another embodiment, a “ridge” waveguide is produced by using similar process steps with an added step of depositing a high-refractive-index material layer and an optional optically-transparent layer.
    Type: Grant
    Filed: June 28, 2013
    Date of Patent: December 2, 2014
    Inventor: Payam Rabiei
  • Patent number: 8809962
    Abstract: Scaled transistors with reduced parasitic capacitance are formed by replacing a high-k dielectric sidewall spacer with a SiO2 or low-k dielectric sidewall spacer. Embodiments include transistors comprising a trench silicide layer spaced apart from a replacement metal gate electrode, and a layer of SiO2 or low-k material on a side surface of the replacement metal gate electrode facing the trench silicide layer. Implementing methodologies may include forming an intermediate structure comprising a removable gate with nitride spacers, removing the removable gate, forming a layer of high-k material on the nitride spacers, forming a layer of metal nitride on the high-k material, filling the opening with insulating material and then removing a portion thereof to form a recess, removing the metal nitride layers and layers of high-k material, depositing a layer of SiO2 or low-k material, and forming a replacement metal gate in the remaining recess.
    Type: Grant
    Filed: August 26, 2011
    Date of Patent: August 19, 2014
    Assignees: GlobalFoundries Inc., GlobalFoundries Singapore Pte. Ltd., International Business Machines Corporation
    Inventors: Yanxiang Liu, Jinping Liu, Min Dai, Xiaodong Yang
  • Patent number: 8786027
    Abstract: In sophisticated semiconductor devices, replacement gate approaches may be applied in combination with a process strategy for implementing a strain-inducing semiconductor material, wherein superior proximity of the strain-inducing semiconductor material and/or superior robustness of the replacement gate approach may be achieved by forming the initial gate electrode structures with superior uniformity and providing at least one cavity for implementing the strained channel regions in a very advanced manufacturing stage, i.e., after completing the basic transistor configuration.
    Type: Grant
    Filed: May 3, 2013
    Date of Patent: July 22, 2014
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Uwe Griebenow, Jan Hoentschel, Thilo Scheiper, Sven Beyer
  • Patent number: 8779438
    Abstract: An AlN buffer layer, an undoped GaN layer, an undoped AlGaN layer, a p-type GaN layer and a heavily doped p-type GaN layer are formed in this order. A gate electrode forms an Ohmic contact with the heavily doped p-type GaN layer. A source electrode and a drain electrode are provided on the undoped AlGaN layer. A pn junction is formed in a gate region by a two dimensional electron gas generated at an interface between the undoped AlGaN layer and the undoped GaN layer and the p-type GaN layer, so that a gate voltage can be increased.
    Type: Grant
    Filed: August 7, 2012
    Date of Patent: July 15, 2014
    Assignee: Panasonic Corporation
    Inventors: Masahiro Hikita, Tetsuzo Ueda, Manabu Yanagihara, Yasuhiro Uemoto, Tsuyoshi Tanaka
  • Patent number: 8766372
    Abstract: Methods of fabricating a first contact to a semiconductor device, which fundamentally comprises providing a semiconductor device formed on a substrate. The substrate further includes a conductive surface. A dielectric layer is formed over the substrate and has an opening exposing the conductive surface. The opening extends an entire length of the semiconductor device, partway down the entire length of the device, extending from the device onto adjacent field of the device, or and a combination thereof. A barrier layer is formed within the opening. A copper containing material fills the opening to form a first contact to the semiconductor device.
    Type: Grant
    Filed: August 7, 2012
    Date of Patent: July 1, 2014
    Assignee: Intel Corporation
    Inventors: Kelin J. Kuhn, Kaizad Mistry, Mark Bohr, Chris Auth
  • Patent number: 8735983
    Abstract: Metal-oxide-semiconductor transistors are provided. A metal-oxide-semiconductor transistor may be formed on a semiconductor substrate. Source and drain regions may be formed in the substrate. A gate insulator such as a high-K dielectric may be formed between the source and drain regions. A gate may be formed from multiple gate conductors. The gate conductors may be metals with different workfunctions. A first of the gate conductors may form a pair of edge gate conductors that are adjacent to dielectric spacers. An opening between the edge gate conductors may be filled with the second gate conductor to form a center gate conductor. A self-aligned gate formation process may be used in fabricating the metal-oxide-semiconductor transistor.
    Type: Grant
    Filed: November 26, 2008
    Date of Patent: May 27, 2014
    Assignee: Altera Corporation
    Inventors: Jun Liu, Albert Ratnakumar, Qi Xiang, Jeffrey Xiaoqi Tung
  • Patent number: 8735888
    Abstract: An embodiment of the invention relates to a TFT-LCD array substrate comprising a substrate, a gate line and a data line formed on the substrate, a pixel electrode and a thin film transistor formed in a pixel region defined by the gate line and the data line, wherein the thin film transistor comprises a gate electrode, a source electrode, and a transparent drain electrode, and the transparent drain electrode is electrically connected with the pixel electrode.
    Type: Grant
    Filed: September 16, 2010
    Date of Patent: May 27, 2014
    Assignee: Beijing Boe Optoelectronics Technology Co., Ltd.
    Inventors: Wei Li, Jeong Hun Rhee
  • Patent number: 8710594
    Abstract: A semiconductor device includes a first conductive structure and a second conductive structure. The first conductive structure is formed in a first region of a substrate, and includes a first polysilicon layer pattern, a first conductive layer pattern having a resistance smaller than that of the first polysilicon layer pattern, and a first hard mask. The second conductive structure is formed in a second region of the substrate and has a thickness substantially the same as that of the first conductive structure. The second conductive structure includes a second polysilicon layer pattern, a second conductive layer pattern having a resistance smaller than that of the second polysilicon layer pattern and having a thickness different from that of the first conductive layer pattern, and a second hard mask.
    Type: Grant
    Filed: January 23, 2012
    Date of Patent: April 29, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Dae-Joong Won
  • Patent number: 8659087
    Abstract: A transistor structure of an electronic device can include a gate dielectric layer and a gate electrode. The gate electrode can have a surface portion between the gate dielectric layer and the rest of the gate electrode. The surface portion can be formed such that another portion of the gate electrode primarily sets the effective work function in the finished transistor structure.
    Type: Grant
    Filed: December 16, 2009
    Date of Patent: February 25, 2014
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Olubunmi O. Adetutu, Tien Ying Luo, Narayanan C. Ramani
  • Patent number: 8587062
    Abstract: A field effect transistor (FET) with an adjacent body contact, a SOI IC with circuits including the FETs and a method of fabricating the ICs. Device islands are formed in the silicon surface layer of a SOI wafer. Gates are defined on the wafer. Body contacts are formed in a perimeter conductive region adjacent to the gates. The body contacts may be either a silicide strap along the gate sidewall at one side of the FET or a separate contact separated from the gate by a dielectric stripe at one side of the FET. Separate contacts may be connected to a bias supply.
    Type: Grant
    Filed: March 26, 2007
    Date of Patent: November 19, 2013
    Assignee: International Business Machines Corporation
    Inventors: Jack A. Mandelman, Haining S. Yang
  • Patent number: 8581350
    Abstract: Current drive efficiency is deteriorated in the conventional FET. The FET 20 includes an electrode film 24a provided over the semiconductor substrate 10 and a stressor film 24b that is provided on the electrode film 24a and constitutes a gate electrode 24 together with the electrode film 24a. Each of the electrode film 24a and the stressor film 24b is composed of a metal, a metallic nitride or a metallic silicide. The stressor film 24b is capable of exhibiting a compressive stress over the semiconductor substrate 10.
    Type: Grant
    Filed: May 23, 2012
    Date of Patent: November 12, 2013
    Assignee: Renesas Electronics Corporation
    Inventor: Takeo Matsuki
  • Patent number: 8569837
    Abstract: A semiconductor structure includes a semiconductor substrate; a gate dielectric over the semiconductor substrate; a gate electrode over the gate dielectric; a deep source/drain region adjacent the gate electrode; a silicide region over the deep source/drain region; and an elevated metallized source/drain region between the silicide region and the gate electrode. The elevated metallized source/drain region adjoins the silicide region.
    Type: Grant
    Filed: May 7, 2007
    Date of Patent: October 29, 2013
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Hsin Ko, Hung-Wei Chen, Chung-Hu Ke, Ta-Ming Kuan, Wen-Chin Lee
  • Patent number: 8482080
    Abstract: A PMOS transistor is disclosed which includes a nitrogen containing barrier to oxygen diffusion between a gate dielectric layer and a metal gate in the PMOS transistor, in combination with a low oxygen region of the metal gate in direct contact with the nitrogen containing barrier and an oxygen rich region of the metal gate above the low oxygen content metal region. The nitrogen containing barrier may be formed by depositing nitrogen containing barrier material on the gate dielectric layer or by nitridating a top region of the gate dielectric layer. The oxygen rich region of the metal gate may be formed by depositing oxidized metal on the low oxygen region of the metal gate or by oxidizing a top region of the low oxygen region of the metal gate.
    Type: Grant
    Filed: May 18, 2012
    Date of Patent: July 9, 2013
    Assignee: Texas Instruments Incorporated
    Inventors: Hiroaki Niimi, Huang-Chun Wen
  • Patent number: 8432002
    Abstract: In one embodiment a method is provided that includes providing a structure including a semiconductor substrate having at least one device region located therein, and a doped semiconductor layer located on an upper surface of the semiconductor substrate in the at least one device region. After providing the structure, a sacrificial gate region having a spacer located on sidewalls thereof is formed on an upper surface of the doped semiconductor layer. A planarizing dielectric material is then formed and the sacrificial gate region is removed to form an opening that exposes a portion of the doped semiconductor layer. The opening is extended to an upper surface of the semiconductor substrate and then an anneal is performed that causes outdiffusion of dopant from remaining portions of the doped semiconductor layer forming a source region and a drain region in portions of the semiconductor substrate that are located beneath the remaining portions of the doped semiconductor layer.
    Type: Grant
    Filed: June 28, 2011
    Date of Patent: April 30, 2013
    Assignee: International Business Machines Corporation
    Inventors: Balasubramanian S. Haran, Kangguo Cheng, Shom Ponoth, Theodorus E. Standaert, Tenko Yamashita
  • Patent number: 8405132
    Abstract: A transistor structure includes a semiconductor substrate with a first surface, a diffusion region at the first surface of the substrate, a sacrificial gate formed on the diffusion region, and insulating side walls formed adjacent to the sacrificial gate. A metal gate is formed by etching out the sacrificial gate and filling in the space between the insulating side walls with gate metals. Silicided source and drain contacts are formed over the diffusion region between the side walls of two adjacent aluminum gates. One or more oxide layers are formed over the substrate. Vias are formed in the oxide layers by plasma etching to expose the silicided source and drain contacts, which simultaneously oxidizes the aluminum gate metal. A first metal is selectively formed over the silicided contact by electroless deposition, but does not deposit on the oxidized aluminum gate.
    Type: Grant
    Filed: October 22, 2010
    Date of Patent: March 26, 2013
    Assignee: Intel Corporation
    Inventor: Peter Chang
  • Patent number: 8378428
    Abstract: The applications discloses a semiconductor device comprising a substrate having a first active region, a second active region, and an isolation region having a first width interposed between the first and second active regions; a P-metal gate electrode over the first active region and extending over at least ? of the first width of the isolation region; and an N-metal gate electrode over the second active region and extending over no more than ? of the first width. The N-metal gate electrode is electrically connected to the P-metal gate electrode over the isolation region.
    Type: Grant
    Filed: September 29, 2010
    Date of Patent: February 19, 2013
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Han-Guan Chew, Lee-Wee Teo, Ming Zhu, Bao-Ru Young, Harry-Hak-Lay Chuang
  • Patent number: 8324690
    Abstract: A composite dielectric layer including a tensile stressed nitride layer over an oxide layer serves the dual function of acting as an SMT (stress memorization technique) film while an annealing operation is carried out and then remains partially intact as it is patterned to further serve as an RPO film during a subsequent silicidation process. The composite dielectric layer covers part of a semiconductor substrate that includes a gate structure. The tensile stressed nitride layer protects the oxide layer and alleviates oxide damage during a pre-silicidation PAI (pre-amorphization implant) process. Portions of the gate structure and the semiconductor substrate not covered by the composite dielectric layer include amorphous portions that include the PAI implanted dopant impurities. A silicide material is disposed on the gate structure and portions of the semiconductor substrate not covered by the composite dielectric layer.
    Type: Grant
    Filed: August 23, 2010
    Date of Patent: December 4, 2012
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventor: Jyh-Huei Chen
  • Patent number: 8298934
    Abstract: The semiconductor structure is provided that has entirely self-aligned metallic contacts. The semiconductor structure includes at least one field effect transistor located on a surface of a semiconductor substrate. The at least one field effect transistor includes a gate conductor stack comprising a lower layer of polysilicon and an upper layer of a first metal semiconductor alloy, the gate conductor stack having sidewalls that include at least one spacer. The structure further includes a second metal semiconductor alloy layer located within the semiconductor substrate at a footprint of the at least one spacer.
    Type: Grant
    Filed: June 7, 2011
    Date of Patent: October 30, 2012
    Assignee: International Business Machines Corporation
    Inventors: Jeffery B. Maxson, Cung Do Tran, Huilong Zhu
  • Patent number: 8299542
    Abstract: A field-effect transistor is provided. The field-effect transistor includes a gate structure including a fully silicided gate material overlying a gate dielectric disposed on a substrate, the fully silicided gate material having an upper region and a lower region, wherein the lower region has a first lateral dimension in accordance with a lateral dimension of the gate dielectric, and the upper region has a second lateral dimension different from the first lateral dimension.
    Type: Grant
    Filed: January 5, 2010
    Date of Patent: October 30, 2012
    Assignee: International Business Machines Corporation
    Inventors: Zhijiong Luo, Huilong Zhu
  • Patent number: 8283732
    Abstract: Provided is a semiconductor device including a substrate, a gate insulating film which is formed on the substrate, and a gate electrode which is provided on the gate insulating film. The gate electrode includes a first metal silicide including a first metal material, and a second metal silicide including one of a second metal material and the second metal material in a contact portion between the gate insulating film and the gate electrode. The second metal silicide including the second metal material is a metal-rich silicide in which the composition ratio of the second metal material to silicon in the second metal silicide including the second metal is greater than 1.
    Type: Grant
    Filed: October 1, 2009
    Date of Patent: October 9, 2012
    Assignee: Renesas Electronics Corporation
    Inventors: Hiroshi Sunamura, Kouji Masuzaki
  • Patent number: 8278199
    Abstract: Reliability of a semiconductor element and its product yield are improved by reducing variations in the electrical characteristic of a metal silicide layer. After forming a nickel-platinum alloy film over a semiconductor substrate, by carrying out a first thermal treatment at a thermal treatment temperature of 210 to 310° C. using a heater heating device, the technique causes the nickel-platinum alloy film and silicon to react with each other to form a platinum-added nickel silicide layer in a (PtNi)2Si phase. After removing unreacted nickel-platinum alloy film, the technique carries out a second thermal treatment having the thermal treatment temperature higher than that of the first thermal treatment to form the platinum-added nickel silicide layer in a PtNiSi phase. The temperature rise rate of each thermal treatment is set to 10° C./s or more.
    Type: Grant
    Filed: September 23, 2011
    Date of Patent: October 2, 2012
    Assignee: Renesas Electronics Corporation
    Inventors: Shigenari Okada, Takuya Futase, Yutaka Inaba
  • Patent number: 8264002
    Abstract: An AlN buffer layer, an undoped GaN layer, an undoped AlGaN layer, a p-type GaN layer and a heavily doped p-type GaN layer are formed in this order. A gate electrode forms an Ohmic contact with the heavily doped p-type GaN layer. A source electrode and a drain electrode are provided on the undoped AlGaN layer. A pn junction is formed in a gate region by a two dimensional electron gas generated at an interface between the undoped AlGaN layer and the undoped GaN layer and the p-type GaN layer, so that a gate voltage can be increased.
    Type: Grant
    Filed: September 13, 2010
    Date of Patent: September 11, 2012
    Assignee: Panasonic Corporation
    Inventors: Masahiro Hikita, Tetsuzo Ueda, Manabu Yanagihara, Yasuhiro Uemoto, Tsuyoshi Tanaka
  • Patent number: 8247878
    Abstract: Disclosed are a semiconductor device with a metal gate and a method of manufacturing the same.
    Type: Grant
    Filed: May 9, 2011
    Date of Patent: August 21, 2012
    Assignee: Hynix Semiconductor Inc.
    Inventor: Jin Yul Lee
  • Patent number: 8242567
    Abstract: In order that a top surface of a gate electrode does not have sharp portions, ends of the top surface of the gate electrode are rounded before refractory metal is deposited for silicidation. This reduces intensive application of film stresses which are generated in heat treatment, enabling formation of a silicide layer with a uniform, sufficient thickness.
    Type: Grant
    Filed: May 27, 2011
    Date of Patent: August 14, 2012
    Assignee: Panasonic Corporation
    Inventors: Kenshi Kanegae, Akihiko Tsuzumitani, Atsushi Ikeda
  • Patent number: 8183644
    Abstract: The invention relates to integrated circuit fabrication, and more particularly to a metal gate structure. An exemplary structure for a CMOS semiconductor device comprises a substrate comprising a P-active region, an N-active region, and an isolation region interposed between the P- and N-active regions; a P-metal gate electrode over the P-active region, that extends over the isolation region; and an N-metal gate electrode having a first width over the N-active region, that extends over the isolation region and has a contact section in the isolation region electrically contacting the P-metal gate electrode, wherein the contact section has a second width greater than the first width.
    Type: Grant
    Filed: February 11, 2011
    Date of Patent: May 22, 2012
    Inventors: Harry Hak-Lay Chuang, Bao-Ru Young, Ming Zhu, Hui-Wen Lin, Lee-Wee Teo
  • Patent number: 8148786
    Abstract: A complementary metal oxide semiconductor integrated circuit may be formed with a PMOS device formed using a replacement metal gate and a raised source drain. The raised source drain may be formed of epitaxially deposited silicon germanium material that is doped p-type. The replacement metal gate process results in a metal gate electrode and may involve the removal of a nitride etch stop layer.
    Type: Grant
    Filed: June 29, 2009
    Date of Patent: April 3, 2012
    Assignee: Intel Corporation
    Inventors: Jack Kavalieros, Annalisa Cappellani, Justin K. Brask, Mark L. Doczy, Matthew V. Metz, Suman Datta, Chris E. Barns, Robert S. Chau
  • Patent number: 8148248
    Abstract: There is provided a semiconductor device having a metal silicide layer which can suppress the malfunction and the increase in power consumption of the device. The semiconductor device has a semiconductor substrate containing silicon and having a main surface, first and second impurity diffusion layers formed in the main surface of the semiconductor substrate, a metal silicide formed over the second impurity diffusion layer, and a silicon nitride film and a first interlayer insulation film sequentially stacked over the metal silicide. In the semiconductor device, a contact hole penetrating through the silicon nitride film and the first interlayer insulation film, and reaching the surface of the metal silicide is formed. The thickness of a portion of the metal silicide situated immediately under the contact hole is smaller than the thickness of a portion of the metal silicide situated around the contact hole.
    Type: Grant
    Filed: March 22, 2011
    Date of Patent: April 3, 2012
    Assignee: Renesas Electronics Corporation
    Inventors: Toshiaki Tsutsumi, Tomonori Okudaira, Keiichiro Kashihara, Tadashi Yamaguchi
  • Patent number: 8143676
    Abstract: A semiconductor device includes a substrate having first and second regions on a surface thereof, a first conductivity type first MISFET formed in the first region and a second conductivity type second MISFET formed in the second region. The first MISFET includes a silicon oxide film or a silicon oxynitride film formed on the surface of the substrate and a first insulating film which is formed in contact with the silicon oxide film or the silicon oxynitride film and which has a first element forming electric dipoles that reduce a threshold voltage of the first MISFET and the second MISFET includes a silicon oxide film or a silicon oxynitride film formed on the surface of the substrate, and a second insulating film which is formed in contact with the silicon oxide film or the silicon oxynitride film formed on the surface of the substrate and which has a second element forming electric dipoles in a direction opposite to that in the first MISFET.
    Type: Grant
    Filed: October 30, 2008
    Date of Patent: March 27, 2012
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Seiji Inumiya, Takuya Kobayashi, Tomonori Aoyama
  • Patent number: 8089128
    Abstract: A transistor gate forming method includes forming a first and a second transistor gate. Each of the two gates includes a lower metal layer and an upper metal layer. The lower metal layer of the first gate originates from an as-deposited material exhibiting a work function the same as exhibited in an as-deposited material from which the lower metal layer of the second gate originates. However, the first gate's lower metal layer exhibits a modified work function different from a work function exhibited by the second gate's lower metal layer. The first gate's lower metal layer may contain less oxygen and/or carbon in comparison to the second gate's lower metal layer. The first gate's lower metal layer may contain more nitrogen in comparison to the second gate's lower metal layer. The first gate may be a n-channel gate and the second gate may be a p-channel gate.
    Type: Grant
    Filed: April 15, 2009
    Date of Patent: January 3, 2012
    Assignee: Micron Technology, Inc.
    Inventors: D. V. Nirmal Ramaswamy, Ravi Iyer
  • Patent number: 8053301
    Abstract: Silicon germanium (SiGe) is epitaxially grown on a silicon channel above nFET and pFET regions of a substrate. SiGe is removed above the nFET regions. A device includes a silicon channel above the nFET regions and a SiGe channel above the pFET regions.
    Type: Grant
    Filed: March 30, 2009
    Date of Patent: November 8, 2011
    Assignee: International Business Machines Corporation
    Inventors: Daniel J. Jaeger, Michael V. Aquilino, Christopher V. Baiocco
  • Patent number: 8039378
    Abstract: To provide a technique capable of improving the reliability of a semiconductor element and its product yield by reducing the variations in the electrical characteristic of a metal silicide layer. After forming a nickel-platinum alloy film over a semiconductor substrate 1, by carrying out a first thermal treatment at a thermal treatment temperature of 210 to 310° C. using a heater heating device, the technique causes the nickel-platinum alloy film and silicon to react with each other to form a platinum-added nickel silicide layer in a (PtNi)2Si phase. Subsequently, after removing the unreacted nickel-platinum alloy film, the technique carries out a second thermal treatment having the thermal treatment temperature higher than that of the first thermal treatment to form the platinum-added nickel silicide layer in a PtNiSi phase. The temperature rise rate of the first thermal treatment is set to 10° C./s or more (for example, 30 to 250° C.
    Type: Grant
    Filed: January 23, 2009
    Date of Patent: October 18, 2011
    Assignee: Renesas Electronics Corporation
    Inventors: Shigenari Okada, Takuya Futase, Yutaka Inaba
  • Patent number: 8030718
    Abstract: The present disclosure provides a semiconductor device. The semiconductor device includes a semiconductor substrate having a source region and a drain region, defining a first dimension from the source to drain; and a gate stack disposed on the semiconductor substrate and partially interposed between the source region and the drain region. The gate stack includes a high k dielectric layer disposed on the semiconductor substrate; a first metal feature disposed on the high k dielectric layer, the first metal gate feature having a first work function and defining a second dimension parallel with the first dimension; and a second metal feature having a second work function different from the first work function and defining a third dimension parallel with the first dimension, the third dimension being less than the second dimension.
    Type: Grant
    Filed: April 15, 2009
    Date of Patent: October 4, 2011
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Huan-Tsung Huang, Shyh-Horng Yang, Yuri Masuoka, Ken-Ichi Goto
  • Patent number: 8030717
    Abstract: A disclosed semiconductor device includes a gate insulation film formed on a silicon substrate and a metal gate electrode formed in the gate insulation film, wherein the gate insulation film includes a first insulation film, a second insulation film that is formed on the first insulation film and has a greater dielectric constant than the first insulation film, and a third insulation film formed on the second insulation film.
    Type: Grant
    Filed: March 11, 2009
    Date of Patent: October 4, 2011
    Assignees: Tokyo Electron Limited, National Institute of Advanced Industrial Science and Technology
    Inventors: Koji Akiyama, Wenwu Wang
  • Patent number: 8021971
    Abstract: An integrated circuit is provided including a narrow gate stack having a width less than or equal to 65 nm, including a silicide region comprising Pt segregated in a region of the silicide away from the top surface of the silicide and towards an lower portion defined by a pulldown height of spacers on the sidewalls of the gate conductor. In a preferred embodiment, the spacers are pulled down prior to formation of the silicide. The silicide is first formed by a formation anneal, at a temperature in the range 250° C. to 450° C. Subsequently, a segregation anneal at a temperature in the range 450° C. to 550° C. The distribution of the Pt along the vertical length of the silicide layer has a peak Pt concentration within the segregated region, and the segregated Pt region has a width at half the peak Pt concentration that is less than 50% of the distance between the top surface of the silicide layer and the pulldown spacer height.
    Type: Grant
    Filed: November 4, 2009
    Date of Patent: September 20, 2011
    Assignee: International Business Machines Corporation
    Inventors: Anthony G. Domenicucci, Christian Lavoie, Ahmet S. Ozcan
  • Patent number: 8022463
    Abstract: This semiconductor device comprises a semiconductor substrate, a gate insulating film formed thereon, and a gate electrode formed through the gate insulating film on the semiconductor substrate. The first silicon nitride film is formed on the upper surface of the gate electrode, and a protection insulating film is formed on the side thereof. The second silicon nitride film is formed on the side of the protection insulating film. The third silicon nitride film is formed on the upper surface of the protection insulating film, and the bottom thereof is formed on a higher position than the bottom of the first silicon nitride film.
    Type: Grant
    Filed: July 8, 2009
    Date of Patent: September 20, 2011
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Kazunori Masuda