Abstract: A transistor gate forming method includes forming a first and a second transistor gate. Each of the two gates includes a lower metal layer and an upper metal layer. The lower metal layer of the first gate originates from an as-deposited material exhibiting a work function the same as exhibited in an as-deposited material from which the lower metal layer of the second gate originates. However, the first gate's lower metal layer exhibits a modified work function different from a work function exhibited by the second gate's lower metal layer. The first gate's lower metal layer may contain less oxygen and/or carbon in comparison to the second gate's lower metal layer. The first gate's lower metal layer may contain more nitrogen in comparison to the second gate's lower metal layer. The first gate may be a n-channel gate and the second gate may be a p-channel gate.

Abstract: Silicon germanium (SiGe) is epitaxially grown on a silicon channel above nFET and pFET regions of a substrate. SiGe is removed above the nFET regions. A device includes a silicon channel above the nFET regions and a SiGe channel above the pFET regions.

Abstract: To provide a technique capable of improving the reliability of a semiconductor element and its product yield by reducing the variations in the electrical characteristic of a metal silicide layer. After forming a nickel-platinum alloy film over a semiconductor substrate 1, by carrying out a first thermal treatment at a thermal treatment temperature of 210 to 310° C. using a heater heating device, the technique causes the nickel-platinum alloy film and silicon to react with each other to form a platinum-added nickel silicide layer in a (PtNi)2Si phase. Subsequently, after removing the unreacted nickel-platinum alloy film, the technique carries out a second thermal treatment having the thermal treatment temperature higher than that of the first thermal treatment to form the platinum-added nickel silicide layer in a PtNiSi phase. The temperature rise rate of the first thermal treatment is set to 10° C./s or more (for example, 30 to 250° C.

Abstract: The present disclosure provides a semiconductor device. The semiconductor device includes a semiconductor substrate having a source region and a drain region, defining a first dimension from the source to drain; and a gate stack disposed on the semiconductor substrate and partially interposed between the source region and the drain region. The gate stack includes a high k dielectric layer disposed on the semiconductor substrate; a first metal feature disposed on the high k dielectric layer, the first metal gate feature having a first work function and defining a second dimension parallel with the first dimension; and a second metal feature having a second work function different from the first work function and defining a third dimension parallel with the first dimension, the third dimension being less than the second dimension.

Abstract: A disclosed semiconductor device includes a gate insulation film formed on a silicon substrate and a metal gate electrode formed in the gate insulation film, wherein the gate insulation film includes a first insulation film, a second insulation film that is formed on the first insulation film and has a greater dielectric constant than the first insulation film, and a third insulation film formed on the second insulation film.

Abstract: An integrated circuit is provided including a narrow gate stack having a width less than or equal to 65 nm, including a silicide region comprising Pt segregated in a region of the silicide away from the top surface of the silicide and towards an lower portion defined by a pulldown height of spacers on the sidewalls of the gate conductor. In a preferred embodiment, the spacers are pulled down prior to formation of the silicide. The silicide is first formed by a formation anneal, at a temperature in the range 250° C. to 450° C. Subsequently, a segregation anneal at a temperature in the range 450° C. to 550° C. The distribution of the Pt along the vertical length of the silicide layer has a peak Pt concentration within the segregated region, and the segregated Pt region has a width at half the peak Pt concentration that is less than 50% of the distance between the top surface of the silicide layer and the pulldown spacer height.

Abstract: This semiconductor device comprises a semiconductor substrate, a gate insulating film formed thereon, and a gate electrode formed through the gate insulating film on the semiconductor substrate. The first silicon nitride film is formed on the upper surface of the gate electrode, and a protection insulating film is formed on the side thereof. The second silicon nitride film is formed on the side of the protection insulating film. The third silicon nitride film is formed on the upper surface of the protection insulating film, and the bottom thereof is formed on a higher position than the bottom of the first silicon nitride film.

Abstract: A method for carrying out a replacement metal gate process comprises providing a transistor in a reactor, wherein the transistor includes a gate stack, removing at least a portion of the gate stack to expose a surface of a barrier layer, causing a temperature of the reactor be less than or equal to 150° C., introducing methylpyrrolidine:alane (MPA) proximate to the surface of the barrier layer, and carrying out a CVD process to deposit aluminum metal on the barrier layer using a bottom-up deposition mechanism.

Abstract: A method for forming a semiconductor element structure is provided. First, a substrate including a first MOS and a second MOS is provided. The gate electrode of the first MOS is connected to the gate electrode of the second MOS, wherein the first MOS includes a first high-K material and a first metal for use in a first gate, and a second MOS includes a second high-K material and a second metal for use in a second gate. Then the first gate and the second gate are partially removed to form a connecting recess. Afterwards, the connecting recess is filled with a conductive material to form a bridge channel for electrically connecting the first metal and the second metal.

Abstract: A polysilicon electrode layer (103) (a first electrode layer) is formed by forming a polysilicon film on a gate oxide film (102) on a silicon wafer (101). A tungsten layer (105) (a second electrode layer) is formed on this polysilicon electrode layer (103). In addition, a barrier layer (104) is formed on the polysilicon electrode layer (103) before the formation of the tungsten layer (105). Etching is then conducted using a silicon nitride layer (106) as the etching mask. Next, an oxide insulating film (107) is formed on an exposed surface of the polysilicon layer (103) by plasma oxidation wherein a process gas containing oxygen gas and hydrogen gas is used at a process temperature not less than 300° C. With this method, a selective oxidation of the polysilicon electrode layer (103) can be carried out without oxidizing the tungsten layer (105).

Abstract: In order that a top surface of a gate electrode does not have sharp portions, ends of the top surface of the gate electrode are rounded before refractory metal is deposited for silicidation. This reduces intensive application of film stresses which are generated in heat treatment, enabling formation of a silicide layer with a uniform, sufficient thickness.

Abstract: A semiconductor device includes a gate electrode having ends that overlap isolation regions, wherein the gate electrode is located over an active region located within a semiconductor substrate. A gate oxide is located between the gate electrode and the active regions, and source/drains are located adjacent the gate electrode and within the active region. An etch stop layer is located over the gate electrode and the gate electrode has at least one electrical contact that extends through the etch stop layer and contacts a portion of the gate electrode that in one embodiment overlies the active region, and in another embodiment is less than one alignment tolerance from the active region.

Abstract: The semiconductor structure is provided that has entirely self-aligned metallic contacts. The semiconductor structure includes at least one field effect transistor located on a surface of a semiconductor substrate. The at least one field effect transistor includes a gate conductor stack comprising a lower layer of polysilicon and an upper layer of a first metal semiconductor alloy, the gate conductor stack having sidewalls that include at least one spacer. The structure further includes a second metal semiconductor alloy layer located within the semiconductor substrate at a footprint of the at least one spacer.

Abstract: Stabilized metal gate electrode for complementary metal-oxide-semiconductor (“CMOS”) applications and methods of making the stabilized metal gate electrodes are disclosed. Specifically, the metal gate electrodes are stabilized by alloying wherein the alloy comprises a metal selected from the group consisting of Re, Ru, Pt, Rh, Ni, Al and combinations thereof and an element selected from the group consisting of W, V, Ti, Ta and combinations thereof.

Abstract: Described is a CMOS transistor structure with a multi-layered gate electrode structure and a method of fabrication. The gate electrode structure has a three-layered metallic gate electrode and a polysilicon layer. The first metallic layer acts as a barrier to prevent the second metallic layer from reacting with an underlying dielectric. The second metallic layer acts to set the work function of the gate electrode structure. The third metallic layer acts as a barrier to prevent the second metallic layer from reacting with the polysilicon layer.

Abstract: There is provided a semiconductor device having a metal silicide layer which can suppress the malfunction and the increase in power consumption of the device. The semiconductor device has a semiconductor substrate containing silicon and having a main surface, first and second impurity diffusion layers formed in the main surface of the semiconductor substrate, a metal silicide formed over the second impurity diffusion layer, and a silicon nitride film and a first interlayer insulation film sequentially stacked over the metal silicide. In the semiconductor device, a contact hole penetrating through the silicon nitride film and the first interlayer insulation film, and reaching the surface of the metal silicide is formed. The thickness of a portion of the metal silicide situated immediately under the contact hole is smaller than the thickness of a portion of the metal silicide situated around the contact hole.

Abstract: A method for manufacturing a metal gate includes providing a substrate including a gate electrode located on the substrate. A plurality of layers is formed, including a first layer located on the substrate and the gate electrode and a second layer adjacent the first layer. The layers are etched to form a plurality of adjacent spacers, including a first spacer located on the substrate and adjacent the gate electrode and a second spacer adjacent the first spacer. The first spacer is then etched and a metal layer is formed on the device immediately adjacent to the gate electrode. The metal layer is then reacted with the gate electrode to form a metal gate.

Abstract: Embodiments of an integrated circuit are provided. In one embodiment, the integrated circuit includes a substrate, a short channel (SC) device, and a long channel (LC) device. The short channel device includes an SC gate insulator overlying a first portion of the substrate, an SC metal gate overlying the SC gate insulator, a polycrystalline silicon layer overlying the metal gate, and a silicide layer formed on the polycrystalline silicon layer. The long channel (LC) device includes an LC gate insulator overlying a second portion of the substrate and an LC metal gate overlying the LC gate insulator. An etch stop layer overlies an upper surface of the substrate, and an interlayer dielectric overlies an upper surface of the etch stop layer. An SC cap is disposed in the interlayer dielectric, overlies the SC device, and is formed substantially from the same metal as is the LC metal gate.

Abstract: A contact architecture for nanoscale channel devices having contact structures coupling to and extending between source or drain regions of a device having a plurality of parallel semiconductor bodies. The contact structures being able to contact parallel semiconductor bodies having sub-lithographic pitch.

Abstract: The present disclosure provides a method of fabricating a semiconductor device that includes providing a substrate having a first region and a second region, forming first and second gate stacks in the first and second regions, respectively, the first gate stack including a first dummy gate and the second gate stack including a second dummy gate, removing the first dummy gate in the first gate stack thereby forming a first trench and removing the second dummy gate in the second gate stack thereby forming a second trench, forming a first metal layer in the first trench and in the second trench, removing at least a portion of the first metal layer in the first trench, forming a second metal layer in the remainder of the first trench and in the remainder of the second trench, reflowing the second metal layer, and performing a chemical mechanical polishing (CMP).

Abstract: An SRAM device includes a first inverter; a second inverter cross-coupled with the first inverter; a first pass gate transistor connecting the first inverter to a bit line; and a second pass gate transistor connecting the second inverter to a complementary bit line, wherein the first or second pass gate transistor has a layout structure where a first distance between its gate conductive layer and its source contact is purposefully designed to be substantially different from a second distance between its gate conductive layer and its drain contact for reducing leakage current induced by misalignment of the gate conductive layer with respect to the source contact.

Abstract: Methods and structures for reducing resistance in wordlines of an integrated circuit memory device are disclosed. In one embodiment, the method includes forming multiple columns of polycrystalline silicon for respective number of wordlines, forming core transistor junctions and periphery transistor junctions associated with the wordlines, performing a salicidation process for the periphery transistor junction and performing a salicidation process for the columns of polycrystalline silicon to from the wordlines with low resistance.

Abstract: A first insulating film is formed. Then, a gate electrode of a low voltage drive thin film transistor and a mask film for covering a region constituting a channel of a high voltage drive thin film transistor are formed with a molybdenum film on the first insulating film. An impurity is implanted into a semiconductor film while using the gate electrode and the mask film as a mask, thereby forming a high density impurity region. Thereafter, the impurity is activated by performing a thermal process under a condition at 500° C. and for 2 hours, for example. Subsequently, the mask film is removed and a second insulating film is formed. A gate electrode of the high voltage drive thin film transistor is formed with an aluminum alloy on the second insulating film.

Abstract: A semiconductor device includes: a semiconductor substrate; a PFET formed on the substrate, the PFET includes a SiGe layer disposed on the substrate, a high-K dielectric layer disposed on the SiGe layer, a first metallic layer disposed on the high-k dielectric layer, a first intermediate layer disposed on the first metallic layer, a second metallic layer disposed on the first intermediate layer, a second intermediate layer disposed on the second metallic layer, and a third metallic layer disposed on the second intermediate layer; an NFET formed on the substrate, the NFET includes the high-k dielectric layer, the high-k dielectric layer being disposed on the substrate, the second intermediate layer, the second intermediate layer being disposed on the high-k dielectric layer, and the third metallic layer, the third metallic layer being disposed on the second intermediate layer. Alternatively, the first metallic layer is omitted.

Abstract: An AlN buffer layer, an undoped GaN layer, an undoped AlGaN layer, a p-type GaN layer and a heavily doped p-type GaN layer are formed in this order. A gate electrode forms an Ohmic contact with the heavily doped p-type GaN layer. A source electrode and a drain electrode are provided on the undoped AlGaN layer. A pn junction is formed in a gate region by a two dimensional electron gas generated at an interface between the undoped AlGaN layer and the undoped GaN layer and the p-type GaN layer, so that a gate voltage can be increased.

Abstract: A gate structure includes a substrate, a gate dielectric layer, a first conductive layer, a second conductive layer, a cap layer and a first insulating spacer. The gate dielectric layer is disposed on the substrate. The first conductive layer is disposed on the gate dielectric layer and has an opening. A part of the second conductive layer is disposed in the opening. The second conductive layer has an extrusion that protrudes above the opening of the first conductive layer. The extrusion has a cross-sectional width less than the width of the second conductive layer inside the opening. The cap layer is disposed on the extrusion. The first insulating spacer is disposed on a part of the first conductive layer and covers the sidewalls of the extrusion. The inclusion of the extrusion in the second conductive layer decreases the resistance of the gate structure and promotes the efficiency of the device.

Abstract: A method comprises determining a poly-gate temperature for a given device and determining channel temperatures of monitor devices. The method further includes extrapolating channel temperatures of the monitor devices to obtain a channel temperature for the given device. The difference in temperature (?T value) is determined for the given device based on the poly-gate temperature and the channel temperature.

Abstract: A semiconductor element structure includes a first MOS having a first high-K material and a first metal for use in a first gate, a second MOS having a second high-K material and a second metal for use in a second gate and a bridge channel disposed in a recess connecting the first gate and the second gate for electrically connecting the first gate and the second gate, wherein the bridge channel is embedded in at least one of the first gate and the second gate.

Abstract: Methods for reducing contact resistance in semiconductor devices are provided in the present invention. In one embodiment, the method includes providing a substrate having semiconductor device formed thereon, wherein the device has source and drain regions and a gate structure formed therein, performing a silicidation process on the substrate by a thermal annealing process, and performing a laser anneal process on the substrate. In another embodiment, the method includes providing a substrate having implanted dopants, performing a silicidation process on the substrate by a thermal annealing process, and activating the dopants by a laser anneal process.

Abstract: The invention relates to a thin film transistor substrate for use in a liquid crystal display device and a method of fabricating the same, and an object is to provide a thin film transistor substrate which can ensure high reliability even though a low resistance metal is used in a material for a gate electrode and a predetermined wiring and a method of fabricating the same. A TFT substrate has a gate electrode in a multilayer structure configured of an AlN film as a nitrogen containing layer, an Al film as a main wiring layer and an upper wiring layer formed of an MoN film and an Mo film. On the gate electrode whose side surface inclines gently, a gate insulating film of excellent film quality is formed.

Abstract: A semiconductor device has an n-channel MISFET having first diffusion layers formed in a first region of a surface portion of a semiconductor substrate so as to sandwich a first channel region therebetween, a first gate insulating film formed on the first channel region, and a first gate electrode including a first metal layer formed on the first gate insulating film, and a first n-type polysilicon film formed on the first metal layer, and a p-channel MISFET having second diffusion layers containing boron as a dopant and formed in a second region of the surface portion of the semiconductor substrate so as to sandwich a second channel region therebetween, a second gate insulating film formed on the second channel region, and a second gate electrode including a second metal layer containing nitrogen or carbon and formed on the second gate insulating film and a second n-type polysilicon film formed on the second metal layer and having a boron concentration of not more than 5×1019 cm?3 in a portion adjacent an in

Abstract: A PMOS (p-channel metal oxide semiconductor) device having at low voltage threshold MOSFET (MOS field effect transistor) with an improved work function and favorable DIBL (drain-induced barrier lowering) and SCE (short channel effect) characteristics, and a method for making such a device. The PMOS device includes a gate structure that is disposed on a substrate and includes a silicided gate electrode. The silicide is preferably nickel-rich and includes a peak platinum concentration at or near the interface between the gate electrode and a dielectric layer that separates the gate electrode from the substrate. The platinum peak region is produced by a multi-step rapid thermal annealing or similar process. The PMOS device may also include two such MOSFETs, one of which is boron-doped and one of which is not.

Abstract: A semiconductor device includes: a substrate and a p-channel MIS transistor. The p-channel MIS transistor includes: an n-type semiconductor region formed in the substrate; p-type first source and drain regions formed at a distance from each other in the n-type semiconductor region; a first gate insulating film formed on the n-type semiconductor region between the first source region and the first drain region; and a first gate electrode formed on the first gate insulating film. The first gate electrode includes a first nickel silicide layer having a Ni/Si composition ratio of 1 or greater, and a silicide layer formed on the first nickel silicide layer. The silicide layer contains a metal having a larger absolute value of oxide formation energy than that of Si, and a composition ratio of the metal to Si is smaller than the Ni/Si composition ratio.

Abstract: A method and an apparatus are provided in which non-directional and directional metal (e.g. Ni) deposition steps are performed in the same process chamber. A first plasma is formed for removing material from a target; a secondary plasma for increasing ion density in the material is formed in the interior of an annular electrode (e.g. a Ni ring) connected to an RF generator. Material is deposited non-directionally on the substrate in the absence of the secondary plasma and electrical biasing of the substrate, and deposited directionally when the secondary plasma is present and the substrate is electrically biased. Nickel silicide formed from the deposited metal has a lower gate polysilicon sheet resistance and may have a lower density of pipe defects than NiSi formed from metal deposited in a solely directional process, and has a lower source/drain contact resistance than NiSi formed from metal deposited in a solely non-directional process.

Abstract: In producing complementary sets of metal-oxide-semiconductor (CMOS) field effect transistors, including nFET and pFET), carrier mobility is enhanced or otherwise regulated through the reacting the material of the gate electrode with a metal to produce a stressed alloy (preferably CoSi2, NiSi, or PdSi) within a transistor gate. In the case of both the nFET and pFET, the inherent stress of the respective alloy results in an opposite stress on the channel of respective transistor. By maintaining opposite stresses in the nFET and pFET alloys or silicides, both types of transistors on a single chip or substrate can achieve an enhanced carrier mobility, thereby improving the performance of CMOS devices and integrated circuits.

Abstract: A semiconductor device includes a substrate, a p-channel MIS transistor formed on an n-type well on the substrate, having a first gate dielectric and a first gate electrode formed thereon and formed of a Ta—C alloy wherein a crystal orientation ratio of a TaC (111) face in a film thickness direction [TaC (111) face/{TaC (111) face+TaC (200) face}] is 80% or more, and an n-channel MIS transistor formed on a p-type well on the substrate, having a second gate dielectric and a second gate electrode formed thereon and formed of a Ta—C alloy wherein a crystal orientation ratio of a TaC (111) face in a film thickness direction [TaC (111) face/{TaC (111) face+TaC (200) face}] is 60% or less.

Abstract: An advanced gate structure that includes a fully silicided metal gate and silicided source and drain regions in which the fully silicided metal gate has a thickness that is greater than the thickness of the silicided source/drain regions is provided. Methods of forming the advanced gate structure are also provided.

Abstract: A thin film transistor and a method of fabricating the same capable of reducing stress of a substrate caused by a metal layer of the drain and source electrodes, the thin film transistor including a substrate; a semiconductor layer disposed on the substrate and including source, drain and channel regions; a gate insulating layer disposed on the substrate including the semiconductor layer; a gate electrode disposed on the gate insulating layer to correspond to the channel region of the semiconductor layer; an interlayer insulating layer disposed on the substrate including the gate electrode, and having contact holes connected with the source and drain regions of the semiconductor layer; and source and drain electrodes connected with the source and drain regions through the contact holes, wherein the source and drain electrodes include a first metal layer, a second metal layer, and a metal oxide layer interposed between the first metal layer and the second metal layer.

Abstract: A semiconductor structure having a plurality of gate stacks on a semiconductor substrate provided with a gate dielectric. The gate stacks have a lower first layer made of polysilicon, an overlying second layer made of a metal silicide, and an upper third layer made of an insulating material, and a sidewall oxide on the sidewalls of the first and second layers. The sidewall oxide is thinned or removed on one of the sidewalls, and the gate stacks have sidewall spacers made of the insulating material.

Abstract: In order that a top surface of a gate electrode does not have sharp portions, ends of the top surface of the gate electrode are rounded before refractory metal is deposited for silicidation. This reduces intensive application of film stresses which are generated in heat treatment, enabling formation of a silicide layer with a uniform, sufficient thickness.

Abstract: A semiconductor device includes a substrate, a p-channel MIS transistor formed on an n-type well on the substrate, having a first gate dielectric and a first gate electrode formed thereon and formed of a Ta—C alloy wherein a crystal orientation ratio of a TaC (111) face in a film thickness direction [TaC (111) face/{TaC (111) face+TaC (200) face}] is 80% or more, and an n-channel MIS transistor formed on a p-type well on the substrate, having a second gate dielectric and a second gate electrode formed thereon and formed of a Ta—C alloy wherein a crystal orientation ratio of a TaC (111) face in a film thickness direction [TaC (111) face/{TaC (111) face+TaC (200) face}] is 60% or less.

Abstract: A thin film transistor (TFT) that can prevent damage to a silicon layer under a gate electrode in an annealing process by using a first gate electrode having high thermal resistance and a second gate electrode having high reflectance and a method of manufacturing the TFT are provided. The method of manufacturing a TFT includes forming a double-layered gate electrode which includes a first gate electrode formed of a material having high thermal resistance and a second gate electrode formed of a metal having high optical reflectance on the first gate electrode, and forming a source and a drain by annealing doped regions on both sides of a silicon layer under the gate electrode by radiating a laser beam onto the entire upper surface of the silicon layer.

Abstract: Interconnections are formed over an interlayer insulating film which covers MISFETQ1 formed on the principal surface of a semiconductor substrate, while dummy interconnections are disposed in a region spaced from such interconnections. Dummy interconnections are disposed also in a scribing area. Dummy interconnections are not formed at the peripheries of a bonding pad and a marker. In addition, a gate electrode of a MISFET and a dummy gate interconnection formed of the same layer are disposed. Furthermore, dummy regions are disposed in a shallow trench element-isolation region. After such dummy members are disposed, an insulating film is planarized by the CMP method.

Abstract: A method for forming a metal/metal oxide structure that includes forming metal oxide regions, e.g. ruthenium oxide regions, at grain boundaries of a metal layer, e.g., platinum. Preferably, the metal oxide regions are formed by diffusion of oxygen through grain boundaries of the metal layer, e.g., platinum, to oxidize a metal layer thereon, e.g, ruthenium layer. The structure is particularly advantageous for use in capacitor structures and memory devices, such as dynamic random access memory (DRAM) devices.

Abstract: A semiconductor device includes a semiconductor substrate having a resistor region, an isolation layer disposed in the resistor region, the isolation layer defining active regions, first conductive layer patterns disposed on the active regions, a second conductive layer pattern covering the first conductive layer patterns and disposed on the isolation layer, the second conductive layer pattern and the first conductive layer patterns constituting a load resistor pattern, an upper insulating layer disposed over the load resistor pattern, and resistor contact plugs disposed over the active regions, the resistor contact plugs penetrating the upper insulating layer to contact the load resistor pattern.

Abstract: A gate electrode of a transistor can include an interface between a polysilicon conformal layer and a tungsten layer thereon in a trench in a substrate and a capping layer extending across the trench and covering the interface. Related methods are also disclosed.

Abstract: Semiconductor devices and methods of fabricating the same are provided. A gate insulating film is provided on a semiconductor substrate. A polymetal gate electrode is provided on the gate insulating film. The polymetal gate electrode includes a conductive polysilicon film on the gate insulating film, a first metal silicide film on the conductive polysilicon film, a barrier film on the first metal silicide film, and a metal film on the barrier film. The barrier film includes a titanium nitride (TiN) film on the first metal silicide film and a buffer layer between the TiN film and the metal film.

Abstract: A method of manufacturing a semiconductor device comprises forming a gate insulation film on a semiconductor substrate; forming a first gate electrode and a second gate electrode on the gate insulation film, the area of the second gate electrode on the surface of the semiconductor substrate being larger than that of the first gate electrode; selectively etching or grinding an upper part of the second gate electrode so that the thickness of the second gate electrode becomes smaller than the thickness of the first gate electrode; depositing a metal film on the first gate electrode and the second gate electrode; and siliciding the whole of the first gate electrode and the whole of the second gate electrode.

Abstract: A field effect transistor and a method of fabricating the field effect transistor. The field effect transistor includes: a silicon body, a perimeter of the silicon body abutting a dielectric isolation; a source and a drain formed in the body and on opposite sides of a channel formed in the body; and a gate dielectric layer between the body and an electrically conductive gate electrode, a bottom surface of the gate dielectric layer in direct physical contact with a top surface of the body and a bottom surface the gate electrode in direct physical contact with a top surface of the gate dielectric layer, the gate electrode having a first region having a first thickness and a second region having a second thickness, the first region extending along the top surface of the gate dielectric layer over the channel region, the second thickness greater than the first thickness.

Abstract: A element isolation insulating film is formed around the device regions in the silicon substrate. The device regions are formed an n-type diffusion layer region, a p-type diffusion layer region, a p-type extension region, an n-type extension region, a p-type source/drain region, an n-type source/drain region, and a nickel silicide film. Each gate dielectric film is made up of a silicon oxide film and a hafnium silicon oxynitride film. The n-type gate electrode is made up of an n-type silicon film and a nickel silicide film, and the p-type gate electrode is made up of a nickel silicide film. The hafnium silicon oxynitride films are not formed on the sidewalls of the gate electrodes.