Abstract: The adhesion between a metallic silicide film and a dielectric layer of a semiconductor device is improved. Formed on a silicon substrate is a gate dielectric layer formed on which is a metallic silicide film. A silicon dielectric layer of a rich-in-silicon-content type, which have a silicon content higher than a silicon content according to the stoichiometric composition formula, is deposited on the metallic silicide film. Because of this arrangement, a semiconductor device which is free from film peeling and which has an electrode wire with a low electrical resistance is achievable without decreasing the concentration of impurity at an electrode. If a passivation silicon oxide layer whose composition is close to a composition according to the stoichiometric composition formula is formed on the silicon oxide layer of a rich-in-silicon-content type, the degradation of the inside of an electrode, and the degradation of a gate oxide layer both caused by unwanted impurities from the outside can be prevented.

Abstract: A gate electrode comprises a N.sup.+ type polysilicon film and N.sup.- type polysilicon films directly contacted with side of the N.sup.+ type polysilicon film. Under the N.sup.+ type polysilicon films, N.sup.- type source.drain regions are provided in a P type silicon substrate to be coplanar with the main surface thereof.

Abstract: In a semiconductor device having a gate electrode and an insulating film covering the gate electrode on a compound semiconductor substrate, the vector sum of the stress in the gate metal and the stress produced by the insulating film on the gate electrode is zero. A production method of a semiconductor device includes producing a gate electrode having the same but opposite stress of an insulating film by sputtering under an adjusted gas pressure a target of WSi.sub.x and depositing an insulating film covering the gate electrode.

Abstract: A static type random access memory cell comprises two n-channel type driver transistors formed in a major surface portion of a p-type silicon substrate, two n-channel type transfer transistors formed in the major surface portion of the p-type silicon substrate, and two p-channel type load transistors stacked over the n-channel type driver transistors, and heavily doped n-type polysilicon gate electrodes of the n-channel type driver transistors are electrically connected with p-type polysilicon gate electrodes of the p-channel type load transistors, respectively, wherein metal films are inserted between the n-type polysilicon gate electrodes and the p-type polysilicon gate electrodes so that any undesirable diode never take place therebetween.

Abstract: A CMOS SRAM memory cell, and a method of making the same, is disclosed. The disclosed cell is configured as cross-coupled CMOS inverters, with the n-channel pull-down transistors in bulk, and with the p-channel load devices being accumulation mode p-channel transistors in a thin polysilicon film. The cross-coupling connection is made by way of an intermediate layer, which may include polysilicon at its top surface for performance enhancement, each of which makes contact to the drain region of an n-channel transistor, and to the opposite gate electrode, via a buried contact. The intermediate layer also serves as the gate for the thin-film p-channel transistor, which has its channel region overlying the intermediate layer. The p-channel transistors may be formed so as to overlie part of the n-channel transistor in its inverter, thus reducing active chip area required for implementation of the memory cell.

Abstract: A method is provided for forming a gate overlap LDD structure of an integrated circuit, and an integrated circuit formed according to the same. An oxide layer is formed over a substrate. A four layered gate electrode is formed in an inverse T shape. A first polysilicon layer is formed over the underlying oxide layer. A first conductive layer is formed over the first polysilicon layer. A second polysilicon layer is formed over the first conductive layer. A second conductive layer is then formed over the second polysilicon layer. The second conductive and polysilicon layers are etched to expose a portion of the underlying first conductive layer. Lightly doped drain regions are formed in the substrate adjacent to the second conductive and polysilicon layers. Sidewall oxide spacers are formed on the sides of the second conductive and polysilicon layers and on top of the first conductive layer. The first conductive and polysilicon layers are etched exposing a portion of the underlying oxide layer.

Abstract: The present invention relates to a semiconductor device used as a gate electrode or interconnection, in which a polysilicon layer in a laminate comprising a polysilicon layer doped with an impurity and a refractory metal silicide layer has an impurity concentration that is reduced close to a boundary between the polysilicon layer and the refractory metal silicide layer. With this structure, the difference in oxidation speed between the polysilicon layer and the silicide layer is smaller in comparison with a conventional structure, and thus peeling due to bird's beaks can be prevented. The semiconductor device of this structure can be realized by a two-layer polysilicon structure in which the upper layer in contact with the refractory metal silicide layer has a lower impurity concentration, or by a structure in which the peak of the impurity concentration profile is set to be deep within the polysilicon layer during ion implantation.

Abstract: This is a method of fabricating a transistor on a wafer.

Abstract: A semiconductor device, wherein an electrode wiring, which is in contact with semiconductor layers of mutually different conductive types and serves to connect at least the layers of mutually different conductive types, comprises a first portion principally composed of the same component as the principal component of the semiconductor layers, and a second portion consisting of a metal.