Abstract: A method is provided for fabricating a semiconductor device on a structure, the method including forming a dielectric layer adjacent a gate conductor of the semiconductor device and above an LDD region of the structure and forming a first dielectric spacer adjacent a first portion of the dielectric layer adjacent the gate conductor and above a second portion of the dielectric layer above the LDD region. The method also includes introducing a dopant into a source/drain region of the structure and removing a third portion of the dielectric layer above the gate conductor, the second portion of the dielectric layer above the LDD region, and the first dielectric spacer. In addition, the method includes forming a first conductive layer above the gate conductor, adjacent the first portion of the dielectric layer and above the LDD region, and saliciding the first conductive layer above the gate conductor and above the LDD region to form a salicided first conductive layer.

Abstract: A semiconductor device, in which diffusion of impurities and boron penetration are prevented, comprising a substrate, a first polycrystalline silicon layer formed on the substrate and comprising large grain polycrystalline silicon with a maximum grain size of more than 200 nm; a second polycrystalline silicon layer formed on the first polycrystalline silicon layer and comprising large grain polycrystalline silicon with a maximum grain size of at least 200 nm; and a metal layer or a metal silicide layer formed on the second polycrystalline silicon layer.

Abstract: Aluminum containing films having an oxygen content within the films. The aluminum-containing film is formed by introducing hydrogen gas along with argon gas into a sputter deposition vacuum chamber during the sputter deposition of aluminum or aluminum alloys onto a semiconductor substrate. The aluminum-containing film so formed is hillock-free and has low resistivity, relatively low roughness compared to pure aluminum, good mechanical strength, and low residual stress.

Abstract: A semiconductor device includes a pair of second semiconductor regions (5) selectively formed in predetermined spaced apart relation in a first semiconductor region (3), and a silicide film (8) formed in an upper main surface of the first semiconductor region (3) between the pair of second semiconductor regions (5). The silicide film (8) is formed to establish an electric connection between side surfaces of the second semiconductor regions (5) at their respective edges opposed to each other. A source electrode (11) is formed on an upper surface of the silicide film (8). The semiconductor device has an increased safe operating area without the increase in manufacturing costs. A method of manufacturing the semiconductor device is also provided.

Abstract: A reverse self-aligned field effect transistor and a method of fabricating the same are provided. The reverse self-aligned transistor includes a source formed on an active region of a semiconductor substrate and a drain formed on the active region of the semiconductor substrate, the drain being positioned a predetermined distance from the source. A silicide film is formed on the source and the drain. Insulative film spacers are formed on sidewalls of a trench, the trench being formed by etchin the semiconductor substrate between the source and the drain. A gate insulative film is formed on a lower portion of the trench and a metal gate is formed on the gate insulative film between the insulative film spacers. The metal gate is electrically isolated from the source and the drain by the insulative film spacers.

Abstract: A semiconductor device having a trench type gate and a fabrication method therefor is provided. The semiconductor device includes a trench formed in a semiconductor substrate and a gate insulating layer formed on the inner walls of the trench. A gate fills the trench and is insulated from the semiconductor substrate by the gate insulating layer. A barrier layer is formed between the gate insulating layer and the gate for preventing migration of impurities from the gate to the gate insulating layer.

Abstract: Aluminum-containing films having an oxygen content within the films. The aluminum-containing film is formed by introducing hydrogen gas along with argon gas into a sputter deposition vacuum chamber during the sputter deposition of aluminum or aluminum alloys onto a semiconductor substrate. The aluminum-containing film so formed is hillock-free and has low resistivity, relatively low roughness compared to pure aluminum, good mechanical strength, and low residual stress.

Abstract: A transistor device includes a gate dielectric overlying a substrate, a barrier layer overlying the gate dielectric, and a gate electrode overlying the barrier layer. The barrier layer of the device has a physical property that inhibits interaction between the gate dielectric and the gate electrode.

Abstract: An electrostatic discharge protective circuit under an input pad. The electrostatic discharge protective circuit has at least a MOS, wherein the MOS comprises a drain region, a gate structure and a source region. A metal silicon layer is on the gate structure and the source region, wherein the gate structure and the source region are coupled to each other through the metal silicon layer. A dielectric layer is over the drain region, the gate structure and the source region. A metal layer is over the dielectric layer. A via plug is in the dielectric layer, wherein the drain and the conductive layer are coupled to each other through the via plug. An input pad is over the MOS, wherein the metal layer is coupled to an input port and an internal circuit through the input pad.

Abstract: The invention provides an ESD protection circuit, which is formed on a semiconductor substrate. There is at least one MOS transistor branches out at a place between an I/O port and an internal circuit. The MOS transistor includes a drain region, a source region, a gate oxide layer, and a gate electrode. The source and the drain regions are formed in the substrate and located on each side of the gate electrode. An insulating layer is formed over the substrate to cover the MOS transistor. A drain contact is formed in the insulating layer with a contact to the drain region of the MOS transistor so that the drain region can be coupled to the internal circuit through the drain contact. A source contact is formed in the insulating layer with a contact to the source region of the MOS transistor so that the source region can be coupled to the I/O port through the source contact. Several floating silicide blocks is located between the insulating layer and the substrate at the drain region.

Abstract: A static random access memory (SRAM) is disclosed. The SRAM includes a shared contact. A gate oxide layer is firstly formed on a semiconductor substrate, and a polysilicon layer is then formed on the gate oxide layer. A dielectric spacer abuts surface of the polysilicon layer of the SRAM except on a top surface of the expect on a top surface of the polysilicon layer of the SRAM. Moreover, first ions of a first conductive type are implanted between the substrate. And second ions of the first conductive type are implanted into substrate to form a source/drain region of a first gate, and a second gate without the source/drain region using the dielectric spacers as a mask. The SRAM has at least three silicidation regions abutting top surface of the source/drain region, and the first and second gate, and the side wall second gate with no space is also covered a silicidation region. Finally, an inter-layer dielectric (ILD) is deposited over the substrate.

Abstract: A method of fabricating a mid-gap workfunction tungsten gate or W electrode directly onto a gate dielectric material for use in high speed/high density advanced MOS and CMOS devices is provided which utilizes low temperature/low pressure CVD of a tungsten carbonyl. MOS and CMOS devices containing one or more of the CVD W gates or W electrodes manufactured by the present invention are also provided herein.

Abstract: The formation of lightly doped regions under a gate of a transistor that has a reduced gate oxide is disclosed. In one embodiment, a method includes four steps. In the first step, a gate is formed over a semiconductor substrate. In the second step, the gate oxide is etched to reduce the length of the gate oxide. In the third step, a first ion implantation is applied, at an angle other than perpendicular to the substrate. Finally, in the fourth step, a second ion implantation is applied, perpendicular to the substrate.

Abstract: A semiconductor device is provided which is improved to be capable of stably forming a contact hole. A stopper film is provided on a gate electrode. An interlayer insulating film is provided on a semiconductor substrate to cover the gate electrode. The interlayer insulating film and the stopper film are penetrated by a first contact hole which exposes a surface of the gate electrode. The interlayer insulating film is provided with a second contact hole for exposing a surface of an impurity diffusion layer. The stopper film is formed of a material higher in etch selectivity than the interlayer insulating film.

Abstract: A technique for fabricating an integrated circuit device 100 using an inverse-T tungsten gate structure 121 overlying a silicided layer 119 is provided. This technique uses steps of forming a high quality gate oxide layer 115 overlying a semiconductor substrate 111. The silicided layer 119 is defined overlying the gate oxide layer 115. The silicided layer 119 does not substantially react to this layer. The technique defines the inverse-T tungsten gate electrode layer 121 overlying the silicided layer 119. A top surface of this gate electrode may also be silicided 127 to further reduce the resistance of this device element.

Abstract: Semiconductor device and method for fabricating the same, is disclosed, in which a gate insulating film is formed thicker at portions opposite to edge portions of a gate electrode for preventing the hot carrier possible to occur due to a strong electric field of the gate electrode, that can improve a device reliability, the device including a semiconductor substrate, a gate insulating film formed on the semiconductor substrate, the gate insulating film having both end portions formed thicker than a center portion, a gate electrode formed on the gate insulating film, the gate electrode having a center portion formed thicker than portions thereof on both sides of the gate insulating film, and impurity regions formed in surfaces of the semiconductor substrate on both sides of the gate electrode, and the method including the steps of (1) forming a gate insulating film on a semiconductor substrate, and forming a gate electrode having a thicker center portion on the gate insulating film, (2) expanding thicknesses o

Abstract: A method of fabricating a transistor having an improved salicided gate is provided. The method may include forming a gate (14) that is separated from a substrate (12) by a gate insulator (16). A spacer (22) may be formed proximate the gate (14) such that the spacer (22) exposes a top region (28) and a side region (30) of the gate (14). The top region (28) and the side region (30) of the gate (14) may be irradiated at an angle (38) to form a post amorphous region (32) within the gate (14). A reactive layer (42) may be formed adjacent the post amorphous region (32). A salicidation region (44) may be then formed between the post amorphous region (32) and the reactive layer (42). The reactive layer (42) may be removed to expose the salicidation region (44).

Abstract: A unit cell of a static random-access memory includes a laminated gate electrode structure adjacent to a diffusion layer. A top surface of the gate electrode structure is coated with a first silicide layer and the diffusion layer includes a second silicide layer. The second silicide layer is separated from the gate electrode structure by a distance that is the same as a width of a sidewall spacer on an opposite side of the gate electrode structure. The portion of the diffusion layer that is exposed between the second silicide layer and the gate electrode structure has a higher impurity concentration than the remainder of the diffusion layer to reduce or eliminate undesired leakage voltage.

Abstract: Silicidation of a polysilicon line having frcc upper sidewalls is performed so that no stress is applied to the sidewalls of the polysilicon line, resulting in the formation of a reduced stress silicide structure. This is accomplished by forming a polysilicon line having spacers on either side which extend above the upper surface of the polysilicon line but which are spaced from the edge of the polysilicon line. A layer of a metal such as titanium or tungsten is provided in contact with the top surface polysilicon line. The structure is annealed to cause the metal to react with the polysilicon to form a layer of silicide. Since the upper side portions of the polysilicon line are spaced away from the spacers during the silicidation anneal, the growing silicide region has room to expand without being subjected to lateral stresses in the silicidation process.

Abstract: A non-volatile semiconductor cell structure and method comprises a trenched floating gate, a sidewall doping and a corner doping and further includes a sidewall doped region, a corner doped region, a channel region, and an inter-gate dielectric layer, and a control gate. The trenched floating gate is formed in a trench etched into the semiconductor substrate. In a preferred embodiment, the trenched floating gate has a top surface which is substantially planar with a top surface of the semiconductor substrate. The control gate and the inter-gate dielectric are formed on the top surface of the trenched floating gate. The sidewall doped region and the corner doped region are laterally separated by the trench in which the trenched floating gate is formed. The sidewall doped region has a depth which is greater than the depth of the trench, and the corner doped region has a depth which is less than the depth of the trench.

Abstract: A self-aligned thin-film transistor, fabricated by depositing a conductive layer on a transparent insulating substrate, etching the conductive layer so as to form a gate electrode together with gate lines, forming a triple layer having of a gate insulating layer, a semiconductor layer and an extrinsic semiconductor layer sequentially deposited over the substrate, etching the triple layer so that only a part thereof covering the gate electrode only remains to form an active pattern, depositing a transparent conductive layer over the substrate to form a drain electrode part by etching the transparent conductive layer so that a part of the transparent conductive layer remains overlapping the gate electrode, depositing a negative photoresist over the substrate, exposing the negative photoresist to a light supplied from the back of the transparent substrate opposite the gate and developing the thus-exposed photoresist, forming a drain electrode by removing the part of a transparent conductive layer appearing in a

Abstract: A semiconductor device comprises a semiconductor substrate of a first conductivity type with a first insulating layer formed on the semiconductor substrate and a thin film field effect transistor with a control gate containing a refractory metal silicide formed on the semiconductor substrate over the first insulating layer. A second insulating layer covers the control gate electrode. A semiconductor film is formed on the semiconductor substrate over the first and second insulating layers and having a first region of a second conductivity type opposite to the first conductivity type. A second region of the first conductivity type is formed in contact with a first end of the first region. A third region of the first conductivity type is formed in contact with a second end of the first region. The control gate electrode and a part of the first region are overlapped with each other over the second insulating layer.

Abstract: An aluminum-containing film having an oxygen content within the film. The aluminum-containing film is formed by introducing hydrogen gas and oxygen gas along with argon gas into a sputter deposition vacuum chamber during the sputter deposition of aluminum or aluminum alloys onto a semiconductor substrate. The alumininum-containing film so formed is hillock-free and has low resistivity, relatively low roughness compared to pure aluminum, good mechanical strength, and low residual stress.

Abstract: A semiconductor structure that includes a silicon substrate which has a top surface, a diffusion region formed in the substrate adjacent to the top surface, a polysilicon gate formed on the top surface of the substrate adjacent to but not contacting the diffusion region, an insulator layer substantially covers the polysilicon gate and the diffusion region, the layer contains a via opening therein, and an electrically conducting plug filling at least partially the via opening providing electrical communication between the polysilicon gate and the diffusion region.

Abstract: Ba--Sr--Ti-oxide dielectric material, with at least 60 atomic percent of the total content of the oxide being Ti, can have relatively high dielectric constant K (>40 at 20.degree. C.) and relatively low second order voltage coefficient a.sub.2 of the dielectric constant (a.sub.2 <100 PPM V.sup.2 at 20.degree. C.). In preferred embodiments the dielectric material has nominal composition (BA.sub.x Sr.sub.y Ti.sub.1--x--y)-oxide, with 1--x--y in the range 0.65-0.90, with both x and y greater than or equal to 0.05. Ba, Sr and Ti together typically comprise at least 99 atomic percent of the total metal content of the dielectric material.

Abstract: In this structure, the lightly doped layers that form the upper portions of the source and drain regions extend inwards towards the gate region, thereby satisfying the design requirements of low area and high resistivity at the interface, but not outwards towards the poly/silicide conductors that make connection to the source and drain areas.

Abstract: An MOS semiconductor device containing an MOSFET with an asymmetric LDD structure, which has in a semiconductor substrate a first heavily doped region, a lightly doped region formed adjacent to the first heavily doped region, and a second heavily doped region formed apart from the first lightly doped region. The first heavily doped region and the lightly doped region act as a drain region of the MOSFET, and the second heavily doped region acts as a source region thereof. A gate electrode composed of a plurality of parts is positioned over a channel region. At least one of the parts has a drain-side end positioned over the lightly doped region and a source-side end positioned over the channel region not to extend to the second heavily doped region. Free design can be realized without layout restriction and fabricated with high reproducibility in large quantities.

Abstract: A method of forming a polycide thin film. First, a silicon layer is formed. Next, a thin barrier layer is formed on the first silicon layer. A second silicon layer is then formed on the barrier layer. Next, a metal layer is formed on the second silicon layer. The metal layer and the second silicon layer are then reacted together to form a silicide.

Abstract: In a thin-film transistor 171, in order to sufficiently suppress an optical leakage current Ioff, thereby achieving a high ON/OFF current ratio, at least one of shortest distances between an arbitrary intersection of an outline of a gate electrode 131 and an outline of a drain electrode 141 and an intersection of the outline of the gate electrode 131 and an outline of a source electrode 151 is formed to be larger than the shortest distance between a portion of the outline of the gate electrode 131 overlapping the drain electrode 141 and another portion thereof overlapping the source electrode 151.

Abstract: A gate electrode is made up of a polycrystalline silicon film containing phosphorous as a dopant for determining its conductivity type, a titanium silicide film of the C54 structure, and a tungsten silicide film all of which films are laid one on another in said order.

Abstract: The present invention provides a semiconductor memory device including (a) a substrate, (b) a first MOS transistor acting as a driver, the first MOS transistor being formed on the substrate, (c) a second MOS transistor acting as a load, the second MOS transistor being formed on an insulative layer formed on the substrate, and (d) a gate electrode formed on a gate insulating film above a channel region of the second MOS transistor, the gate electrode comprising a semiconductor layer and a layer composed of metallic compound thereof. The present invention avoids significant reduction of breakdown voltage of a gate electrode in SRAM including a p-channel TFT as a load, even if a gate insulating film of a p-channel TFT is made thin.

Abstract: A semiconductor device includes a gate insulating film on a semiconductor region of a first conductive type. There is provided on the gate insulating film a gate electrode having a channel length under a design rule of 350 nm or below. The gate electrode includes a first conductive film and a first silicide film formed on the first conductive film and a contact length between the first conductive film and the first silicide film in a channel length direction is longer than the channel length. Source and drain regions each including an impurity layer of a second conductive type formed on the surface of the semiconductor region and a second silicide film formed on the impurity layer. An insulating film spacer structure is provided to contact with side surfaces of the first conductive film of the gate electrode and to have a top surface thereof higher than a top surface of the gate electrode.

Abstract: A semiconductor device including a CMOSFET having first and second channel type MOSFETs, respectively formed in a first semiconductor region of a first conductivity type and in a second semiconductor region of a second conductivity type. The first channel type MOSFET has a first gate electrode insulatively formed on the first region, made of a first conductivity type semiconductor, and having a gate length of 0.2 .mu.m or less, first source/drain regions of the second conductivity type respectively formed in the first region and having a LDD structure, and a buried channel region of the second conductivity type formed just below the first gate electrode. The second channel type MOSFET has a second gate electrode insulatively formed on the second region, made of a first conductivity type semiconductor, and having a gate length of 0.2 .mu.m or less, second source/drain regions of the first conductivity type respectively formed in the second region and having a LDD structure.

Abstract: A polysilicon electrode is formed in an active area surrounded by an isolation on a silicon substrate with a gate oxide film sandwiched therebetween, a polysilicon wire is formed on the isolation, and a source/drain region is formed on both sides of the polysilicon electrode. On the both sides of a polysilicon film constituting the electrode and the wire are formed side walls having a height that is 4/5 or less of the height of the polysilicon film. Furthermore, the polysilicon film is provided with a silicide layer in contact with the top surface and portions of the side surfaces of the polysilicon film projecting from the side walls, and another silicide layer is formed in contact with the source/drain region. Since the sectional area of the silicide layer is increased, the resistance value can be suppressed even when the dimension of the polysilicon film is minimized. Thus, the invention provides a semiconductor device including an FET having a low resistance value applicable to a refined pattern.

Abstract: A method is described for fabricating field effect transistors (FETs) having double silicide gate electrodes and interconnecting lines for CMOS circuits. The method reduces the IR voltage drops and RC time delay constants, and thereby improves circuit performance. The method consists of forming FETs having gate electrodes and interconnecting lines from a multilayer made up of a doped first polysilicon layer, a first silicide layer (WSi.sub.2), and a doped second polysilicon layer. After patterning the multilayer to form the gate electrodes, a titanium (Ti) metal is deposited and annealed to form a second silicide layer on the gate electrodes, and simultaneously forms self-aligned Ti silicide contacts on the source/drain areas. The latitude in overetching the contact openings in an insulating (PMD) layer to the gate electrodes extending over the field oxide area is increased, and the contact resistance (R.sub.c) is reduced because of the presence of the WSi.sub.

Abstract: A multiple implant lightly doped drain ("MILDD") field effect transistor is disclosed. The transistor includes a channel, a gate, a dielectric structure that separates the gate from the channel, a source region and a drain region. The drain region has a first drain subregion, a second drain subregion and a third drain subregion. Each drain subregion has a dopant concentration that differs from that of the other two drain subregions. A method of forming the same is also disclosed.

Abstract: A method for forming a tungsten silicide polycide gate electrode within a Metal Oxide Semiconductor Field Effect Transistor (MOSFET), and the tungsten silicide polycide gate electrode which is formed through the method. Formed upon a semiconductor substrate is a gate oxide layer. Formed upon the gate oxide layer is a first polysilicon layer which is formed through annealing a first amorphous silicon layer. Formed upon the first polysilicon layer is a second polysilicon layer which is formed through annealing a second amorphous silicon layer. Formed upon the second polysilicon layer is a tungsten silicide layer formed through a Chemical Vapor Deposition (CVD) method. The first polysilicon layer and the second polysilicon layer have a crystallite size no greater than about 0.3 microns, and the first polysilicon layer and the second polysilicon layer have a dopant concentration larger than about 1E16 atoms per cubic centimeter.

Abstract: An improved method of forming insulated gate field effect transistors is described. In accordance with the method, gate electrodes are formed from metal such as aluminum together with wirings electrically connecting the gate electrodes. The gate electrodes are anodic oxidized by dipping them as an anode in an electrolyte to form an oxide of the metal covering them. Since the connecting wirings are covered with a suitable organic film before the anodizing, no aluminum oxide is formed thereon so that it is easy to remove the connecting wiring by usual etching.

Abstract: A semiconductor device having an enhancement-type MOS structure which can prevent large leakage current is disclosed. A high-concentration region for threshold-value regulation use formed in a channel region below a gate electrode in an enhancement-type transistor is caused to be contiguous with a source region and not contiguous with a drain region. Herein, the distance between the high-concentration region and the drain region is set so as to preclude the depletion layer extending from the drain region side from reaching the high-concentration region. Therefore, the electrical field in the depletion layer does not become the critical field which causes avalanche or Zener breakdown, and so leakage current can be caused to be reduced.

Abstract: A process is disclosed for forming an integrated circuit device, such as an EPROM device, with a floating gate electrode with a discontinuous phase of metal silicide formed on a surface thereof is described. The process for forming such a discontinuous phase of metal silicide on the surface of a polysilicon floating gate electrode for the device comprises the steps of depositing a first polysilicon layer over a substrate, and preferably over a thin oxide layer on the substrate capable of functioning as a gate oxide; then forming a very thin layer of a silicide-forming metal over the polysilicon layer; and heating the structure sufficiently to cause all of the silicide-forming metal to react with the underlying polysilicon layer to form metal silicide and to coalesce the metal silicide into a discontinuous phase on the surface of the polysilicon layer.

Abstract: After formation a gate electrode and source/drain regions, N ions or O ions are implanted into a predetermined region using a resist mask, and a Ti layer is deposited on the entire face of a substrate, and then the Ti layer is silicided in self-alignment by a heat treatment, whereby a high resistivity TixNySiz mixing layer is formed the predetermined region on the gate electrode and the source/drain regions 10, and a low resistivity TiSi.sub.2 layer 12 is formed on another region.

Abstract: The present invention is directed to a unique silicon based MOS transistor having an inverse-T refractory metal gate structure. The gate fabricated according to this invention comprises a main CVD tungsten portion and a lower sputtered tungsten portion outwardly extending from the bottom of the CVD portion such that a cross section of the gate appears as an inverted "T". A Cl.sub.2 /O.sub.2 plasma etch is used to etch the CVD tungsten layer and a chemical etch is used to etch the sputtered tungsten layer to form the gate electrode. It has been discovered that sputtered tungsten is more resistant to Cl.sub.2 /O.sub.2 reactive ion etch than is CVD tungsten. The sputtered tungsten layer acts as a shield to protect the underlying gate oxide layer from ion damage throughout the fabrication process.

Abstract: A p-type silicon substrate is provided at its main surface with n-type impurity regions with a space between each other. A gate electrode is formed on a region between the n-type impurity regions with a gate insulating film therebetween. A titanium silicide layer is formed in a region extending from a surface layer of the gate electrode to a surface layer of the n-type impurity region. The titanium silicide layer forms a local interconnection. A side wall insulating film remains on a side wall of the gate electrode on which the titanium silicide layer is not formed. Thereby, the semiconductor device can have a local interconnection which has high reliability and can be formed easily.

Abstract: An interconnection structure of a semiconductor device with a gate electrode, an active region provided in the vicinity of the gate electrode and a first buried layer in a contact hole exposing the gate electrode and the active region. The contact hole is easily formed, and the first buried layer has a substantially low interconnection resistance value.

Abstract: A method for fabricating semiconductor devices wherein polysilicon gates for complementary-type field-effect semiconductor devices are formed of polysilicon to which impurity doped simultaneously to the polysilicon deposition; the both gates having the dual N.sup.+ /P.sup.+ polysilicon gate structure, so that the both N- and P-channel transistors are formed as the surface-channel type ones; and therefore, the off-characteristic, the short channel effect, and the controllability of threshold voltage are progressed. More specifically, N- and P-channel MISFETs are provided on a common semiconductor substrate (1); N-type polysilicon (9) doped with N-type impurity is adopted as the gate electrode for the N-channel MISFET; P-type polysilicon (8) doped with P-type impurity is adopted as the gate electrode for the P-channel MISFET; and a narrow region preventing the mutual diffusion of impurities is provided between portions of respective polysilicon.

Abstract: In a thin-film transistor 171, in order to sufficiently suppress an optical leakage current Ioff, thereby achieving a high ON/OFF current ratio, at least one of shortest distances between an arbitrary intersection of an outline of a gate electrode 131 and an outline of a drain electrode 141 and an intersection of the outline of the gate electrode 131 and an outline of a source electrode 151 is formed to be larger than the shortest distance between a portion of the outline of the gate electrode 131 overlapping the drain electrode 141 and another portion thereof overlapping the source electrode 151.

Abstract: A semiconductor apparatus with MOS transistors for transmitting electrons from an n type source layer to an n type drain layer through a first channel region in an n-channel MOS transistor and transmitting holes from a p type source layer to a p type drain layer through a second channel region in a p-channel MOS transistor consists of a field oxide layer for separating the n-channel MOS transistor from the p-channel MOS transistor, an n type gate electrode mounted on a first gate oxide film arranged on the first channel region, a p type gate electrode mounted on a second gate oxide film arranged on the second channel region and positioned far away from the n type gate electrode to prevent impurities implanted into one of tile gate electrodes from diffusing into the other gate electrode, and a gate metal wiring connecting the gate electrodes through a gate contact hole to miniaturize the transistors.

Abstract: In a semiconductor device having a gate electrode and an insulating film covering the gate electrode on a compound semiconductor substrate, the stress in the gate metal and the stress produced by the insulating film on the gate electrode cancel so that threshold voltage is not a function of gate orientation relative to the crystalline directions of the substrate.

Abstract: A layout and fabrication technique for EPROMs and similar devices includes a preferred technique for partially self-aligning bit line contacts. In addition, a self-aligned, buried Vss line is provided which is in contact with the substrate for its entire length. This provides a highly conductive Vss line, allowing the size of such line to be diminished. The use of a buried Vss contact line and a partially self-aligned bit line contact contributes to a device layout having minimum cell sizes for a given feature size.

Abstract: A semiconductor device and a method of fabricating the semiconductor device are disclosed in which the method comprises the steps of forming an insulating film for element-isolation and a gate insulating film on a surface of a semiconductor substrate, forming a semiconductor film on the element-isolation insulating film and the gate insulating film, removing a part of the semiconductor film corresponding to a boundary between a first region for formation of an N-channel transistor and a second region for formation of a P-channel transistor, introducing N type impurities into a part of the semiconductor film located on the first region and introducing P type impurities into a part of the semiconductor film located on the second region, forming a metallic film over the semiconductor film having the impurities introduced therein and the element-isolation insulating film, and patterning the metallic film and the semiconductor film into a pattern of a gate electrode common to the N-channel transistor and the P-cha