Three Or More Electrode Device Patents (Class 257/39)
  • Patent number: 10361292
    Abstract: Antiferromagnetic magneto-electric spin-orbit read (AFSOR) logic devices are presented. The devices include a voltage-controlled magnetoelectric (ME) layer that switches polarization in response to an electric field from the applied voltage and a narrow channel conductor of a spin-orbit coupling (SOC) material on the ME layer. One or more sources and one or more drains, each optionally formed of ferromagnetic material, are provided on the SOC material.
    Type: Grant
    Filed: February 17, 2018
    Date of Patent: July 23, 2019
    Assignees: INTEL CORPORATION, THE RESEARCH FOUNDATION FOR THE STATE UNIVERSITY OF NEW YORK, BOARD OF REGENTS OF THE UNIVERSITY OF NEBRASKA, THE REGENTS OF THE UNIVERSITY OF CALIFORNIA
    Inventors: Dmitri E. Nikonov, Christian Binek, Xia Hong, Jonathan P. Bird, Kang L. Wang, Peter A. Dowben
  • Patent number: 10283611
    Abstract: An electronic device may include a topological insulating layer including first and second surfaces facing each other and a transition metal oxide layer provided on the first surface of the topological insulating layer. The topological insulating layer may have a thickness ranging from 1 nm to 10 nm.
    Type: Grant
    Filed: July 25, 2017
    Date of Patent: May 7, 2019
    Assignee: Industry-Academic Cooperation Foundation, Yonsei University
    Inventors: MannHo Cho, KwangSik Jeong, DaeHong Ko, DongHyeok Lim, TaeHyeon Kim
  • Patent number: 10249744
    Abstract: A tunnel field-effect transistor and a method for manufacturing a tunnel field-effect transistor is disclosed. Source regions are located on two sides of an oxide structure, an epitaxial layer is located on a surface on a side that is of the source region and that is away from the oxide structure, and a gate structure is located on a surface on a side that is of the epitaxial layer and that is away from the source region, so that a gate electric field direction of the tunnel field-effect transistor is the same as an electron tunneling direction, and carriers on a valence band of the source region tunnel to a conduction band of the epitaxial layer at relatively high tunneling efficiency, thereby generating a steep subthreshold swing and enabling a subthreshold swing value of the tunnel field-effect transistor to be lower than 60 mV/dec to consume relatively low power.
    Type: Grant
    Filed: May 11, 2018
    Date of Patent: April 2, 2019
    Assignee: HUAWEI TECHNOLOGIES CO., LTD.
    Inventors: Jing Zhao, Chen-Xiong Zhang
  • Patent number: 10243054
    Abstract: Embodiments of the invention are directed to fabrication operations for co-integrating standard-gate (SG) and extended-gate (EG) nanosheet/nanowire transistors on the same substrate. The SG and EG nanosheet/nanowire transistors share certain fabrication operations for certain features. For example, the processes to form the bottommost channel nanosheet, the bottommost sacrificial nanosheet, and the topmost channel nanosheet are the same for SG nanosheet transistors and the EG nanosheet transistors. Because the thickness of the sacrificial nanosheet needs to be thicker for EG nanosheet transistors, a thickness of the bottommost sacrificial nanosheet is selected to accommodate the design parameters of the EG nanosheet transistor. Because the thickness of the SG and the EG channel nanosheets do not need to be different, a thickness of the bottommost channel nanosheet and the topmost channel nanosheet can be selected to accommodate the design parameters of both the SG and the EG nanosheet transistors.
    Type: Grant
    Filed: April 3, 2018
    Date of Patent: March 26, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Kangguo Cheng, Juntao Li, Geng Wang, Qintao Zhang
  • Patent number: 10229971
    Abstract: A method is presented for integrating a first nanosheet transistor and a second nanosheet transistor on a chip. The method includes constructing the first nanosheet transistor by forming a first nanosheet stack including alternating layers of a first material and a second material over a substrate, forming a dummy gate and first spacers over the first nanosheet stack, selectively etching the alternating layers of the first material to define gaps between the alternating layers of the second material, filling the gaps with second spacers, removing the dummy gate, removing a portion of the first nanosheet stack including layers of the first and second materials, and selectively removing remaining layers of the second material such that a single layer of the first material remains intact to define a single nanosheet channel. The method includes constructing the second nanosheet transistor by forming a second nanosheet stack having multiple layers of nanosheet channels.
    Type: Grant
    Filed: November 16, 2017
    Date of Patent: March 12, 2019
    Assignee: International Business Machines Corporation
    Inventors: Kangguo Cheng, Xin Miao, Wenyu Xu, Chen Zhang
  • Patent number: 10204903
    Abstract: Devices and methods for forming a device are disclosed. A substrate is provided. A plurality of fin structures are formed in the substrate. The fin structures include an upper part and a lower part. An isolation layer is formed on the substrate. The lower part of the plurality of fin structures is embedded in the isolation layer. A source including a first source portion and a second source portion is formed in a first side of the substrate. The first source portion partially occupies the fin structures along a length direction. The second source portion is formed over the first source portion. The second source portion elevates the fin structures. A drain is formed in a second side of the substrate. A distance between the source to the drain defines a channel region. A gate having a gate dielectric and a metal gate electrode is formed over the substrate. The gate wraps around the elevated fin structures and channel region.
    Type: Grant
    Filed: December 1, 2016
    Date of Patent: February 12, 2019
    Assignee: GLOBALFOUNDRIES SINGAPORE PTE. LTD.
    Inventors: Ping Zheng, Eng Huat Toh
  • Patent number: 10170548
    Abstract: A semiconductor device and process of making the same generally includes simultaneously forming nanosheet capacitors with nanosheet FET devices on the same substrate. The nanosheets in the capacitor have a width and are coupled to one another by sacrificial layers, wherein the sacrificial layers have a width smaller than the nanosheet width, and wherein the nanosheets and the sacrificial layers are conductively coupled to the substrate. The nanosheets in the FET devices are spaced apart and free of sacrificial layers. The nanosheets in the FET device have a width less than half the width of the nanosheets in the capacitor region.
    Type: Grant
    Filed: March 21, 2018
    Date of Patent: January 1, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Kangguo Cheng, James J. Demarest, John G. Gaudiello, Juntao Li
  • Patent number: 10157935
    Abstract: Embodiments are directed to a method of forming a semiconductor device and resulting structures having a nanosheet capacitor by forming a first nanosheet stack over a substrate. The first nanosheet stack includes a first nanosheet vertically stacked over a second nanosheet. A second nanosheet stack is formed over the substrate adjacent to the first nanosheet stack. The second nanosheet stack includes a first nanosheet vertically stacked over a second nanosheet. Exposed portions of the first and second nanosheets of the second nanosheet stack are doped and gates are formed over channel regions of the first and second nanosheet stacks.
    Type: Grant
    Filed: February 22, 2017
    Date of Patent: December 18, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Kangguo Cheng, Juntao Li, Geng Wang, Qintao Zhang
  • Patent number: 10141528
    Abstract: Embodiments of the invention are directed to methods and resulting structures for enhancing drive current and increasing device yield in n-type carbon nanotube field effect transistors (CNT FETs) with scaled contacts using a wetting layer. In some embodiments of the invention, a nanotube is formed over a surface of a substrate. An insulating layer is formed over the nanotube such that end portions of the nanotube are exposed. A low work function metal is formed over the end portions of the nanotube and a wetting layer is formed between the low work function metal and the nanotube.
    Type: Grant
    Filed: May 23, 2017
    Date of Patent: November 27, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Damon B. Farmer, Shu-Jen Han, Jianshi Tang, John J. Yurkas
  • Patent number: 10014390
    Abstract: Structures for a nanosheet field-effect transistor and methods for forming a structure for a nanosheet field-effect transistor. A body feature is formed that includes a first nanosheet channel layer, a second nanosheet channel layer, and first, second, and third sacrificial layers that are vertically arranged between the first and second nanosheet channel layers. The first, second, and third sacrificial layers are laterally recessed relative to the first and second nanosheet channel layers to form a cavity indented into a sidewall of the first body feature. The second sacrificial layer is laterally recessed to a lesser extent than the first sacrificial layer or the third sacrificial layer such that an end of the second sacrificial layer projects into the cavity between the first and third sacrificial layers. A dielectric spacer is formed in the first and second portions of cavity between the first and second nanosheet channel layers.
    Type: Grant
    Filed: October 10, 2017
    Date of Patent: July 3, 2018
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Guillaume Bouche, Julien Frougier, Ruilong Xie
  • Patent number: 9985097
    Abstract: A semiconductor device and process of making the same generally includes simultaneously forming nanosheet capacitors with nanosheet FET devices on the same substrate. The nanosheets in the capacitor have a width and are coupled to one another by sacrificial layers, wherein the sacrificial layers have a width smaller than the nanosheet width, and wherein the nanosheets and the sacrificial layers are conductively coupled to the substrate. The nanosheets in the FET devices are spaced apart and free of sacrificial layers. The nanosheets in the FET device have a width less than half the width of the nanosheets in the capacitor region.
    Type: Grant
    Filed: June 30, 2016
    Date of Patent: May 29, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Kangguo Cheng, James J. Demarest, John G. Gaudiello, Juntao Li
  • Patent number: 9978787
    Abstract: An image sensor includes a substrate including a photoelectric conversion element; a transfer gate formed over the photoelectric conversion element; and a channel layer controlled by the transfer gate, wherein the channel layer includes a first region which is in contacts with the photoelectric conversion element and a second region which is separated from the photoelectric conversion element, and the first region and the second region have different crystalline states from each other.
    Type: Grant
    Filed: August 8, 2017
    Date of Patent: May 22, 2018
    Assignee: SK Hynix Inc.
    Inventor: Sung-Kun Park
  • Patent number: 9935189
    Abstract: The present invention provides a transistor and a fabrication method thereof. By a silicon nanowire as a core region being serially wrapped by a germanium channel, a gate insulating film and a gate, the present invention enables to form a potential well for storing holes as a carrier of HHMT in the germanium channel by a valance band energy offset between the silicon core region and the germanium channel, to gain maximum gate controllability to the germanium channel, and to simplify a fabricating process by simultaneously forming the germanium channel and the gate insulating film in one process.
    Type: Grant
    Filed: November 8, 2016
    Date of Patent: April 3, 2018
    Assignee: GACHON UNIVERSITY OF INDUSTRY—ACADEMIC COOPERATION FOUNDATION
    Inventors: Seongjae Cho, Mina Yun
  • Patent number: 9865380
    Abstract: The present invention relates to a material comprising reduced graphene oxide, wherein the degree of reduction of the graphene oxide exhibits a spatial variation so that the material exhibits a gradient in the electric conductivity and/or permittivity. The material can for example be used in an electric device for purposes of field grading and/or dissipation of charges. Examples of electric devices wherein the material is beneficial includes cable accessories, bushings, power cables, microelectronics, switchgear, etc. The invention further relates to a method of producing a material for electrical applications. The method comprises treating different parts of a graphene oxide element differently, so as to achieve a different degree of reduction of the graphene oxide within the element, resulting in a sample having a gradient in the electrical conductivity and/or permittivity.
    Type: Grant
    Filed: June 24, 2013
    Date of Patent: January 9, 2018
    Assignee: ABB SCHWEIZ AG
    Inventors: Emmanuel Logakis, Alex Skordos, Panagiota Chatzi
  • Patent number: 9735233
    Abstract: Provided are electronic devices and methods of manufacturing same. An electronic device includes an energy barrier forming layer on a substrate, an upper channel material layer on the substrate, and a gate electrode that covers the upper channel material layer and the energy barrier forming layer. The gate electrode includes a side gate electrode portion that faces a side surface of the energy barrier forming layer. The side gate electrode may be configured to cause an electric field to be applied directly on the energy barrier forming layer via the side surface of the energy barrier forming layer, thereby enabling adjustment of the energy barrier between the energy barrier forming layer and the upper channel material layer. The electronic device may further include a lower channel material layer that is provided on the substrate and does not contact the upper channel material layer.
    Type: Grant
    Filed: November 4, 2015
    Date of Patent: August 15, 2017
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jinseong Heo, Kiyoung Lee, Jaeho Lee, Seongjun Park
  • Patent number: 9698373
    Abstract: A barrier film layer, a photoelectric device comprising the barrier film layer and a manufacturing method of the photoelectric device are provided. A material forming the barrier film layer includes a topological insulator, and the barrier film layer is formed on a surface of an base plate which is patterned. In this way, a better package of the photoelectric device can be achieved.
    Type: Grant
    Filed: December 12, 2014
    Date of Patent: July 4, 2017
    Assignee: BOE Technology Group Co., Ltd.
    Inventors: Yongchun Lu, Yong Qiao, Hongfei Cheng, Jianbo Xian
  • Patent number: 9548394
    Abstract: A two-dimensional thin film transistor and a method for manufacturing a two-dimensional thin film transistor includes layering a semiconducting channel material on a substrate, providing a first electrode material on top of the semiconducting channel material, patterning a source metal electrode and a drain metal electrode at opposite ends of the semiconducting channel material from the first electrode material, opening a window between the source metal electrode and the drain metal electrode, removing the first electrode material from the window located above the semiconducting channel material providing a gate dielectric above the semiconducting channel material, and providing a top gate above the gate dielectric, the top gate formed from a second electrode material. The semiconducting channel material is made of tungsten diselenide, the first electrode material and the second electrode material are made of graphene, and the gate dielectric is made of hexagonal boron nitride.
    Type: Grant
    Filed: April 21, 2015
    Date of Patent: January 17, 2017
    Assignee: UChicago Argonne, LLC
    Inventors: Saptarshi Das, Anirudha V. Sumant, Andreas Roelofs
  • Patent number: 9484428
    Abstract: A semiconductor device includes a first gate electrode defined on a base layer. A first plurality of layers is disposed on a first sidewall of the first gate electrode. The first plurality of layers includes a first dielectric layer formed on the first sidewall, a first ballistic conductor layer formed above the first dielectric layer, an intermediate layer formed above the first ballistic conductor layer, a second ballistic conductor layer formed above the intermediate layer, and a second dielectric layer formed above the second ballistic conductor layer. A second gate electrode contacts the second dielectric layer.
    Type: Grant
    Filed: January 29, 2015
    Date of Patent: November 1, 2016
    Assignee: GLOBALFOUNDRIES Inc.
    Inventor: Ajey Poovannummoottil Jacob
  • Patent number: 9385195
    Abstract: A vertical tunneling FET (TFET) provides low-power, high-speed switching performance for transistors having critical dimensions below 7 nm. The vertical TFET uses a gate-all-around (GAA) device architecture having a cylindrical structure that extends above the surface of a doped well formed in a silicon substrate. The cylindrical structure includes a lower drain region, a channel, and an upper source region, which are grown epitaxially from the doped well. The channel is made of intrinsic silicon, while the source and drain regions are doped in-situ. An annular gate surrounds the channel, capacitively controlling current flow through the channel from all sides. The source is electrically accessible via a front side contact, while the drain is accessed via a backside contact that provides low contact resistance and also serves as a heat sink. Reliability of vertical TFET integrated circuits is enhanced by coupling the vertical TFETs to electrostatic discharge (ESD) diodes.
    Type: Grant
    Filed: March 31, 2015
    Date of Patent: July 5, 2016
    Assignee: STMicroelectronics, Inc.
    Inventor: John H. Zhang
  • Patent number: 9318556
    Abstract: Provided are graphene transistors having a tunable barrier. The graphene transistor includes a semiconductor substrate, an insulating thin film disposed on the semiconductor substrate, a graphene layer on the insulating thin film, a first electrode connected to an end of the graphene layer, a second electrode that is separate from an other end of the graphene layer and contacts the semiconductor substrate, a gate insulating layer covering the graphene layer, and a gate electrode on the gate insulating layer, wherein an energy barrier is formed between the semiconductor substrate and the graphene layer.
    Type: Grant
    Filed: July 10, 2014
    Date of Patent: April 19, 2016
    Assignees: Samsung Electronics Co., Ltd., Research & Business Foundation Sungkyunkwan University
    Inventors: Jin-hong Park, Jae-woo Shim, Hyung-youl Park, Jae-ho Lee
  • Patent number: 9312760
    Abstract: A power converter is described that includes components arranged within a first die and a second die of a single package. The first die includes one or more first switches coupled to a switching node of a power stage. The second die includes one or more second switches coupled to the switching node of the power stage, a feedback control unit configured to detect a current level at the one or more second switches of the power stage, and a controller unit configured to control the one or more first switches and the one or more second switches of the power stage based at least in part on the current level detected by the feedback control unit.
    Type: Grant
    Filed: December 16, 2013
    Date of Patent: April 12, 2016
    Assignee: Infineon Technologies Austria AG
    Inventors: Christoph Sandner, Roman Riederer, Josef Höglauer, Stephan Auer
  • Patent number: 9214596
    Abstract: According to the present invention, a method for manufacturing a compound semiconductor comprises: forming a graphene-derived material layer on either a first selected substrate or a first selected compound semiconductor layer; forming a second compound semiconductor layer of at least one layer on at least said graphene-derived material layer, and changing the graphene-derived material layer so as to separate said second compound semiconductor layer of at least one layer.
    Type: Grant
    Filed: October 26, 2011
    Date of Patent: December 15, 2015
    Assignees: LG Siltron Inc., Kumoh National Institute of Technology Industry-Academic Cooperation Foundation
    Inventors: Sung-Jin An, Dong-Gun Lee, Seok-Han Kim
  • Patent number: 9126829
    Abstract: The present invention is to provide a graphene valley singlet-triplet qubit device. The device includes a substrate, and a graphene layer formed on the substrate. An energy gap is created between the valence band and the conduction band of the graphene layer. At least one electrical gate is configured on the graphene layer and/or on two sides of the graphene layer. The graphene layer is located in a magnetic field and a voltage is applied to at least one electrical gate, thereby creating a valley singlet-triplet qubit.
    Type: Grant
    Filed: January 13, 2012
    Date of Patent: September 8, 2015
    Assignee: National Tsing Hua University
    Inventor: Yu-Shu Wu
  • Patent number: 9105556
    Abstract: According to example embodiments, a tunneling field-effect transistor (TFET) includes a first electrode on a substrate, a semiconductor layer on a portion of the first electrode, a graphene channel on the semiconductor layer, a second electrode on the graphene channel, a gate insulating layer on the graphene channel, and a gate electrode on the gate insulating layer. The first electrode may include a portion that is adjacent to the first area of the substrate. The semiconductor layer may be between the graphene channel and the portion of the first electrode. The graphene channel may extend beyond an edge of at least one of the semiconductor layer and the portion of the first electrode to over the first area of the substrate.
    Type: Grant
    Filed: May 31, 2013
    Date of Patent: August 11, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jin-seong Heo, Seong-jun Park, Kyung-eun Byun, David Seo, Hyun-jae Song, Jae-ho Lee, Hyun-jong Chung
  • Publication number: 20150137079
    Abstract: Among other things, one or more techniques for forming a vertical tunnel field effect transistor (FET), and a resulting vertical tunnel FET are provided herein. In an embodiment, the vertical tunnel FET is formed by forming a core over a first type substrate region, forming a second type channel shell around a circumference greater than a core circumference, forming a gate dielectric around a circumference greater than the core circumference, forming a gate electrode around a circumference greater than the core circumference, and forming a second type region over a portion of the second type channel shell, where the second type has a doping opposite a doping of the first type. In this manner, line tunneling is enabled, thus providing enhanced tunneling efficiency for a vertical tunnel FET.
    Type: Application
    Filed: December 22, 2014
    Publication date: May 21, 2015
    Inventors: Krishna Kumar Bhuwalka, Gerben Doornbos, Matthias Passlack
  • Patent number: 9018617
    Abstract: A topological insulator structure includes an insulating substrate and a magnetically doped TI quantum well film located on the insulating substrate. A material of the magnetically doped TI quantum well film is represented by a chemical formula of Cry(BixSb1-x)2-yTe3. 0<x<1, 0<y<2. Values of x and y satisfies that an amount of a hole type charge carriers introduced by a doping with Cr is substantially equal to an amount of an electron type charge carriers introduced by a doping with Bi. The magnetically doped TI quantum well film is in 3 QL to 5 QL.
    Type: Grant
    Filed: October 16, 2013
    Date of Patent: April 28, 2015
    Assignees: Tsinghua University, Institute of Physics, Chinese Academy of Sciences
    Inventors: Qi-Kun Xue, Ke He, Xu-Cun Ma, Xi Chen, Li-Li Wang, Cui-Zu Chang, Xiao Feng, Yao-Yi Li, Jin-Feng Jia
  • Publication number: 20150102289
    Abstract: A gate tunable diode is provided. The gate tunable diode includes a gate dielectric formed on a gate electrode and a graphene electrode formed on the gate dielectric. Also, the gate tunable diode includes a tunnel dielectric formed on the graphene electrode and a tunnel electrode formed on the tunnel dielectric.
    Type: Application
    Filed: December 18, 2014
    Publication date: April 16, 2015
    Inventors: Ali Afzali-Ardakani, Damon Farmer
  • Patent number: 8994006
    Abstract: Semiconductor nanoparticles are deposited on a top surface of a first insulator layer of a substrate. A second insulator layer is deposited over the semiconductor nanoparticles and the first insulator layer. A semiconductor layer is then bonded to the second insulator layer to provide a semiconductor-on-insulator substrate, which includes a buried insulator layer including the first and second insulator layers and embedded semiconductor nanoparticles therein. Back gate electrodes are formed underneath the buried insulator layer, and shallow trench isolation structures are formed to isolate the back gate electrodes. Field effect transistors are formed in a memory device region and a logic device region employing same processing steps. The embedded nanoparticles can be employed as a charge storage element of non-volatile memory devices, in which charge carriers tunnel through the second insulator layer into or out of the semiconductor nanoparticles during writing and erasing.
    Type: Grant
    Filed: October 2, 2012
    Date of Patent: March 31, 2015
    Assignee: International Business Machines Corporation
    Inventors: Kangguo Cheng, Robert H. Dennard, Hemanth Jagannathan, Ali Khakifirooz, Tak H. Ning, Ghavam G. Shahidi
  • Patent number: 8975095
    Abstract: A technique is provided for base recognition in an integrated device is provided. A target molecule is driven into a nanopore of the integrated device. The integrated device includes a nanowire separated into a left nanowire part and a right nanowire part to form a nanogap in between, a source pad connected to the right nanowire part, a drain pad connected to the left nanowire part, and the nanopore. The source pad, the drain pad, the right nanowire part, the left nanowire part, and the nanogap together form a transistor. The nanogap is part of the nanopore. A transistor current is measured while a single base of the target molecule is in the nanogap of the nanopore, and the single base affects the transistor current. An identity of the single base is determined according to a change in the transistor current.
    Type: Grant
    Filed: May 29, 2013
    Date of Patent: March 10, 2015
    Assignee: International Business Machines Corporation
    Inventors: Shu-Jen Han, Ajay K. Royyuru, Gustavo A. Stolovitzky, Deqiang Wang
  • Patent number: 8975123
    Abstract: Device structures, fabrication methods, and design structures for tunnel field-effect transistors. A drain comprised of a first semiconductor material having a first band gap and a source comprised of a second semiconductor material having a second band gap are formed. A tunnel barrier is formed between the source and the drain. The second semiconductor material exhibits a broken-gap energy band alignment with the first semiconductor material. The tunnel barrier is comprised of a third semiconductor material with a third band gap larger than the first band gap and larger than the second band gap. The third band gap is configured to bend under an external bias to assist in aligning a first energy band of the first semiconductor material with a second energy band of the second semiconductor material.
    Type: Grant
    Filed: July 9, 2013
    Date of Patent: March 10, 2015
    Assignee: International Business Machines Corporation
    Inventors: Douglas M. Daley, Hung H. Tran, Wayne H. Woods, Ze Zhang
  • Publication number: 20150060772
    Abstract: According to one embodiment, the pair of semiconductor regions are provided respectively on a pair of side walls of the second semiconductor layer having the fin configuration to form tunnel junctions with the second semiconductor layer. The gate electrode is provided on two sides of the second semiconductor layer at the pair of side walls to oppose the tunnel junctions with the semiconductor regions interposed between the gate electrode and the tunnel junctions. The third semiconductor layer is separated from the second semiconductor layer and the semiconductor regions by the first semiconductor layer to be adjacent to the first semiconductor layer.
    Type: Application
    Filed: November 12, 2013
    Publication date: March 5, 2015
    Applicant: Kabushiki Kaisha Toshiba
    Inventor: Toshitaka MIYATA
  • Publication number: 20150048313
    Abstract: The present invention discloses a strip-shaped gate-modulated tunneling field effect transistor with double-diffusion and a preparation method thereof, belonging to a field of CMOS field effect transistor logic device and the circuit.
    Type: Application
    Filed: July 8, 2013
    Publication date: February 19, 2015
    Inventors: Ru Huang, Qianqian Huang, Yingxin Qiu, Zhan Zhan, Yangyuan Wang
  • Publication number: 20150034909
    Abstract: A nonvolatile memory (“NVM”) bitcell includes a capacitor, an asymmetrically doped transistor, and a tunneling device. The capacitor, transistor, and tunneling device are each electrically coupled to different active regions and metal contacts. The three devices are coupled by a floating gate that traverses the three active regions. The tunneling device is formed in a native region to allow for greater dynamic range in the voltage used to induce tunneling. The FN tunneling device is used to erase the device, allowing for faster page erasure, and thus allows for rapid testing and verification of functionality. The asymmetric transistor, in conjunction with the capacitor, is used to both program and read the logical state of the floating gate. The capacitor and floating gate are capacitively coupled together, removing the need for a separate selection device to perform read and write operations.
    Type: Application
    Filed: July 30, 2013
    Publication date: February 5, 2015
    Applicant: Synopsys, Inc.
    Inventor: Andrew E. Horch
  • Patent number: 8946679
    Abstract: The present disclosure relates to the fabrication of microelectronic devices having at least one negative differential resistance device formed therein. In at least one embodiment, the negative differential resistance devices may be formed utilizing quantum wells. Embodiments of negative differential resistance devices of present description may achieve high peak drive current to enable high performance and a high peak-to-valley current ratio to enable low power dissipation and noise margins, which allows for their use in logic and/or memory integrated circuitry.
    Type: Grant
    Filed: August 21, 2013
    Date of Patent: February 3, 2015
    Assignee: Intel Corporation
    Inventor: Ravi Pillarisetty
  • Patent number: 8946680
    Abstract: A tunnel field effect transistor (TFET) includes a source region, the source region comprising a first portion of a nanowire; a channel region, the channel region comprising a second portion of the nanowire; a drain region, the drain region comprising a portion of a silicon pad, the silicon pad being located adjacent to the channel region; and a gate configured such that the gate surrounds the channel region and at least a portion of the source region.
    Type: Grant
    Filed: August 10, 2012
    Date of Patent: February 3, 2015
    Assignee: International Business Machines Corporation
    Inventors: Sarunya Bangsaruntip, Isaac Lauer, Amlan Majumdar, Jeffrey Sleight
  • Publication number: 20150014633
    Abstract: Device structures, fabrication methods, and design structures for tunnel field-effect transistors. A drain comprised of a first semiconductor material having a first band gap and a source comprised of a second semiconductor material having a second band gap are formed. A tunnel barrier is formed between the source and the drain. The second semiconductor material exhibits a broken-gap energy band alignment with the first semiconductor material. The tunnel barrier is comprised of a third semiconductor material with a third band gap larger than the first band gap and larger than the second band gap.
    Type: Application
    Filed: July 9, 2013
    Publication date: January 15, 2015
    Inventors: Douglas M. Daley, Hung H. Tran, Wayne H. Woods, Ze Zhang
  • Patent number: 8933435
    Abstract: Devices and methods for forming a device are presented. The device includes a substrate and a fin type transistor disposed on the substrate. The transistor includes a fin structure which serves as a body of the transistor. The fin structure includes first and second end regions and an intermediate region in between the first and second end regions. A source region is disposed on the first end region, a drain region disposed in the second end region and a gate disposed on the intermediate region of the fin structure. The device includes a channel region disposed adjacent to the source region and a gate dielectric of the gate. A source tunneling junction is aligned to the gate with a controlled channel thickness TCH.
    Type: Grant
    Filed: December 26, 2012
    Date of Patent: January 13, 2015
    Assignees: GLOBALFOUNDRIES Singapore Pte. Ltd., National University of Singapore
    Inventors: Kian Hui Goh, Eng Huat Toh, Yee Chia Yeo
  • Patent number: 8927968
    Abstract: A method of forming a semiconductor device is provided. The method includes providing a structure including, a handle substrate, a buried boron nitride layer located above an uppermost surface of the handle substrate, a buried oxide layer located on an uppermost surface of the buried boron nitride layer, and a top semiconductor layer located on an uppermost surface of the buried oxide layer. Next, a first semiconductor pad, a second semiconductor pad and a plurality of semiconductor nanowires connecting the first semiconductor pad and the second semiconductor pad in a ladder-like configuration are patterned into the top semiconductor layer. The semiconductor nanowires are suspended by removing a portion of the buried oxide layer from beneath each semiconductor nanowire, wherein a portion of the uppermost surface of the buried boron nitride layer is exposed. Next, a gate all-around field effect transistor is formed.
    Type: Grant
    Filed: August 26, 2013
    Date of Patent: January 6, 2015
    Assignee: International Business Machines Corporation
    Inventors: Guy Cohen, Michael A. Guillorn, Alfred Grill, Leathen Shi
  • Publication number: 20140353593
    Abstract: A vertical tunneling field effect transistor (TFET) and method for forming a vertical tunneling field effect transistor (TFET) is disclosed. The vertical tunneling field effect transistor TFET comprises a vertical core region, a vertical source region, a vertical drain region and a gate structure. The vertical core region is extending perpendicularly from a semiconductor substrate, having a top surface, consisting of a doped outer part and a middle part. The vertical source region of semiconducting core material comprises the doped outer part of the vertical core region. The vertical drain region of semiconducting drain material comprises along its longitudinal direction a first drain part and a second drain part, the first drain part either directly surrounding said vertical source region or directly sandwiching said vertical source region between two sub-parts of said first drain part, the second drain part located directly above and in contact with the first drain part.
    Type: Application
    Filed: May 28, 2014
    Publication date: December 4, 2014
    Inventor: Quentin Smets
  • Patent number: 8890121
    Abstract: A technique is provided for base recognition in an integrated device is provided. A target molecule is driven into a nanopore of the integrated device. The integrated device includes a nanowire separated into a left nanowire part and a right nanowire part to form a nanogap in between, a source pad connected to the right nanowire part, a drain pad connected to the left nanowire part, and the nanopore. The source pad, the drain pad, the right nanowire part, the left nanowire part, and the nanogap together form a transistor. The nanogap is part of the nanopore. A transistor current is measured while a single base of the target molecule is in the nanogap of the nanopore, and the single base affects the transistor current. An identity of the single base is determined according to a change in the transistor current.
    Type: Grant
    Filed: May 6, 2013
    Date of Patent: November 18, 2014
    Assignee: International Business Machines Corporation
    Inventors: Shu-Jen Han, Ajay K. Royyuru, Gustavo A. Stolovitzky, Deqiang Wang
  • Patent number: 8877532
    Abstract: A method of manufacturing an organic electroluminescence display device includes an organic compound layer which is placed between a pair of electrodes and includes at least an emission layer, the organic compound layer being two-dimensionally arranged, includes forming the organic compound layer which is insoluble in water in an entire emission region on a substrate, providing a mask layer containing a water-soluble material in at least a part of a region on the organic compound layer, removing a part of the organic compound layer which is provided in a region which is other than the region in which the mask layer is provided, removing the mask layer, and forming, after the removing of the mask layer, a layer containing at least an alkali metal or an alkaline-earth metal in a region including at least the emission region.
    Type: Grant
    Filed: March 15, 2012
    Date of Patent: November 4, 2014
    Assignee: Canon Kabushiki Kaisha
    Inventors: Tomoyuki Hiroki, Taro Endo, Itaru Takaya, Koichi Ishige, Nobuhiko Sato
  • Patent number: 8860006
    Abstract: A carrier-mediated magnetic phase change spin transistor is disclosed. In general, the spin transistor includes a Dilute Magnetic Semiconductor (DMS) channel and a gate stack formed on the DMS channel. The gate stack includes a multiferroic gate dielectric on the DMS channel, and a gate contact on a surface of the multiferroic gate dielectric opposite the DMS channel. The multiferroic gate dielectric is formed of a multiferroic material that exhibits a cross-coupling between magnetic and electric orders (i.e., magnetoelectric coupling), which in one embodiment is BiFeO3 (BFO). As a result, the multiferroic material layer enables an electrically modulated magnetic exchange bias that enhances paramagnetic to ferromagnetic switching of the DMS channel. The DMS channel is formed of a DMS material, which in one embodiment is Manganese Germanium (MnGe). In one embodiment, the DMS channel is a nanoscale DMS channel.
    Type: Grant
    Filed: March 25, 2011
    Date of Patent: October 14, 2014
    Assignee: The Regents of the University of California
    Inventors: Kang-Lung Wang, Ajey Poovannummoottil, Faxian Xiu
  • Publication number: 20140264289
    Abstract: The present disclosure provides one embodiment of a semiconductor structure. The semiconductor structure includes a semiconductor substrate having a first region and a second region; a first semiconductor mesa formed on the semiconductor substrate within the first region; a second semiconductor mesa formed on the semiconductor substrate within the second region; and a field effect transistor (FET) formed on the semiconductor substrate. The FET includes a first doped feature of a first conductivity type formed in a top portion of the first semiconductor mesa; a second doped feature of a second conductivity type formed in a bottom portion of the first semiconductor mesa, the second semiconductor mesa, and a portion of the semiconductor substrate between the first and second semiconductor mesas; a channel in a middle portion of the first semiconductor mesa and interposed between the source and drain; and a gate formed on sidewall of the first semiconductor mesa.
    Type: Application
    Filed: March 12, 2013
    Publication date: September 18, 2014
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Harry-Hak-Lay Chuang, Yi-Ren Chen, Chi-Wen Liu, Chao-Hsiung Wang, Ming Zhu
  • Patent number: 8829492
    Abstract: The present invention relates to a multi-quantum dot device and a method of manufacturing the multi-quantum dot device.
    Type: Grant
    Filed: November 25, 2010
    Date of Patent: September 9, 2014
    Assignee: Chungbuk National University Industry-Academic Cooperation Foundation
    Inventors: Jung Bum Choi, Jong Jin Lee
  • Publication number: 20140239258
    Abstract: A tunnel field effect transistor (TFET) includes a source region, the source region comprising a first portion of a nanowire; a channel region, the channel region comprising a second portion of the nanowire; a drain region, the drain region comprising a portion of a silicon pad, the silicon pad being located adjacent to the channel region; and a gate configured such that the gate surrounds the channel region and at least a portion of the source region.
    Type: Application
    Filed: August 10, 2012
    Publication date: August 28, 2014
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Sarunya Bangsaruntip, Isaac Lauer, Amlan Majumdar, Jeffrey Sleight
  • Patent number: 8766384
    Abstract: A method of forming a magnetic tunnel junction device is disclosed that includes forming a trench in a substrate, the trench including a plurality of sidewalls and a bottom wall. The method includes depositing a first conductive material within the trench proximate to one of the sidewalls and depositing a second conductive material within the trench. The method further includes depositing a material to form a magnetic tunnel junction (MTJ) structure within the trench. The MTJ structure includes a fixed magnetic layer having a magnetic field with a fixed magnetic orientation, a tunnel junction layer, and a free magnetic layer having a magnetic field with a configurable magnetic orientation. The method further includes selectively removing a portion of the MTJ structure to create an opening in the MTJ structure.
    Type: Grant
    Filed: October 30, 2012
    Date of Patent: July 1, 2014
    Assignee: QUALCOMM Incorporated
    Inventor: Xia Li
  • Publication number: 20140175381
    Abstract: Devices and methods for forming a device are presented. The device includes a substrate and a fin type transistor disposed on the substrate. The transistor includes a fin structure which serves as a body of the transistor. The fin structure includes first and second end regions and an intermediate region in between the first and second end regions. A source region is disposed on the first end region, a drain region disposed in the second end region and a gate disposed on the intermediate region of the fin structure. The device includes a channel region disposed adjacent to the source region and a gate dielectric of the gate. A source tunneling junction is aligned to the gate with a controlled channel thickness TCH.
    Type: Application
    Filed: December 26, 2012
    Publication date: June 26, 2014
    Applicants: GLOBALFOUNDRIES SINGAPORE PTE. LTD., NATIONAL UNIVERSITY OF SINGAPORE
    Inventors: Kian Hui GOH, Eng Huat TOH, Yee Chia YEO
  • Publication number: 20140175382
    Abstract: An electrical device includes an insulating substrate and a magnetically doped TI quantum well film. The insulating substrate includes a first surface and a second surface. The magnetically doped topological insulator quantum well film is located on the first surface of the insulating substrate. A material of the magnetically doped topological insulator quantum well film is represented by a chemical formula of Cry(BixSb1-x)2-yTe3, wherein 0<x<1, 0<y<2, and values of x and y satisfies that an amount of a hole type charge carriers introduced by a doping with Cr is substantially equal to an amount of an electron type charge carriers introduced by a doping with Bi, the magnetically doped topological insulator quantum well film is in 3 QL thickness to 5 QL thickness.
    Type: Application
    Filed: October 16, 2013
    Publication date: June 26, 2014
    Applicants: Institute of Physics, Chinese Academy of Sciences, Tsinghua University
    Inventors: QI-KUN XUE, KE HE, XU-CUN MA, XI CHEN, LI-LI WANG, YA-YU WANG, Li Lv, CUI-ZU CHANG, XIAO FENG
  • Publication number: 20140166985
    Abstract: A rectifying device includes: a one-dimensional channel (18) formed with a semiconductor, electrons traveling through the one-dimensional channel; an electrode (26) that applies an effective magnetic field generated from a spin orbit interaction to the electrons traveling through the one-dimensional channel by applying an electric field to the one-dimensional channel, the effective magnetic field being in a direction intersectional to the direction in which the electrons are traveling; and an external magnetic field generating unit (38) that generates an external magnetic field in the one-dimensional channel.
    Type: Application
    Filed: August 21, 2012
    Publication date: June 19, 2014
    Applicant: JAPAN SCIENCE AND TECHNOLOGY AGENCY
    Inventors: Makoto Kohda, Junsaku Nitta, Kensuke Kobayashi
  • Publication number: 20140166984
    Abstract: A graphene device having a ribbon structure with soft boundaries formed between two thin parallel transport barriers in a “railroad track” configuration. Such a structure permits transport along the ribbon, and also permits transport of electrons across the barriers by means of resonant tunneling through quasi-bound states within the railroad track confinement. The transport barriers can be of any form of so long as transport through the barriers leads to the formation of isolated resonant bands with a transport gap. In some embodiments, the transport barriers can be in the form of a pair of parallel line defects, wherein the line defects delineate the central ribbon section and the two lateral sections. In some such embodiments, the line defects are chemically decorated by the adsorption of diatomic gases. In other embodiments, the transport barriers can be formed by the application of large local potentials directly to the graphene sheet.
    Type: Application
    Filed: December 6, 2013
    Publication date: June 19, 2014
    Inventors: L. Daniel Gunlycke, Carter T. White