Three Or More Electrode Device Patents (Class 257/39)
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Publication number: 20150060772Abstract: According to one embodiment, the pair of semiconductor regions are provided respectively on a pair of side walls of the second semiconductor layer having the fin configuration to form tunnel junctions with the second semiconductor layer. The gate electrode is provided on two sides of the second semiconductor layer at the pair of side walls to oppose the tunnel junctions with the semiconductor regions interposed between the gate electrode and the tunnel junctions. The third semiconductor layer is separated from the second semiconductor layer and the semiconductor regions by the first semiconductor layer to be adjacent to the first semiconductor layer.Type: ApplicationFiled: November 12, 2013Publication date: March 5, 2015Applicant: Kabushiki Kaisha ToshibaInventor: Toshitaka MIYATA
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Publication number: 20150048313Abstract: The present invention discloses a strip-shaped gate-modulated tunneling field effect transistor with double-diffusion and a preparation method thereof, belonging to a field of CMOS field effect transistor logic device and the circuit.Type: ApplicationFiled: July 8, 2013Publication date: February 19, 2015Inventors: Ru Huang, Qianqian Huang, Yingxin Qiu, Zhan Zhan, Yangyuan Wang
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Publication number: 20150034909Abstract: A nonvolatile memory (“NVM”) bitcell includes a capacitor, an asymmetrically doped transistor, and a tunneling device. The capacitor, transistor, and tunneling device are each electrically coupled to different active regions and metal contacts. The three devices are coupled by a floating gate that traverses the three active regions. The tunneling device is formed in a native region to allow for greater dynamic range in the voltage used to induce tunneling. The FN tunneling device is used to erase the device, allowing for faster page erasure, and thus allows for rapid testing and verification of functionality. The asymmetric transistor, in conjunction with the capacitor, is used to both program and read the logical state of the floating gate. The capacitor and floating gate are capacitively coupled together, removing the need for a separate selection device to perform read and write operations.Type: ApplicationFiled: July 30, 2013Publication date: February 5, 2015Applicant: Synopsys, Inc.Inventor: Andrew E. Horch
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Patent number: 8946679Abstract: The present disclosure relates to the fabrication of microelectronic devices having at least one negative differential resistance device formed therein. In at least one embodiment, the negative differential resistance devices may be formed utilizing quantum wells. Embodiments of negative differential resistance devices of present description may achieve high peak drive current to enable high performance and a high peak-to-valley current ratio to enable low power dissipation and noise margins, which allows for their use in logic and/or memory integrated circuitry.Type: GrantFiled: August 21, 2013Date of Patent: February 3, 2015Assignee: Intel CorporationInventor: Ravi Pillarisetty
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Patent number: 8946680Abstract: A tunnel field effect transistor (TFET) includes a source region, the source region comprising a first portion of a nanowire; a channel region, the channel region comprising a second portion of the nanowire; a drain region, the drain region comprising a portion of a silicon pad, the silicon pad being located adjacent to the channel region; and a gate configured such that the gate surrounds the channel region and at least a portion of the source region.Type: GrantFiled: August 10, 2012Date of Patent: February 3, 2015Assignee: International Business Machines CorporationInventors: Sarunya Bangsaruntip, Isaac Lauer, Amlan Majumdar, Jeffrey Sleight
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Publication number: 20150014633Abstract: Device structures, fabrication methods, and design structures for tunnel field-effect transistors. A drain comprised of a first semiconductor material having a first band gap and a source comprised of a second semiconductor material having a second band gap are formed. A tunnel barrier is formed between the source and the drain. The second semiconductor material exhibits a broken-gap energy band alignment with the first semiconductor material. The tunnel barrier is comprised of a third semiconductor material with a third band gap larger than the first band gap and larger than the second band gap.Type: ApplicationFiled: July 9, 2013Publication date: January 15, 2015Inventors: Douglas M. Daley, Hung H. Tran, Wayne H. Woods, Ze Zhang
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Patent number: 8933435Abstract: Devices and methods for forming a device are presented. The device includes a substrate and a fin type transistor disposed on the substrate. The transistor includes a fin structure which serves as a body of the transistor. The fin structure includes first and second end regions and an intermediate region in between the first and second end regions. A source region is disposed on the first end region, a drain region disposed in the second end region and a gate disposed on the intermediate region of the fin structure. The device includes a channel region disposed adjacent to the source region and a gate dielectric of the gate. A source tunneling junction is aligned to the gate with a controlled channel thickness TCH.Type: GrantFiled: December 26, 2012Date of Patent: January 13, 2015Assignees: GLOBALFOUNDRIES Singapore Pte. Ltd., National University of SingaporeInventors: Kian Hui Goh, Eng Huat Toh, Yee Chia Yeo
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Patent number: 8927968Abstract: A method of forming a semiconductor device is provided. The method includes providing a structure including, a handle substrate, a buried boron nitride layer located above an uppermost surface of the handle substrate, a buried oxide layer located on an uppermost surface of the buried boron nitride layer, and a top semiconductor layer located on an uppermost surface of the buried oxide layer. Next, a first semiconductor pad, a second semiconductor pad and a plurality of semiconductor nanowires connecting the first semiconductor pad and the second semiconductor pad in a ladder-like configuration are patterned into the top semiconductor layer. The semiconductor nanowires are suspended by removing a portion of the buried oxide layer from beneath each semiconductor nanowire, wherein a portion of the uppermost surface of the buried boron nitride layer is exposed. Next, a gate all-around field effect transistor is formed.Type: GrantFiled: August 26, 2013Date of Patent: January 6, 2015Assignee: International Business Machines CorporationInventors: Guy Cohen, Michael A. Guillorn, Alfred Grill, Leathen Shi
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Publication number: 20140353593Abstract: A vertical tunneling field effect transistor (TFET) and method for forming a vertical tunneling field effect transistor (TFET) is disclosed. The vertical tunneling field effect transistor TFET comprises a vertical core region, a vertical source region, a vertical drain region and a gate structure. The vertical core region is extending perpendicularly from a semiconductor substrate, having a top surface, consisting of a doped outer part and a middle part. The vertical source region of semiconducting core material comprises the doped outer part of the vertical core region. The vertical drain region of semiconducting drain material comprises along its longitudinal direction a first drain part and a second drain part, the first drain part either directly surrounding said vertical source region or directly sandwiching said vertical source region between two sub-parts of said first drain part, the second drain part located directly above and in contact with the first drain part.Type: ApplicationFiled: May 28, 2014Publication date: December 4, 2014Inventor: Quentin Smets
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Patent number: 8890121Abstract: A technique is provided for base recognition in an integrated device is provided. A target molecule is driven into a nanopore of the integrated device. The integrated device includes a nanowire separated into a left nanowire part and a right nanowire part to form a nanogap in between, a source pad connected to the right nanowire part, a drain pad connected to the left nanowire part, and the nanopore. The source pad, the drain pad, the right nanowire part, the left nanowire part, and the nanogap together form a transistor. The nanogap is part of the nanopore. A transistor current is measured while a single base of the target molecule is in the nanogap of the nanopore, and the single base affects the transistor current. An identity of the single base is determined according to a change in the transistor current.Type: GrantFiled: May 6, 2013Date of Patent: November 18, 2014Assignee: International Business Machines CorporationInventors: Shu-Jen Han, Ajay K. Royyuru, Gustavo A. Stolovitzky, Deqiang Wang
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Patent number: 8877532Abstract: A method of manufacturing an organic electroluminescence display device includes an organic compound layer which is placed between a pair of electrodes and includes at least an emission layer, the organic compound layer being two-dimensionally arranged, includes forming the organic compound layer which is insoluble in water in an entire emission region on a substrate, providing a mask layer containing a water-soluble material in at least a part of a region on the organic compound layer, removing a part of the organic compound layer which is provided in a region which is other than the region in which the mask layer is provided, removing the mask layer, and forming, after the removing of the mask layer, a layer containing at least an alkali metal or an alkaline-earth metal in a region including at least the emission region.Type: GrantFiled: March 15, 2012Date of Patent: November 4, 2014Assignee: Canon Kabushiki KaishaInventors: Tomoyuki Hiroki, Taro Endo, Itaru Takaya, Koichi Ishige, Nobuhiko Sato
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Patent number: 8860006Abstract: A carrier-mediated magnetic phase change spin transistor is disclosed. In general, the spin transistor includes a Dilute Magnetic Semiconductor (DMS) channel and a gate stack formed on the DMS channel. The gate stack includes a multiferroic gate dielectric on the DMS channel, and a gate contact on a surface of the multiferroic gate dielectric opposite the DMS channel. The multiferroic gate dielectric is formed of a multiferroic material that exhibits a cross-coupling between magnetic and electric orders (i.e., magnetoelectric coupling), which in one embodiment is BiFeO3 (BFO). As a result, the multiferroic material layer enables an electrically modulated magnetic exchange bias that enhances paramagnetic to ferromagnetic switching of the DMS channel. The DMS channel is formed of a DMS material, which in one embodiment is Manganese Germanium (MnGe). In one embodiment, the DMS channel is a nanoscale DMS channel.Type: GrantFiled: March 25, 2011Date of Patent: October 14, 2014Assignee: The Regents of the University of CaliforniaInventors: Kang-Lung Wang, Ajey Poovannummoottil, Faxian Xiu
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Publication number: 20140264289Abstract: The present disclosure provides one embodiment of a semiconductor structure. The semiconductor structure includes a semiconductor substrate having a first region and a second region; a first semiconductor mesa formed on the semiconductor substrate within the first region; a second semiconductor mesa formed on the semiconductor substrate within the second region; and a field effect transistor (FET) formed on the semiconductor substrate. The FET includes a first doped feature of a first conductivity type formed in a top portion of the first semiconductor mesa; a second doped feature of a second conductivity type formed in a bottom portion of the first semiconductor mesa, the second semiconductor mesa, and a portion of the semiconductor substrate between the first and second semiconductor mesas; a channel in a middle portion of the first semiconductor mesa and interposed between the source and drain; and a gate formed on sidewall of the first semiconductor mesa.Type: ApplicationFiled: March 12, 2013Publication date: September 18, 2014Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Harry-Hak-Lay Chuang, Yi-Ren Chen, Chi-Wen Liu, Chao-Hsiung Wang, Ming Zhu
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Patent number: 8829492Abstract: The present invention relates to a multi-quantum dot device and a method of manufacturing the multi-quantum dot device.Type: GrantFiled: November 25, 2010Date of Patent: September 9, 2014Assignee: Chungbuk National University Industry-Academic Cooperation FoundationInventors: Jung Bum Choi, Jong Jin Lee
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Publication number: 20140239258Abstract: A tunnel field effect transistor (TFET) includes a source region, the source region comprising a first portion of a nanowire; a channel region, the channel region comprising a second portion of the nanowire; a drain region, the drain region comprising a portion of a silicon pad, the silicon pad being located adjacent to the channel region; and a gate configured such that the gate surrounds the channel region and at least a portion of the source region.Type: ApplicationFiled: August 10, 2012Publication date: August 28, 2014Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Sarunya Bangsaruntip, Isaac Lauer, Amlan Majumdar, Jeffrey Sleight
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Patent number: 8766384Abstract: A method of forming a magnetic tunnel junction device is disclosed that includes forming a trench in a substrate, the trench including a plurality of sidewalls and a bottom wall. The method includes depositing a first conductive material within the trench proximate to one of the sidewalls and depositing a second conductive material within the trench. The method further includes depositing a material to form a magnetic tunnel junction (MTJ) structure within the trench. The MTJ structure includes a fixed magnetic layer having a magnetic field with a fixed magnetic orientation, a tunnel junction layer, and a free magnetic layer having a magnetic field with a configurable magnetic orientation. The method further includes selectively removing a portion of the MTJ structure to create an opening in the MTJ structure.Type: GrantFiled: October 30, 2012Date of Patent: July 1, 2014Assignee: QUALCOMM IncorporatedInventor: Xia Li
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Publication number: 20140175381Abstract: Devices and methods for forming a device are presented. The device includes a substrate and a fin type transistor disposed on the substrate. The transistor includes a fin structure which serves as a body of the transistor. The fin structure includes first and second end regions and an intermediate region in between the first and second end regions. A source region is disposed on the first end region, a drain region disposed in the second end region and a gate disposed on the intermediate region of the fin structure. The device includes a channel region disposed adjacent to the source region and a gate dielectric of the gate. A source tunneling junction is aligned to the gate with a controlled channel thickness TCH.Type: ApplicationFiled: December 26, 2012Publication date: June 26, 2014Applicants: GLOBALFOUNDRIES SINGAPORE PTE. LTD., NATIONAL UNIVERSITY OF SINGAPOREInventors: Kian Hui GOH, Eng Huat TOH, Yee Chia YEO
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Publication number: 20140175382Abstract: An electrical device includes an insulating substrate and a magnetically doped TI quantum well film. The insulating substrate includes a first surface and a second surface. The magnetically doped topological insulator quantum well film is located on the first surface of the insulating substrate. A material of the magnetically doped topological insulator quantum well film is represented by a chemical formula of Cry(BixSb1-x)2-yTe3, wherein 0<x<1, 0<y<2, and values of x and y satisfies that an amount of a hole type charge carriers introduced by a doping with Cr is substantially equal to an amount of an electron type charge carriers introduced by a doping with Bi, the magnetically doped topological insulator quantum well film is in 3 QL thickness to 5 QL thickness.Type: ApplicationFiled: October 16, 2013Publication date: June 26, 2014Applicants: Institute of Physics, Chinese Academy of Sciences, Tsinghua UniversityInventors: QI-KUN XUE, KE HE, XU-CUN MA, XI CHEN, LI-LI WANG, YA-YU WANG, Li Lv, CUI-ZU CHANG, XIAO FENG
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Publication number: 20140166984Abstract: A graphene device having a ribbon structure with soft boundaries formed between two thin parallel transport barriers in a “railroad track” configuration. Such a structure permits transport along the ribbon, and also permits transport of electrons across the barriers by means of resonant tunneling through quasi-bound states within the railroad track confinement. The transport barriers can be of any form of so long as transport through the barriers leads to the formation of isolated resonant bands with a transport gap. In some embodiments, the transport barriers can be in the form of a pair of parallel line defects, wherein the line defects delineate the central ribbon section and the two lateral sections. In some such embodiments, the line defects are chemically decorated by the adsorption of diatomic gases. In other embodiments, the transport barriers can be formed by the application of large local potentials directly to the graphene sheet.Type: ApplicationFiled: December 6, 2013Publication date: June 19, 2014Inventors: L. Daniel Gunlycke, Carter T. White
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Publication number: 20140166985Abstract: A rectifying device includes: a one-dimensional channel (18) formed with a semiconductor, electrons traveling through the one-dimensional channel; an electrode (26) that applies an effective magnetic field generated from a spin orbit interaction to the electrons traveling through the one-dimensional channel by applying an electric field to the one-dimensional channel, the effective magnetic field being in a direction intersectional to the direction in which the electrons are traveling; and an external magnetic field generating unit (38) that generates an external magnetic field in the one-dimensional channel.Type: ApplicationFiled: August 21, 2012Publication date: June 19, 2014Applicant: JAPAN SCIENCE AND TECHNOLOGY AGENCYInventors: Makoto Kohda, Junsaku Nitta, Kensuke Kobayashi
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Publication number: 20140158990Abstract: An embodiment integrated circuit device and a method of making the same. The embodiment integrated circuit includes a substrate supporting a source with a first doping type and a drain with a second doping type on opposing sides of a channel region in the substrate, and a pocket disposed in the channel region, the pocket having the second doping type and spaced apart from the drain between about 2 nm and about 15 nm. In an embodiment, the pocket has a depth of between about 1 nanometer to about 30 nanometers.Type: ApplicationFiled: December 12, 2012Publication date: June 12, 2014Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventor: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
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Publication number: 20140091281Abstract: Semiconductor nanoparticles are deposited on a top surface of a first insulator layer of a substrate. A second insulator layer is deposited over the semiconductor nanoparticles and the first insulator layer. A semiconductor layer is then bonded to the second insulator layer to provide a semiconductor-on-insulator substrate, which includes a buried insulator layer including the first and second insulator layers and embedded semiconductor nanoparticles therein. Back gate electrodes are formed underneath the buried insulator layer, and shallow trench isolation structures are formed to isolate the back gate electrodes. Field effect transistors are formed in a memory device region and a logic device region employing same processing steps. The embedded nanoparticles can be employed as a charge storage element of non-volatile memory devices, in which charge carriers tunnel through the second insulator layer into or out of the semiconductor nanoparticles during writing and erasing.Type: ApplicationFiled: October 2, 2012Publication date: April 3, 2014Applicant: International Business Machines CorporationInventors: Kangguo Cheng, Robert H. Dennard, Hemanth Jagannathan, Ali Khakifirooz, Tak H. Ning, Ghavam G. Shahidi
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Patent number: 8680592Abstract: A method of forming a magnetic tunnel junction device is disclosed that includes forming a trench in a substrate, the trench including a first sidewall, a second sidewall, a third sidewall, a fourth sidewall, and a bottom wall. The method includes depositing a first conductive material within the trench proximate to the first sidewall and depositing a second conductive material within the trench. The method further includes depositing a magnetic tunnel junction (MTJ) structure within the trench. The MTJ structure includes a fixed magnetic layer having a magnetic field with a fixed magnetic orientation, a tunnel junction layer, and a free magnetic layer having a magnetic field with a configurable magnetic orientation. The method further includes selectively removing a portion of the MTJ structure that is adjacent to the fourth sidewall to create an opening such that the MTJ structure is substantially u-shaped.Type: GrantFiled: May 14, 2010Date of Patent: March 25, 2014Assignee: QUALCOMM IncorporatedInventor: Xia Li
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Patent number: 8653504Abstract: A complementary tunneling field effect transistor and a method for forming the same are provided. The complementary tunneling field effect transistor comprises: a substrate; an insulating layer, formed on the substrate; a first semiconductor layer, formed on the insulating layer and comprising first and second doped regions; a first type TFET vertical structure formed on a first part of the first doped region and a second type TFET vertical structure formed on a first part of the second doped region, in which a second part of the first doped region is connected with a second part of the second doped region and a connecting portion between the second part of the first doped region and the second part of the second doped region is used as a drain output; and a U-shaped gate structure, formed between the first type TFET vertical structure and the second type TFET vertical structure.Type: GrantFiled: November 28, 2011Date of Patent: February 18, 2014Assignee: Tsinghua UniversityInventors: Renrong Liang, Jun Xu, Jing Wang
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Patent number: 8648342Abstract: A photodetector includes a waveguide on a substrate, and a photodetection portion connected to the waveguide. The photodetection portion includes a first semiconductor layer, graphene on the semiconductor layer, and a second semiconductor layer on the graphene. A first electrode and a second electrode separated from the first ridge portion and electrically connected to the graphene.Type: GrantFiled: October 3, 2012Date of Patent: February 11, 2014Assignee: Samsung Electronics Co., Ltd.Inventors: Taek Kim, Bok-ki Min
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Patent number: 8637851Abstract: Disclosed herein is a graphene device having a structure in which a physical gap is provided so that the off-state current of the graphene device can be significantly reduced without having to form a band gap in graphene, and thus the on/off current ratio of the graphene device can be significantly increased while the high electron mobility of graphene is maintained.Type: GrantFiled: July 5, 2011Date of Patent: January 28, 2014Assignee: Korea Advanced Institute of Science and TechnologyInventors: Byung Jin Cho, Jeong Hun Mun
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Patent number: 8634442Abstract: An optical device includes a gallium nitride substrate member having an m-plane nonpolar crystalline surface region characterized by an orientation of about ?1 degree towards (000-1) and less than about +/?0.3 degrees towards (11-20). The device also has a laser stripe region formed overlying a portion of the m-plane nonpolar crystalline orientation surface region. In a preferred embodiment, the laser stripe region is characterized by a cavity orientation that is substantially parallel to the c-direction, the laser stripe region having a first end and a second end. The device includes a first cleaved c-face facet, which is coated, provided on the first end of the laser stripe region. The device also has a second cleaved c-face facet, which is exposed, provided on the second end of the laser stripe region.Type: GrantFiled: August 25, 2010Date of Patent: January 21, 2014Assignee: Soraa Laser Diode, Inc.Inventors: James W. Raring, Daniel F. Feezell, Nicholas J. Pfister, Rajat Sharma, Mathew C. Schmidt, Christiane Poblenz, Yu-Chia Chang
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Patent number: 8629428Abstract: A tunnel field effect transistor (TFET) and method of making the same is provided. The TFET comprises a source-channel-drain structure and a gate electrode. The source region comprises a first source sub-region which is doped with a first doping profile with a dopant element of a first doping type having a first peak concentration and a second source sub-region close to a source-channel interface which is doped with a second doping profile with a second dopant element with the same doping type as the first dopant element and having a second peak concentration. The second peak concentration of the second doping profile is substantially higher than the maximum doping level of the first doping profile close to an interface between the first and the second source sub-regions.Type: GrantFiled: May 17, 2012Date of Patent: January 14, 2014Assignees: IMEC, Katholieke Universiteit Leuven, K.U. Leuven R&DInventors: Anne S. Verhulst, Kuo-Hsing Kao
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Patent number: 8629427Abstract: A Topological INsulator-based field-effect transistor (TINFET) is disclosed. The TINFET includes a first and second gate dielectric layers separated by a topological insulator (TI) layer. A first gate contact is connected to the first gate dielectric layer on the surface that is opposite the TI layer. A second gate contact may be connected to the second gate dielectric layer on the surface that is opposite the TI layer. A first TI surface contact is connected to one surface of the TI layer, and a second TI surface contact is connected to the second surface of the TI layer.Type: GrantFiled: April 29, 2011Date of Patent: January 14, 2014Assignee: Texas A&M UniversityInventors: Sanjay K. Banerjee, Leonard Franklin Register, II, Allan MacDonald, Bhagawan R. Sahu, Priyamvada Jadaun, Jiwon Chang
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Publication number: 20130334500Abstract: A Tunnel Field Effect Transistor device (TFET) made of at least following layers: a highly doped drain layer, a highly doped source layer, a channel layer, a gate dielectric layer and a gate electrode layer, the gate dielectric layer extending along the source layer, and a highly doped pocket layer extending in between and along the gate dielectric layer and the source layer, characterized in that the pocket layer extends to between and along the source layer and the channel layer.Type: ApplicationFiled: May 29, 2013Publication date: December 19, 2013Applicants: Katholieke Universiteit, K.U. LEUVEN R&D, IMECInventors: Quentin Smets, Anne S. Verhulst, Rita Rooyackers, Marc Heyns
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Patent number: 8563966Abstract: A new devices structure of nano tunneling field effect transistor based on nano metal particles is introduced. The nano semiconductor device, comprising a source and a drain, wherein each of the source and drain comprise an implanted nano cluster of metal atoms, wherein the implanted nano cluster of metal atoms forming the source has an average radius in the range from about 1 to about 2 nanometers, and the implanted nano cluster of metal atoms forming the drain has an average radius in the range from about 2 to about 4 nanometers. Processes for producing the nano semiconductor device are detailed.Type: GrantFiled: December 30, 2011Date of Patent: October 22, 2013Assignee: Khalifa University of Science, Technology & Research (KUSTAR)Inventor: Moh'd Rezeq
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Publication number: 20130234762Abstract: A circuit includes a negative differential resistance (NDR) device which includes a gate and a graphene channel, and a gate voltage source which modulates a gate voltage on the gate such that an electric current through the graphene channel exhibits negative differential resistance.Type: ApplicationFiled: March 12, 2012Publication date: September 12, 2013Applicant: International Business Machines CorporationInventors: Shu-Jen Han, Yu-Ming Lin, Yanqing Wu
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Publication number: 20130221330Abstract: The present invention relates to a multi-quantum dot device and a method of manufacturing the multi-quantum dot device.Type: ApplicationFiled: November 25, 2010Publication date: August 29, 2013Applicant: CHUNGBUK NATIONAL UNIVERSITY INDUSTRY-ACADEMIC COOPERATION FOUNDATIONInventors: Jung Bum Choi, Jong Jin Lee
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Publication number: 20130168641Abstract: A new devices structure of nano tunneling field effect transistor based on nano metal particles is introduced. The nano semiconductor device, comprising a source and a drain, wherein each of the source and drain comprise an implanted nano cluster of metal atoms, wherein the implanted nano cluster of metal atoms forming the source has an average radius in the range from about 1 to about 2 nanometers, and the implanted nano cluster of metal atoms forming the drain has an average radius in the range from about 2 to about 4 nanometers. Processes for producing the nano semiconductor device are detailed.Type: ApplicationFiled: December 30, 2011Publication date: July 4, 2013Inventor: Moh'd Rezeq
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Patent number: 8450721Abstract: A III-nitride semiconductor device which includes a barrier body between the gate electrode and the gate dielectric thereof.Type: GrantFiled: June 14, 2011Date of Patent: May 28, 2013Assignee: International Rectifier CorporationInventors: Robert Beach, Zhi He, Jianjun Cao
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Patent number: 8422525Abstract: An optical device capable of emitting light having a wavelength ranging from about 490 to about 580 nanometers has a gallium nitride substrate with a semipolar crystalline surface region characterized by an orientation of greater than 3 degrees from (11-22) towards (0001) but less than about 50 degrees. A laser stripe formed on the substrate has a cavity orientation substantially parallel to the m-direction.Type: GrantFiled: March 29, 2010Date of Patent: April 16, 2013Assignee: Soraa, Inc.Inventors: James W. Raring, Daniel F. Feezell, Nicholas J. Pfister
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Publication number: 20130087767Abstract: A structure includes a substrate having a carbon nanotube (CNT) disposed over a surface. The CNT is partially disposed within a protective electrically insulating layer. The structure further includes a gate stack disposed over the substrate. A first portion of a length of the CNT not covered by the protective electrically insulating layer passes through the gate stack. Source and drain contacts are disposed adjacent to the gate stack, where second and third portions of the length of CNT not covered by the protective electrically insulating layer are conductively electrically coupled to the source and drain contacts. The gate stack and the source and drain contacts are contained within the protective electrically insulating layer and within an electrically insulating organic planarization layer that is disposed over the protective electrically insulating layer. A method to fabricate a CNT-based transistor is also described.Type: ApplicationFiled: October 11, 2011Publication date: April 11, 2013Applicant: International Business Machines CorporationInventors: Josephine B. Chang, Martin Glodde, Michael A. Guillorn
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Publication number: 20130064005Abstract: A tunnel transistor is provided comprising a drain, a source and at least a first gate for controlling current between the drain and the source, wherein the first sides of respectively the first and the second gate dielectric material are positioned substantially along and substantially contact respectively the first and the second semiconductor part.Type: ApplicationFiled: August 16, 2012Publication date: March 14, 2013Applicants: Katholieke Universiteit Leuven, K.U. LEUVEN R&D, IMECInventors: Marc Heyns, Cedric Huyghebaert, Anne S. Verhulst, Daniele Leonelli, Rita Rooyackers, Wim Dehaene
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Patent number: 8384122Abstract: Several embodiments of a tunneling transistor are disclosed. In one embodiment, a tunneling transistor includes a semiconductor substrate, a source region formed in the semiconductor substrate, a drain region formed in the semiconductor substrate, a gate stack including a metallic gate electrode and a gate dielectric, and a tunneling junction that is substantially parallel to an interface between the metallic gate electrode and the gate dielectric. As a result of the tunneling junction that is substantially parallel with the interface between the metallic gate electrode and the gate dielectric, an on-current of the tunneling transistor is substantially improved as compared to that of a conventional tunneling transistor. In another embodiment, a tunneling transistor includes a heterostructure that reduces a turn-on voltage of the tunneling transistor.Type: GrantFiled: April 17, 2009Date of Patent: February 26, 2013Assignee: The Regents of the University of CaliforniaInventors: Chenming Hu, Anupama Bowonder, Pratik Patel, Daniel Chou, Prashant Majhi
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Patent number: 8324120Abstract: An apparatus includes a substrate with a planar surface, a multilayer of semiconductor layers located on the planar surface, a plurality of electrodes located over the multilayer, and a dielectric layer located between the electrodes and the multilayer. The multilayer includes a 2D quantum well. A first set of the electrodes is located to substantially surround a lateral area of the 2D quantum well. A second set of the electrodes is controllable to vary a lateral width of a non-depleted channel between the substantially surrounded lateral area of the 2D quantum well and another area of the 2D quantum well. A third set of the electrodes is controllable to vary an area of a non-depleted portion of the lateral area.Type: GrantFiled: May 6, 2011Date of Patent: December 4, 2012Assignee: Alcatel LucentInventors: Kirk William Baldwin, Loren N. Pfeiffer, Kenneth William West, Robert L Willett
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Publication number: 20120273763Abstract: A Topological INsulator-based field-effect transistor (TINFET) is disclosed. The TINFET includes a first and second gate dielectric layers separated by a topological insulator (TI) layer. A first gate contact is connected to the first gate dielectric layer on the surface that is opposite the TI layer. A second gate contact may be connected to the second gate dielectric layer on the surface that is opposite the TI layer. A first TI surface contact is connected to one surface of the TI layer, and a second TI surface contact is connected to the second surface of the TI layer.Type: ApplicationFiled: April 29, 2011Publication date: November 1, 2012Inventors: Sanjay K. Banerjee, Leonard Franklin Register, II, Allan MacDonald, Bhagawan R. Sahu, Priyamvada Jadaun, Jiwon Chang
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Patent number: 8299520Abstract: According to some embodiments, a semiconductor device includes first and second auxiliary gate electrodes and a semiconductor layer crossing the first and second auxiliary gate electrodes. A primary gate electrode is provided on the semiconductor layer so that the semiconductor layer is between the primary gate electrode and the first and second auxiliary gate electrodes. Moreover, the first and second auxiliary gate electrodes are configured to induce respective first and second field effect type source/drain regions in the semiconductor layer. Related methods are also discussed.Type: GrantFiled: August 20, 2009Date of Patent: October 30, 2012Assignee: Samsung Electronics Co., Ltd.Inventors: Suk-pil Kim, Yoon-dong Park, Jae-young Choi, June-mo Koo, Byung-hee Hong
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Publication number: 20120267609Abstract: A complementary tunneling field effect transistor and a method for forming the same are provided. The complementary tunneling field effect transistor comprises: a substrate; an insulating layer, formed on the substrate; a first semiconductor layer, formed on the insulating layer and comprising first and second doped regions; a first type TFET vertical structure formed on a first part of the first doped region and a second type TFET vertical structure formed on a first part of the second doped region, in which a second part of the first doped region is connected with a second part of the second doped region and a connecting portion between the second part of the first doped region and the second part of the second doped region is used as a drain output; and a U-shaped gate structure, formed between the first type TFET vertical structure and the second type TFET vertical structure.Type: ApplicationFiled: November 28, 2011Publication date: October 25, 2012Applicant: TSINGHUA UNIVERSITYInventors: Renrong Liang, Jun Xu, Jing Wang
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Patent number: 8278650Abstract: An organic semiconductor includes: a compound represented by formula (I): wherein A1 represents O, S or N—R15; each of R11, R12, R13, R14 and R15 independently represents a hydrogen atom or a substituent W as defined in the specification, R11 and R12 may be linked to form a ring; B1 represents a ring structure containing at least one nitrogen atom; and n1 represents an integer of 0 to 2.Type: GrantFiled: May 14, 2009Date of Patent: October 2, 2012Assignee: FUJIFILM CorporationInventors: Kimiatsu Nomura, Tetsuro Mitsui, Hideyuki Suzuki, Rui Shen
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Patent number: 8263967Abstract: A bi-layer pseudo-spin field-effect transistor (BiSFET) is disclosed. The BiSFET includes a first and second conduction layers separated by a tunnel dielectric. The BiSFET transistor also includes a first gate separated from the first conduction layer by an insulating dielectric layer, and a second gate separated from the second conduction layer by an insulating layer. These conduction layers may be composed of graphene. The voltages applied to the first and/or second gates can control the peak current and associated voltage value for current flow between top and bottom conduction channels, and interlayer current voltage characteristic exhibiting negative differential resistance. BiSFETs may be used to make a variety of logic gates. A clocked power supply scheme may be used to facilitate BiSFET-based logic.Type: GrantFiled: May 1, 2012Date of Patent: September 11, 2012Assignee: Board of Regents, The University of Texas SystemsInventors: Sanjay K. Banerjee, Leonard Franklin Register, II, Allan MacDonald, Dharmendar Reddy Palle, Emanuel Tutuc
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Patent number: 8232165Abstract: A semiconductor structure includes an n-channel field effect transistor (NFET) nanowire, the NFET nanowire comprising a film wrapping around a core of the NFET nanowire, the film wrapping configured to provide tensile stress in the NFET nanowire. A method of making a semiconductor structure includes growing a film wrapping around a core of an n-channel field effect transistor (NFET) nanowire of the semiconductor structure, the film wrapping being configured to provide tensile stress in the NFET nanowire.Type: GrantFiled: July 15, 2011Date of Patent: July 31, 2012Assignee: International Business Machines CorporationInventors: Dureseti Chidambarrao, Lidija Sekaric
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Patent number: 8193523Abstract: A quantum well transistor has a germanium quantum well channel region. A silicon-containing etch stop layer provides easy placement of a gate dielectric close to the channel. A group III-V barrier layer adds strain to the channel. Graded silicon germanium layers above and below the channel region improve performance. Multiple gate dielectric materials allow use of a high-k value gate dielectric.Type: GrantFiled: December 30, 2009Date of Patent: June 5, 2012Assignee: Intel CorporationInventors: Ravi Pillarisetty, Been-Yih Jin, Benjamin Chu-Kung, Matthew V. Metz, Jack T. Kavalieros, Marko Radosavljevic, Roza Kotlyar, Willy Rachmady, Niloy Mukherjee, Gilbert Dewey, Robert S. Chau
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Patent number: 8188460Abstract: A bi-layer pseudo-spin field-effect transistor (BiSFET) is disclosed. The BiSFET includes a first and second conduction layers separated by a tunnel dielectric. The BiSFET transistor also includes a first gate separated from the first conduction layer by an insulating dielectric layer, and a second gate separated from the second conduction layer by an insulating layer. These conduction layers may be composed of graphene. The voltages applied to the first and/or second gates can control the peak current and associated voltage value for current flow between top and bottom conduction channels, and interlayer current voltage characteristic exhibiting negative differential resistance. BiSFETs may be used to make a variety of logic gates. A clocked power supply scheme may be used to facilitate BiSFET-based logic.Type: GrantFiled: November 24, 2009Date of Patent: May 29, 2012Assignee: Board of Regents, The University of Texas SystemInventors: Sanjay K. Banerjee, Leonard Franklin Register, II, Allan MacDonald, Dharmendar Reddy Palle, Emanuel Tutuc
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Patent number: 8173992Abstract: A microelectronic device is provided with at least one transistor or triode with Fowler-Nordheim tunneling current modulation, and supported on a substrate. The triode or the transistor includes at least one first block forming a cathode and at least one second block forming an anode. The first block and the second block are supported on the substrate, and are separated from each other by a channel insulating zone also supported on the substrate. A gate dielectric zone is supported on at least the channel insulating zone, and a gate is supported on the gate dielectric zone.Type: GrantFiled: February 7, 2007Date of Patent: May 8, 2012Assignee: STMicroelectronics (Crolles 2) SASInventors: Thomas Skotnicki, Stephane Monfray
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Publication number: 20110287941Abstract: Disclosed herein is a topologically protected ?/8-gate which becomes universal when combined with the gates available through quasi-particle braiding and planar quasi-particle interferometry. A twisted interferometer, and a planar ?/8-gate in CTS, implemented with the help of the twisted interferometer, are disclosed. Embodiments are described in the context of state X (CTS) supported by an ISH, although the concept of a twisted-interferometer is more general and has relevance to all anionic, i.e. quasiparticle systems.Type: ApplicationFiled: March 31, 2011Publication date: November 24, 2011Applicant: MICROSOFT CORPORATIONInventors: Parsa Bonderson, Michael Freedman, Chetan Nayak, Kevin Walker, Lukasz Fidkowski