Three Or More Electrode Device Patents (Class 257/39)
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Patent number: 6518673Abstract: The self inductance associated with a capacitance A52 in a superconductor integrated circuit (FIG. 1) is reduced by adding a layer of superconductor metal (A54) overlying the capacitor, effectively producing a negative inductance to counteract the self-inductance of the capacitor leads, thereby reducing inductance of the circuit. As a result it possible to transfer a single flux quantum (“SFQ”) pulse through the capacitor. Capacitors (19 and 25 FIG. 5) of the foregoing type are incorporated in superconductor integrated circuit SFQ transmission lines (FIG. 5) to permit SQUID-to-SQUID transfer of SFQ pulses, while maintaining the circuit grounds of the respective SQUIDs in DC isolation. Bias current (10) may be supplied to multiple SQUIDs (1 & 3, 7 & 9 FIG. 5) serially, reducing the supply current required previously for operation of multiple SQUIDs.Type: GrantFiled: June 15, 2001Date of Patent: February 11, 2003Assignee: TRW Inc.Inventors: Quentin P. Herr, Lynn A. Abelson, George L. Kerber
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Patent number: 6479863Abstract: A tunneling charge injector includes a conducting injector electrode, a grid insulator disposed adjacent the conducting injector electrode, a grid electrode disposed adjacent the grid insulator, a retention insulator disposed adjacent the grid electrode, and a floating gate electrode disposed adjacent the retention insulator. In the tunneling charge injector, charge is injected from the conducting injector electrode onto the floating gate. Electrons are injected onto the floating gate when the conducting injector electrode is negatively biased with respect to the grid electrode, and holes are injected onto the floating gate when the conducting injector electrode is positively biased with respect to the grid electrode. The tunneling charge injector is employed in a nonvolatile memory cell having a nonvolatile memory element with a floating gate such as a floating gate MOS transistor.Type: GrantFiled: December 6, 2000Date of Patent: November 12, 2002Inventor: John M. Caywood
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Publication number: 20020139974Abstract: A Faraday rotator of multilayer film type is provided which can achieve excellent optical characteristics with a reduced number of layers. In the Faraday rotator, a metal reflection film, a periodic dielectric multilayer film made of silicon dioxide SiO2 and tantalum pentoxide Ta2O5, a magneto-optical thin film, and another periodic dielectric multilayer film made of tantalum pentoxide Ta2O5 and silicon dioxide SiO2 is formed sequentially. Light incident on a polarizer goes therethrough, is reflected at the metal reflection film while traveling trough the periodic dielectric multilayer films, and goes through an analyzer to exit out.Type: ApplicationFiled: March 26, 2002Publication date: October 3, 2002Applicant: Minebea Co., Ltd.Inventors: Takeshi Matsushita, Mitsuteru Inoue, Hideki Kato, Akio Takayama
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Patent number: 6410934Abstract: An electronic fast switch for operation at room temperature utilizing uniform silicon nanoparticles (˜1 nm with about 1 part per thousand exceeding 1 nm) between two conducting electrodes. The silicon nanoparticles, when on an n-type silicon substrate exhibit, at zero bias, a large differential conductance, approaching near full transparency. The conductance is observed after one of the electrode is first biased at a voltage in the range 3 to 5 eV (switching voltage), otherwise the device does not conduct (closed). A practical MOSFET switch of the invention includes the silicon nanoparticles in a body of the MOSFET, with the gate and substrate forming the two conducting electrodes. Electrodes may be realized by metal in other switches of the invention.Type: GrantFiled: February 9, 2001Date of Patent: June 25, 2002Assignee: The Board of Trustees of the University of IllinoisInventors: Munir H. Nayfeh, Joel Therrien, Adam D. Smith
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Patent number: 6407426Abstract: A memory device includes a plurality of cells, each having a first electrode coupled to a first location on semiconductor material, a second electrode coupled to a second location disposed away from the first location on the semiconductor material and a plurality of islands of semiconductor material. The islands have a maximum dimension of three to five nanometers and are surrounded by an insulator having a thickness of between five and twenty nanometers. The islands and the surrounding insulator are formed in pores extending into the semiconductor material between the first and second electrodes. As a result, the memory cells are able to provide consistent, externally observable changes in response to the presence or absence of a single electron on the island.Type: GrantFiled: October 31, 2000Date of Patent: June 18, 2002Assignee: Micron Technology, Inc.Inventors: Kie Y. Ahn, Leonard Forbes
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Patent number: 6384423Abstract: The invention is a process for reducing roughness of a surface of a superconductor material (23) having an undesirable surface roughness (30 and 32) and a trilayer superconductor integrated circuit (100). The process for reducing roughness of a surface of superconductor material having an undesirable surface roughness includes coating the surface with an oxide layer (40) to fill the undesirable surface roughness and to produce an exposed oxide surface (42) with a roughness less than the surface roughness; and etching the exposed oxide surface to remove a thickness of the oxide layer followed by removing at least a portion of the oxide layer filling the undesirable surface roughness and a portion of the surface of the superconductor material to produce an exposed etched surface (44) comprised of at least the superconductor material which has a surface roughness less than the undesirable surface roughness.Type: GrantFiled: February 7, 2000Date of Patent: May 7, 2002Assignee: TRW Inc.Inventors: George L. Kerber, Michael Leung
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Patent number: 6365912Abstract: A superconductive tunnel junction device in which quasiparticles in a superconductive region (S1), relax into a normal metal trap (N1) releasing their potential energy in electron-electron interactions to increase the number of excited charge carriers in the trap. The excited charge carriers tunnel through an insulating tunnel junction barrier (I2) into a second superconductive region (S2). The quasiparticles in the first superconductive region are formed either by absorption or energetic particles/radiation or by injection by charge carriers tunneling in from a base region which can be of normal metal (N0) or superconductor (or both) of semiconductor. The current from the trap to the second superconductor is higher than that out of the base region thus providing current amplification. The device can thus form a three terminal transistor-like device. It can be used as or in particle/radiation detectors, as an analogue signal amplifier, microrefrigerator or digital switch.Type: GrantFiled: March 6, 2001Date of Patent: April 2, 2002Assignee: Isis Innovation LimitedInventors: Norman Ewart Booth, Joel Nathan Ullom, Michael Nahum
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Patent number: 6344659Abstract: The present invention relates on an interferometer arrangement comprising a source electrode and a drain electrode, a base electrode to which the source electrode and the drain electrode are connected through tunnel barriers, the base electrode thus forming a double barrier quantum well, and first and second superconducting gate electrodes to control the source-drain current. The base electrode comprises a ferromagnetic material enabling resonant tunneling of source-drain electrons when there are bound states within the quantum well structure matching the energy of said source-drain electrons. The invention also relates to a logical element comprising such an interferometer arrangement and to a method of controlling the conductance of an interferometer.Type: GrantFiled: November 24, 1999Date of Patent: February 5, 2002Assignee: Telefonaktiebolaget LM Ericsson (publ)Inventors: Zdravko Ivanov, Robert Shekhter, Anatoli Kadiqrobov, Tord Claeson, Mats Jonson, Erland Wikborg
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Patent number: 6337293Abstract: A semiconductor quantum memory element is disclosed which can share the terminals easily among a plurality of memory elements and can pass a high current and which is strong against noise. In order to accomplish this a control electrode is formed so as to cover the entirety of thin film regions connecting low-resistance regions. As a result, the element can have a small size and can store information with high density. Thus, a highly integrated, low power consumption non-volatile memory device can be realized with reduced size. A method of forming a memory element is also disclosed including performing the following steps of forming a first insulating layer, a second insulating layer, a first conductive layer and a layer of amorphous silicon. The amorphous silicon layer is crystallized to a polycrystalline silicon film. Semiconductor drains are deposited to form charge trapping and storage regions.Type: GrantFiled: June 14, 1999Date of Patent: January 8, 2002Assignee: Hitachi, Ltd.Inventors: Tomoyuki Ishii, Kazuo Yano, Koichi Seki, Toshiyuki Mine, Takashi Kobayashi
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Publication number: 20010013608Abstract: It is intended to provide a semiconductor device, its manufacturing method and substrate for manufacturing the semiconductor device which ensures that good cleavable surfaces be made stably in a semiconductor layer under precise control upon making edges of cleaves surfaces in the semiconductor layer stacked on a substrate even when the substrate is non-cleavable, difficult to cleave or different in cleavable orientation from the semiconductor layer. A semiconductor layer 2 made of III-V compound semiconductors is stacked to form a laser structure on a sapphire substrate 1.Type: ApplicationFiled: April 23, 2001Publication date: August 16, 2001Inventors: Toshimasa Kobayashi, Tsuyoshi Tojo
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Patent number: 6198113Abstract: A transistor operated by changing the electrostatic potential of an island disposed between two tunnel junctions. The transistor has an island of material which has a band gap (e.g. semiconductor material). Source and drain contacts are provided. The transistor has a first tunnel junction barrier disposed between island and source, and a second tunnel junction barrier disposed between island and drain. The island is Ohmically isolated from other parts of the transistor as well as a substrate. A gate electrode is capacitively coupled to the island so that a voltage applied to the gate can change the potential of the island. The transistor has n- and p-type embodiments. In operation, applying a gate voltage lowers (e.g., for positive gate bias) or raises (e.g., for negative gate bias) the conduction band and valence band of the island. When the conduction band or valence band aligns with the Fermi energy of the source and drain, tunneling current can pass between the source, island and drain.Type: GrantFiled: April 22, 1999Date of Patent: March 6, 2001Assignee: Acorn Technologies, Inc.Inventor: Daniel E. Grupp
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Patent number: 6160266Abstract: This invention provides a superconducting device with good characteristics that can be reproduced at an arbitrary place on a substrate and a method of manufacturing the same. A convex region (a processed, linearly shaped platinum thin film) of oriented metal is provided on a substrate as a gate electrode. Then, an oxide insulating film (SrTiO.sub.3 thin film) is deposited on the convex region, and further a YBa.sub.2 Cu.sub.3 O.sub.7 oxide superconducting thin film is deposited on the oxide insulating film. Accordingly, a grain boundary part is formed on the convex region. A drain electrode and a source electrode are formed facing each other with the grain boundary part between.Type: GrantFiled: February 20, 1997Date of Patent: December 12, 2000Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Akihiro Odagawa, Hideaki Adachi, Kentaro Setsune
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Patent number: 6111268Abstract: The invention relates to an inverted JOFET with an at least bicrystalline electrically conductive substrate-layer bearing an insulating element and a superconductive element with a Josephson-junction. The substrate-layer is connected to a control-element. The invention further relates to a method for making such a JOFET. The grain boundary in the substrate-layer thereby maps into the Josephson-junction in the superconductive element.Type: GrantFiled: July 17, 1998Date of Patent: August 29, 2000Assignee: International Business Machines CorporartionInventors: Jochen Mannhart, Bernd Mayer
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Patent number: 6057556Abstract: The tunnel-effect device comprises an input electrode 3, an output electrode 4, and N control electrodes 5 separated with tunneling barriers, the latter barriers and the interbarrier space therein appear as an ordered structure of molecules and clusters establishing tunneling junctions; each control electrode 5 is located in the region of the ordered structure of molecules and clusters 2. The dimensions and properties of the molecules and clusters provide for single-electron correlated electron tunneling at a relatively high (room) temperature. The tunnel-effect device functions on the base of controlled correlated electron tunneling. Possibility of controlling the tunneling current opens the way to constructing various electronic gate circuits on the base of single-electron tunneling junctions and hence to preparing single-electron analog and digital devices, in particular, high-sensitivity sensors.Type: GrantFiled: February 2, 1998Date of Patent: May 2, 2000Assignee: Samsung Electronics Co., Ltd.Inventors: Sergei Pavlovich Gubin, Vladimir Vladimirovich Kolesov, Evgenii Sergeevich Soldatov, Artem Sergeevich Trifonov, Vladimir Viktorovich Khanin, Genadii Borisovich Khomutov, Sergei Aleksandrovich Yakovenko
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Patent number: 6023124Abstract: An electron emission device exhibits a high electron emission efficiency. The device includes an electron supply layer of metal or semiconductor, an insulator layer formed on the electron supply layer, and a thin-film metal electrode formed on the insulator layer. The insulator layer is made of an amorphous dielectric substance and has a film thickness of 50 nm or greater and has an amorphous phase with an average grain size of 5 to 100 nm as a major component and a polycrystal phase as a minor component. When an electric field is applied between the electron supply layer and the thin-film metal electrode, the electron emission device emits electrons.Type: GrantFiled: February 27, 1998Date of Patent: February 8, 2000Assignee: Pioneer Electric CorporationInventors: Takashi Chuman, Shingo Iwasaki
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Patent number: 6020596Abstract: A FET type superconducting device comprises a substrate having a principal surface, a thin superconducting channel formed of an oxide superconductor layer over the principal surface of the substrate, a superconducting source region and a superconducting drain region formed of an oxide superconductor layer over the principal surface of the substrate at the both ends of the superconducting channel which connects the superconducting source region and the superconducting drain region, so that superconducting current can flow through the superconducting channel between the superconducting source region and the superconducting drain region and a gate electrode on a gate insulator disposed on the superconducting channel for controlling the superconducting current flowing through the superconducting channel by a signal voltage applied to the gate electrode, wherein the superconducting device is isolated by a isolation layer directly formed on the principal surface of the substrate, the superconducting layer of the suType: GrantFiled: September 30, 1996Date of Patent: February 1, 2000Assignee: Sumitomo Electric Industries, Ltd.Inventor: Takao Nakamura
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Patent number: 5962864Abstract: A semiconductor device comprises mutually separated first and third barrier layers interposed between the first and second patterned terminals. The device operates by the resonant tunneling of carriers from the second terminal to the first terminal. The first terminal is patterned into a section and a plurality of layers comprising the mutually separated first and second barrier layers are formed on top of the first terminal. A second terminal is then formed on top of the plurality of semiconductor layers. The second terminal is then patterned so that it only overlies the first terminal in confined region. A front-gate is then formed on top of the patterned second terminal.Type: GrantFiled: August 15, 1997Date of Patent: October 5, 1999Assignee: Kabushiki Kaisha ToshibaInventors: Mark L. Leadbeater, Nalin K. Patel
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Patent number: 5952683Abstract: A functional semiconductor element, which is designed to perform an ultrafast amplifying, bistable, similar functional operation by initiating and stopping an avalanche multiplication in one of i-type layers of what is called a triangular barrier diode (TBD) structure having an n-i-p-i-n, p-i-n-i-p, n-i-p-i-p, n-i-n-i-p, n-i-n-i-n, p-i-n-i-n, p-i-p-i-p, or p-i-p-i-n configuration. By forming a light absorbing layer and a light emitting layer or light modulating layer in this structure, it is possible to function the element as an optical functional element. Furthermore, the addition of a resonant tunneling diode implements a novel function.Type: GrantFiled: July 15, 1997Date of Patent: September 14, 1999Assignee: Kokusai Denshin Denwa Kabushiki KaishaInventors: Haruhisa Sakata, Katsuyuki Utaka, Yuichi Matsushima
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Patent number: 5946572Abstract: A gate structure including semiconductor regions each having a high impurity-concentration and being formed within respective one of recessed portions provided in a surface of a first semiconductor substrate, and then a second semiconductor substrate is brought into contact with the surface of the first semiconductor substrate. The gate structure may be formed such that each of the recessed portions is completely or partially filled with the gate structure. When the gate structure includes electrically good-conductive films of a high melting point metal or the like each formed in respective one of the recessed portions, the gate resistance can be further decreased.Type: GrantFiled: December 2, 1998Date of Patent: August 31, 1999Assignee: NGK Insulators, Ltd.Inventor: Yoshio Terasawa
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Patent number: 5912472Abstract: A portion of the superconductor in a planar resonator made from that superconductor can be switched into the normally conducting state so that its effective lateral dimensions are changed. The special advantage of this planar resonator is that a switchable filter can be constructed very economically based on its planar resonator structure. Since no perturbing bodies are necessary in the field, the invention points the way to a switchable filter with reduced high frequency losses.Type: GrantFiled: May 15, 1997Date of Patent: June 15, 1999Assignee: Robert Bosch GmbHInventors: Klaus Voigtlaender, Claus Schmidt, Matthias Klauda, Christian Neumann
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Patent number: 5910662Abstract: A semiconductor substrate comprising a single crystal substrate base such a silicon and a superconducting thin film layer deposited on said substrate base and composed of compound oxide such as Ln.sub.1 Ba.sub.2 Cu.sub.3 O.sub.7-.delta.. (Ln is lanthanide).Type: GrantFiled: December 14, 1993Date of Patent: June 8, 1999Assignee: Sumitomo Electric Industries, Ltd.Inventors: Hideo Itozaki, Keizo Harada, Naoji Fujimori, Shuji Yazu, Tetsuji Jodai
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Patent number: 5897367Abstract: A high-temperature (10K) superconductive integrated circuit has a ground plane (2), an interlevel dielectric (6), and a low value resistor (18) to provide conductive paths to reduce parasitic circuit inductances, thereby increasing the speed and performance of the integrated circuit. The circuit also includes a high value resistor (20) connected between interconnect wires (34) to produce a desired resistance with a short distance between the interconnect wires (34), thereby significantly reducing the circuit area.Type: GrantFiled: January 13, 1998Date of Patent: April 27, 1999Assignee: TRW Inc.Inventors: George L. Kerber, Lynn A. Abelson, Raffi N. Elmadjian, Eric G. Ladizinsky
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Patent number: 5861361Abstract: A FET type superconducting device comprises a thin superconducting channel, a superconducting source region and a superconducting drain region formed of an oxide superconductor over a principal surface of the substrate, and a gate electrode on a gate insulator disposed on the superconducting channel for controlling the superconducting current flowing through the superconducting channel by a signal voltage applied to the gate electrode. The superconducting channel is formed of(Pr.sub.w Y.sub.1-w)Ba.sub.2 Cu.sub.3 O.sub.7-z (0<w<1, 0<z<1) oxide superconductororY.sub.1 Ba.sub.2 Cu.sub.3-v CO.sub.V O.sub.7-u (0<v<3, 0<u<1) oxide superconductor.These oxide superconductors have smaller carrier densities than the conventional oxide superconductor so that the superconducting channel has a larger thickness than the one funned of the conventional oxide superconductor.Type: GrantFiled: April 17, 1996Date of Patent: January 19, 1999Assignee: Sumitomo Electric Industries, Ltd.Inventors: Takao Nakamura, Michitomo Iiyama
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Patent number: 5854493Abstract: A superconducting device has a substrate, and a superconducting channel provided by an oxide superconductor thin film formed to have an angle with respect to a deposition surface of the substrate. A superconductor source electrode region and a superconductor drain electrode region are formed at opposite ends of the superconducting channel, so that a superconducting current can flow through the superconducting channel between the superconductor source electrode region and the superconductor drain electrode region. A gate electrode region is formed of a oxide superconductor thin film which is deposited in parallel to the deposition surface of the substrate and which has an end portion which abuts with an insulating layer which separates the end portion and the superconducting channel so as to control superconducting current flow through the superconducting channel.Type: GrantFiled: April 14, 1997Date of Patent: December 29, 1998Assignee: Sumitomo Electric Industries, Ltd.Inventors: Takao Nakamura, Hiroshi Inada, Michitomo Iiyama
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Patent number: 5844279Abstract: A semiconductor device which includes, a substrate, an insulating layer formed on the substrate, a silicon layer having an exposed surface constituted by a Si (100) face, the silicon layer being provided with a tapered recess having a bottom at which a part of the silicon layer is remained without exposing the insulating layer, a first conductive region constituted by the silicon layer remaining at the bottom of the tapered recess, a second and a third conductive regions formed on both sides of the tapered recess respectively, a first insulating film formed on an inner surface of the tapered recess, and an electrode formed in the tapered recess. A flow of electron resulting from the tunneling effect from the second conductive region via the first insulating film to the third conductive region is controlled by controlling a voltage to be impressed onto the electrode.Type: GrantFiled: September 13, 1996Date of Patent: December 1, 1998Assignee: Kabushiki Kaisha ToshibaInventors: Tetsufumi Tanamoto, Riichi Katoh
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Patent number: 5834794Abstract: Disclosed is a superconducting device comprising a logic SQUID and a readout SQUID magnetically coupled with the logic SQUID, which are fabricated using a single layer of an oxide high-temperature superconductor, wherein the logic SQUID comprising a superconducting loop constituted by a first superconducting line, a second superconducting line arranged to be parallel to the first superconducting line, third and fourth superconducting lines provided to connect the first and second superconducting lines, and two Josephson junctions formed in the third and fourth superconducting lines, and widths W.sub.1 and W.sub.2 of the first and second superconducting lines are larger than a distance d between them, the width W.sub.2 is larger than the width W.sub.1, and the widths W.sub.1 and W.sub.2 are larger than the widths W.sub.3 and W.sub.4 of the third and fourth superconducting lines.Type: GrantFiled: April 29, 1997Date of Patent: November 10, 1998Assignees: Kabushiki Kaisha Toshiba, International Superconductivity Technology CenterInventors: Hiroyuki Fuke, Kazuo Saitoh, Youichi Enomoto
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Patent number: 5831278Abstract: A three-terminal device constructed from a Josephson junction with one or more asymmetric control lines is disclosed. The device is constructed with high temperature superconducting materials. The junction can be a bicrystal, SNS (Superconducting-Normal-Superconducting) or any other type of high temperature superconductor junction. The control line is either a conducting or superconducting material which is electrically isolated from the junction but inductively coupled into the junction. A portion of the control line is approximately directly above the junction and has current which at least partially flows parallel or nonparallel to current flowing across the junction. The control line current alters the magnetic field within the junction which changes the critical current of the junction. The junction is in a superconducting or resistive state depending on whether the bias current of the junction is greater than or less than the control current.Type: GrantFiled: March 15, 1996Date of Patent: November 3, 1998Assignee: Conductus, Inc.Inventor: Stuart J. Berkowitz
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Patent number: 5828079Abstract: A field-effect type superconducting device includes a channel layer. The channel layer includes Bi-based oxide compound containing Cu. A source electrode contacts the channel layer. A drain electrode contacts the channel layer. A gate insulating film made of insulating material extends on on the channel layer. A gate electrode extends on the gate insulating film.Type: GrantFiled: June 24, 1993Date of Patent: October 27, 1998Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Koichi Mizuno, Hideaki Adachi, Yo Ichikawa, Kentaro Setsune
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Patent number: 5804835Abstract: This is an invention of a superconductive device that is equipped with a first superconductive electrode, a second superconductive electrode and a junction that is made of a superconductive material that connects these superconductive electrodes, wherein there are 2-terminal or 3-terminal superconductive devices that use a junction that is in a superconductive state that is weaker than the first and the second superconductive electrodes or in a normal conductive state that is near the superconductive state. The differences between the critical current, the critical temperature, the pair potential and the carrier densities of the first and the second superconductive electrodes and the junction are used as a means of putting the junction in the states mentioned above. Based on the methods mentioned above, a superconductive device which has few pattern rule restrictions and which is easy to fabricate can be offered.Type: GrantFiled: June 5, 1995Date of Patent: September 8, 1998Assignee: Seiko Epson CorporationInventors: Taketomi Kamikawa, Eiji Natori, Setsuya Iwashita, Tatsuya Shimoda
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Patent number: 5793055Abstract: A step junction is provided for superconductor/semiconductor heterostructure hybrid devices like tunneling transistors, in a body of p-InAs with a vertical side connecting the low plateau and high plateau on which superconductors, preferably of niobium, are applied.Type: GrantFiled: November 30, 1995Date of Patent: August 11, 1998Assignee: Forschungszentrum Julich GmbHInventor: Alexander Kastalsky
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Patent number: 5773843Abstract: A metal electrode disposed on a surface of an oxide superconductor and forming electric contact with the oxide superconductor wherein at least a portion of the metal electrode is in contact with a side surface of the oxide superconductor which is perpendicular to the surface on which the metal electrode is disposed.Type: GrantFiled: February 20, 1996Date of Patent: June 30, 1998Assignee: Sumitomo Electric Industries, Inc.Inventors: Takao Nakamura, Michitomo Iiyama
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Patent number: 5731598Abstract: The single electron tunnel device of this invention includes: a multiple tunnel junction layer including multiple tunnel junctions; and first and second electrodes for applying a voltage to the multiple tunnel junction layer, wherein the multiple tunnel junction layer includes an electrically insulating thin film and metal particles and/or semiconductor particles dispersed in the electrically insulating thin film.Type: GrantFiled: June 19, 1996Date of Patent: March 24, 1998Assignee: Matsushita Electric Industrial Co. Ltd.Inventors: Hiroyuki Kado, Takao Tohda, Ichiro Tanahashi, Yoshio Manabe
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Patent number: 5717222Abstract: A superconducting device includes a substrate, a projecting insulating region formed in a principal surface of the substrate, and a first thin film portion of an oxide superconductor formed on the projecting insulating region. Second and third thin film portions of an oxide superconductor are positioned at opposite sides of the projecting insulating region to be continuous to the first thin film portion, respectively, so that a superconducting current can flow through the first thin film portion between the second thin film portion and the third thin film portion. The second thin film portion and the third thin film portion has a thickness larger than that of the first thin film portion. The projecting insulating region is formed of an oxide which is composed of the same constituent elements of the oxide superconductor but which has the oxygen content smaller than that of said oxide superconductor.Type: GrantFiled: May 23, 1996Date of Patent: February 10, 1998Assignee: Sumitomo Electric Industries, Ltd.Inventors: Takao Nakamura, Hiroshi Inada, Michitomo Iiyama
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Patent number: 5714767Abstract: For manufacturing a superconducting device, a compound layer which is composed of the same constituent elements of an oxide superconductor is formed on a surface of the substrate, and a gate electrode is formed on a portion of the compound layer. Portions of the compound layer at both sides of die gate electrode are etched using die gate electrode as a mask, so that a shallow step is formed on an upper surface of the compound layer and side surfaces of the step exposed. After that electric power is applied to the gate electrode to heat the gate electrode so as to carry out a heat-treatment on the portion of die compound layer under the gate electrode locally, so that a gate insulator formed directly under the the gate electrode and a superconducting channel which is constituted an extremely thin superconducting region composed of the oxide superconductor and formed under die gate insulator are produced in a self alignment to die gate electrode.Type: GrantFiled: November 1, 1995Date of Patent: February 3, 1998Assignee: Sumitomo Electric Industries, Ltd.Inventors: Takao Nakamura, Hiroshi Inada, Michitomo Iiyama
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Patent number: 5654259Abstract: The substance has a composition of a general chemical formula ofBi.sub.2 -(Sr.sub.2 Ca.sub.1).sub.1-x (La.sub.2 Y.sub.1).sub.x -Cu.sub.y -O.sub.z,where 0.4.ltoreq.x.ltoreq.1, y=2 and z=9-10.5, wherein the substance is an insulator or a semiconductor in the dark, and has a photoconductivity Q(.lambda.,T) in conjugate with superconductivity of a superconductor of an adjacent component of the Bi-SrCa-LaY-Cu-O system at and below a critical temperature (T) of less than 105.degree.-115.degree. K. and below 65.degree.-85.degree. K. at photoexcitation in an optical wavelength range (.lambda.) of 420-670 nm. The present invention relates to a method for producing the same and a superconductive optoelectronic device by using the same. The present invention also relates to an organized integration of the element or device into an apparatus to further develop a new field of "Superconductive Optoelectronics.Type: GrantFiled: June 7, 1995Date of Patent: August 5, 1997Assignee: The University of TokyoInventor: Taizo Masumi
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Patent number: 5623439Abstract: A ferroelectric memory device includes a channel layer of a dielectric material containing oxygen, source and drain electrode provided on the channel layer across a channel region defined in the channel layer, a ferroelectric memory layer provided on the channel layer so as to cover at least the channel region, and a write control electrode provided on the ferroelectric memory layer for applying an electric field thereto.Type: GrantFiled: May 12, 1995Date of Patent: April 22, 1997Assignee: Fujitsu LimitedInventors: Kohtaroh Gotoh, Hirotaka Tamura, Akira Yoshida
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Patent number: 5621223Abstract: A superconducting device includes first and second oxide superconducting regions of a relatively thick thickness, formed directly on a principal surface of a substrate to be separate from each other, and a third oxide superconducting region of an extremely thin thickness which is formed directly on the principal surface of the substrate so as to bridge the first and second oxide superconducting regions. A barrier layer and a diffusion source layer are formed on the third oxide superconducting region, and an isolation region is formed to cover an upper portion or both side surfaces of the diffusion source layer. The first, second and third oxide superconducting regions and the isolation region are formed of the same oxide superconductor material, and the isolation region is diffused with a material of the diffusion source layer, so that the isolation region does not show superconductivity.Type: GrantFiled: August 16, 1995Date of Patent: April 15, 1997Assignee: Sumitomo Electric Industries, Ltd.Inventors: Takao Nakamura, Hiroshi Inada, Michitomo Iiyama
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Patent number: 5610435Abstract: A bipolar transistor having a control electrode area of a semiconductor of a first conductive type, and first and second main electrode areas positioned in contact with the control electrode area and composed of a semiconductor of a second conductive type different from the first conductive type, comprises, for the purpose of preventing depletion of the surface of the control electrode area and suppressing or annulating the current generated in the surfacial depletion area, an electrode for controlling the surface state of the control electrode area, positioned, across an insulation film, on the surface of the control electrode area including the vicinity of the junction between the control electrode area and the above-mentioned first main electrode area.Type: GrantFiled: June 18, 1996Date of Patent: March 11, 1997Assignee: Canon Kabushiki KaishaInventors: Hidenori Watanabe, Junichi Hoshi, Yutaka Yuge, Akira Okita, Hideshi Kuwabara
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Patent number: 5596206Abstract: A new type of superconducting device is disclosed. The device embodies a superconducting ceramic film as an active part. A control electrode is provided on the superconducting film in which a passing current is controlled by applying a voltage on an intermediate portion of the film.Type: GrantFiled: April 4, 1995Date of Patent: January 21, 1997Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventor: Shunpei Yamazaki
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Patent number: 5594257Abstract: A superconducting device comprises a substrate having a principal surface, a non-superconducting oxide layer having a similar crystal structure to that of an oxide superconductor formed on the principal surface, which can compensates the lattice mismatch between the substrate and the oxide superconductor, a superconducting source region and a superconducting drain region formed of c-axis oriented oxide superconductor thin films on the non-superconducting oxide layer, and an insulating region formed of a doped oxide superconductor on the non-superconducting oxide layer separating the superconducting source region and the superconducting drain region between them. On the insulating region an extremely thin superconducting channel formed of a c-axis oriented oxide superconductor thin film is arranged.Type: GrantFiled: June 24, 1993Date of Patent: January 14, 1997Assignee: Sumitomo Electric Industries, Ltd.Inventors: Takao Nakamura, Michitomo Iiyama
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Patent number: 5552374Abstract: A superconducting device comprises a thin superconducting channel formed of an oxide superconductor, a superconducting source region and a superconducting drain region formed of an oxide superconductor at the both ends of the superconducting channel which connects the superconducting source region and the superconducting drain region, so that superconducting current can flow through the superconducting channel between the superconducting source region and the superconducting drain region. The superconducting device further includes a gate electrode through a gate insulator on the superconducting channel for controlling the superconducting current flowing through the superconducting channel. The length of the gate electrode ranges from one third of the length of the superconducting channel to one and a half length of the superconducting channel.Type: GrantFiled: April 4, 1994Date of Patent: September 3, 1996Assignee: Sumitomo Electric Industries, Ltd.Inventors: So Tanaka, Michitomo IIyama
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Patent number: 5550389Abstract: A superconducting device low in power dissipation and high in operating speed is fabricated by use of a combination of a superconductor material and a semiconductor material. The superconducting device having a low power dissipation and high operating speed characteristic according to the present invention is suitable for configuring a large-scale integrated circuit.Type: GrantFiled: December 22, 1993Date of Patent: August 27, 1996Assignee: Hitachi, Ltd.Inventors: Toshikazu Nishino, Mutsuko Hatano, Haruhiro Hasegawa, Hideaki Nakane, Ushio Kawabe, Kazuo Saitoh, Mitsuo Suga, Kazumasa Takagi
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Patent number: 5539215Abstract: A superconducting device comprising a substrate having a principal surface, a non-superconducting oxide layer having a similar crystal structure to that of the oxide superconductor, a first and a second superconducting regions formed of c-axis oriented oxide superconductor thin films on the non-superconducting oxide layer separated from each other and gently inclining to each other, a third superconducting region formed of an extremely thin c-axis oriented oxide superconductor thin film between the first and the second superconducting regions, which is continuous to the first and the second superconducting regions.Type: GrantFiled: December 29, 1994Date of Patent: July 23, 1996Assignee: Sumitomo Electric Industries, Ltd.Inventors: Takao Nakamura, Hiroshi Inada, Michitomo Iiyama
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Patent number: 5528052Abstract: Proposed is a method for operating a field-effect device comprised of a superconducting current channel having source and drain electrodes connected thereto, said superconducting current channel being separated from a gate electrode by an insulating layer, where the resistance of said current channel is controlled by varying the critical current of the superconducting material through the application of an electrical field across the superconducting current channel, which in turn changes the density of the mobile charge carriers in the superconducting material. Taught is also an inverted MISFET device for performing that method, the device being characterized in that on an electrically conductive substrate an insulating layer is provided which in turn carries a layer consisting of a superconducting material, and that a gate electrode is attached to said substrate, and source and drain electrodes are electrically connected to said superconductor layer.Type: GrantFiled: December 22, 1993Date of Patent: June 18, 1996Assignee: International Business Machines CorporationInventors: Johannes G. Bednorz, Jochen D. Mannhart, Carl A. Mueller, Darrell G. Schlom
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Patent number: 5521862Abstract: A magnetic memory cell 10 is provided, which includes a layer 12 of superconducting material. A current path 22 is formed insulatively adjacent layer 12 of superconducting material, such that a current passed through current path 22 induces a magnetic field of a selected magnitude and selected orientation in layer 12 of superconducting material.Type: GrantFiled: November 10, 1993Date of Patent: May 28, 1996Assignee: Texas Instruments IncorporatedInventor: Gary A. Frazier
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Patent number: 5514877Abstract: A superconducting device or a super-FET has a pair of superconducting electrode regions (20b,20c) consisting of a thin film (20)oxide superconductor being deposited on a substrate (5) and a weak link region (20a), the superconducting electrode regions (20b, 20c) being positioned at opposite sides of the weak link region (20a) these superconducting electrode regions (20b, 20c) and the weak link region (20a) being formed on a common plane surface of the substrate (5). The weak link region (20a) is produced by local diffusion of constituent element(s) of the substrate (5) into the thin film (20) of the oxide superconductor in such a manner that a substantial wall thickness of the thin film (20) of the oxide superconductor is reduced at the weak link region (20a) so as to leave a weak link or superconducting channel (10) in the thin film (20) of oxide superconductor over a non-superconducting region (50) which is produced by the diffusion.Type: GrantFiled: January 21, 1994Date of Patent: May 7, 1996Assignee: Sumitomo Electric Industries, Ltd.Inventors: Takao Nakamura, Hiroshi Inada, Michitomo Iiyama
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Patent number: 5510324Abstract: The invention relates to a method of manufacturing a superconducting device, which comprises the steps of forming on a principal surface of a substrate a non-superconducting oxide layer having a similar crystal structure to that of a c-axis oriented oxide superconductor thin film and a flat-top projection at its center portion, forming a c-axis oriented oxide superconductor thin film having an extremely thin thickness on the non-superconducting oxide layer so as to form a superconducting channel on the projecting portion of the non-superconducting oxide layer, forming an insulating layer on the c-axis oriented oxide superconductor thin film so as to form a gate insulating layer on the superconducting channel, and forming an a-axis oriented oxide superconductor thin film so as to form a superconducting source region and a superconducting drain region of which upper surfaces have the same level as that of the superconducting channel.Type: GrantFiled: December 2, 1994Date of Patent: April 23, 1996Assignee: Sumitomo Electric Industries, Ltd.Inventors: Takao Nakamura, Michitomo Iiyama, Hiroshi Inada
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Patent number: 5506197Abstract: A superconducting device comprising a substrate having a principal surface, a non-superconducting oxide layer having a similar crystal structure to that of the oxide superconductor, a first and a second superconducting regions formed of c-axis oriented oxide superconductor thin films on the non-superconducting oxide layer separated from each other and gently inclining to each other, a third superconducting region formed of an extremely thin c-axis oriented oxide superconductor thin film between the first and the second superconducting regions, which is continuous to the first and the second superconducting regions.Type: GrantFiled: September 16, 1994Date of Patent: April 9, 1996Assignee: Sumitomo Electric Industries, Ltd.Inventors: Takao Nakamura, Hiroshi Inada, Michitomo Iiyama
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Patent number: 5504347Abstract: A resonant tunneling transistor (400) with lateral carrier transport through tunneling barriers (404, 408) grown as a refilling of trenches etched partially into a transverse quantum well (410) and defining a quantum wire or quantum dot (406). The fabrication methods include use of angled deposition to create overhangs at the top of openings which define sublithographic separations for tunneling barrier locations.Type: GrantFiled: October 17, 1994Date of Patent: April 2, 1996Assignee: Texas Instruments IncorporatedInventors: Dejan Jovanovic, John N. Randall
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Patent number: 5494891Abstract: A superconducting device comprises a substrate, a non-superconducting layer formed in a principal surface of said substrate, an extremely thin superconducting channel formed of an oxide superconductor thin film on the non-superconducting layer. A superconducting source region and a superconducting drain region of a relatively thick thickness are formed of the oxide superconductor at the both sides of the superconducting channel separated from each other but electrically connected through the superconducting channel, so that a superconducting current can flow through the superconducting channel between the superconducting source region and the superconducting drain region.Type: GrantFiled: December 6, 1994Date of Patent: February 27, 1996Assignee: Sumitomo Electric Industries, Ltd.Inventors: Takao Nakamura, Michitomo Iiyama