Three Or More Electrode Device Patents (Class 257/39)
  • Patent number: 5486704
    Abstract: A semiconductor devive comprises;a collector region of first conductivity type;a base region of second conductivity type;an emitter region of the first conductivity type;a thin film provided on the emitter region and capable of flowing therein a tunnel current; anda polycrystalline layer laminated on the thin film.An energy .DELTA..phi..sub.B of potential barrier formed at a grain boundary is not less than a heat energy kT at a temperature therein.
    Type: Grant
    Filed: September 10, 1993
    Date of Patent: January 23, 1996
    Assignee: Canon Kabushiki Kaisha
    Inventor: Masakazu Morishita
  • Patent number: 5480861
    Abstract: A layered structure formed on a substrate comprising an oxide superconductor thin film deposited on the substrate, a noble metal monolayer deposited on the oxide superconductor thin film and an insulator thin film deposited on the noble metal monolayer. The noble metal monolayer prevents interdiffusion between the oxide superconductor thin film and the insulator thin film so that they have excellent properties.
    Type: Grant
    Filed: July 14, 1994
    Date of Patent: January 2, 1996
    Assignee: Sumitomo Electric Industries Ltd.
    Inventors: So Tanaka, Michitomo Iiyama
  • Patent number: 5471069
    Abstract: A superconducting device includes a superconducting channel constituted in an oxide superconductor the film deposited on a deposition surface of a substrate. A source electrode and a drain electrode are formed on the oxide superconductor thin film at opposite ends of the superconducting channel, so that a superconducting current can flow through be superconducting channel between the superconductor source electrode and the superconductor drain electrode. A gate electrode is formed through a gate insulator layer on the superconducting channel so as to control the superconducting current flowing through the superconducting channel. The gate electrode is in the form of a thin film and stands upright with respect to the gate insulator layer.
    Type: Grant
    Filed: May 13, 1994
    Date of Patent: November 28, 1995
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Takao Nakamura, Hiroshi Inada, Michitomo Iiyama
  • Patent number: 5466664
    Abstract: A method of manufacturing a superconducting device involves forming a thin film on the surface of a substrate, forming a superconducting gate electrode on a portion of the thin film, etching the portions of the thin film using the gate electrode as a mask thereby providing a superconducting channel under the gate, forming a step portion on the superconducting channel and under the gate, converting the oxide portion of the step portion into a gate insulation portion by heating the substrate in a vacuum, forming a second oxide superconducting film on the exposed surface of the channel so that superconducting source and drain electrodes are formed on each side of the gate such that the drain and source have a thickness greater than that of the channel and are electrically isolated from the gate electrode.
    Type: Grant
    Filed: July 26, 1994
    Date of Patent: November 14, 1995
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Hiroshi Inada, Takao Nakamura, Michitomo Iiyama
  • Patent number: 5462916
    Abstract: The disclosed superconductive optoelectronic device with the basic substance Bi.sub.2 O.sub.3 or Bi.sub.2 O.sub.3 ;M.sup.2+ (M=Ca,Sr,Cu) of superconductive-conjugate photoconductivity has a substrate, a photoconductive gate region formed on the substrate, and a source region and a drain region formed on the substrate at opposite sides of the gate region so as to face toward each other across the gate region. The source region and the drain region are made of a Bi-based superconductive material. The gate region is made of such the basic material Bi.sub.2 O.sub.3 or Bi.sub.2 O.sub.3 ;M.sup.2+ (M=Ca,Sr,Cu) of superconductive-conjugate photoconductivity, which reveals photoconductivity at a temperature below the transition temperature of the above relevant Bi-based superconductive material. Also disclosed are superconductive optoelectronic devices formed of an organized integration of the above superconductive optoelectronic devices to develop effectively a new field of "Superconductive Optoelectronics".
    Type: Grant
    Filed: February 14, 1994
    Date of Patent: October 31, 1995
    Assignee: The University of Tokyo
    Inventor: Taizo Masumi
  • Patent number: 5462918
    Abstract: A superconducting device has a stacked structure including a first superconducting layer, a first insulating layer, a second superconducting layer, a second insulating layer and a third superconducting layer stacked on a substrate in this given order. The stacked structure has an end surface portion extending from the first insulating layer to the second insulating layer. A fourth superconducting layer is formed to cover the end surface of the stacked structure. A third insulating layer separates the stacked structure end surface and the fourth superconducting layer. The fourth superconducting layer is electrically connected to the first and third superconducting layers but is isolated from the second superconducting layer by the third insulating layer. The first through fourth superconducting layers are formed of an oxide superconductor thin film.
    Type: Grant
    Filed: May 26, 1994
    Date of Patent: October 31, 1995
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Takao Nakamura, Hiroshi Inada, Michitomo Iiyama
  • Patent number: 5447907
    Abstract: A superconducting device comprising a substrate having a principal surface, a superconducting source region and a superconducting drain region formed of an oxide superconductor on the principal surface of the substrate separated from each other, a superconducting channel formed of the oxide superconductor between the superconducting source region and the superconducting drain region. The superconducting channel electrically connects the superconducting source region to a superconducting drain region, so that a superconducting current can flow through the superconducting channel between the superconducting source region and the superconducting drain region. The superconducting device comprises a gate electrode through a gate insulator on the superconducting channel for controlling the superconducting current flowing through the superconducting channel, and non-superconducting oxide layers having a similar crystal structure to that of the oxide superconductor.
    Type: Grant
    Filed: December 10, 1992
    Date of Patent: September 5, 1995
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Takao Nakamura, Hiroshi Inada, Michitomo Iiyama
  • Patent number: 5446015
    Abstract: For manufacturing a superconducting device, a first oxide superconductor thin film having a very thin thickness is formed on a principal surface of a substrate, and a stacked structure of a gate insulator and a gate electrode is formed on a portion of the first oxide superconductor thin film. A second oxide superconductor thin film is grown on an exposed surface of the first oxide superconductor thin film, using the gate electrode as a mask, so that first and second superconducting regions having a relatively thick thickness are formed at opposite sides of the gate electrode, electrically isolated from the gate electrode. A source electrode and a drain electrode are formed on the first and second oxide superconducting regions. The superconducting device thus formed can function as a super-FET.
    Type: Grant
    Filed: February 10, 1994
    Date of Patent: August 29, 1995
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Takao Nakamura, Hiroshi Inada, Michitomo Iiyama
  • Patent number: 5442195
    Abstract: A superconducting device may include a superconducting weak link equipped with plural superconducting devices that are used as input-output terminals formed on the same plane and at least one current source for applying current to at least one of these superconducting electrodes. A superconducting device suitable for high integration can be realized as it enables structuring of a superconducting weak link 1 equipped with plural superconducting electrodes 101, 102, 103 and 104 that can be used as input-output terminals and changing symmetry of superconducting electrode arrangement through the form of a normal conductor 201 which is forming a superconducting weak link. In addition, when this superconducting device is used as a quasi-particle injection type device, a superconducting device with plural superconducting electrodes that can be used for a gate electrode, drain electrode or control electrode can be realized. Further, a superconducting device equipped with new functions (e.g.
    Type: Grant
    Filed: October 18, 1993
    Date of Patent: August 15, 1995
    Assignee: Hitachi, Ltd.
    Inventors: Kazuo Saitoh, Toshikazu Nishino, Mutsuko Hatano
  • Patent number: 5441926
    Abstract: A superconducting transistor having a source region and a drain region are formed by a YBCO film on a barrier layer, which is composed of a PBCO film formed on an STO substrate. A gate electrode is disposed on the thinner wall at the back of the STO substrate. In a superconducting transistor so constructed the electric field created by the gate voltage works effectively at an interface with the barrier layer, more carriers can be drawn out relative to the applied gate voltage, and it becomes possible for a large superconduction current to flow.
    Type: Grant
    Filed: November 12, 1993
    Date of Patent: August 15, 1995
    Assignee: Fuji Electric Co., Ltd.
    Inventors: Hiroshi Kimura, Toshiyuki Matsui, Takeshi Suzuki, Kazuo Mukae, Akihiko Ohi
  • Patent number: 5442196
    Abstract: A pair of superconducting electrodes are so formed as to interpose a semiconductor therebetween, and a control electrode is formed on the semiconductor through an insulator film so as to control the superconductive weak coupling state in the semiconductor between the superconducting electrodes. The distance between the superconducting electrodes is determined by the thickness of the superconductor interposed between the two electrodes, whereby the interelectrode distance is settled with a high precision to improve the uniformity of the device characteristic.And in an arrangement where two superconducting electrodes are formed on a semiconductor layer and the superconductive weak coupling state between such two electrodes is controlled by a third electrode, the gain is increadable by furnishing a varied impurity distribution in the semiconductor layer.
    Type: Grant
    Filed: February 24, 1994
    Date of Patent: August 15, 1995
    Assignee: Hitachi, Ltd.
    Inventors: Toshikazu Nishino, Mutsuko Miyake, Ushio Kawabe, Yutaka Harada, Masaaki Aoki, Mikio Hirano
  • Patent number: 5430013
    Abstract: A superconducting thin film formed on a substrate, comprising an a-axis orientated oxide superconductor layer, a c-axis orientated oxide superconductor layer and an oxide semiconductor layer inserted between the a-axis orientated oxide superconductor layer and the c-axis orientated oxide superconductor layer, in contact with them in which superconducting current can flow between the a-axis orientated oxide superconductor layer and the c-axis orientated oxide superconductor layer through the oxide semiconductor layer by a long-range proximity effect.
    Type: Grant
    Filed: October 24, 1994
    Date of Patent: July 4, 1995
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Hiroshi Inada, Michitomo Iiyama
  • Patent number: 5430011
    Abstract: A superconducting thin film formed on a substrate, comprising at least one oxide superconductor layer formed on the principal surface of said substrate and at least one oxide layer formed of an oxide which compensates for crystalline incompleteness at the surface of said oxide superconductor layer, and which is arranged on or under the superconducting layer.
    Type: Grant
    Filed: September 17, 1992
    Date of Patent: July 4, 1995
    Assignee: Sumitomi Electric Industries, Ltd.
    Inventors: So Tanaka, Michitomo Iiyama
  • Patent number: 5422336
    Abstract: A superconducting transistor with superior withstand voltage having source region and a drain region formed of oxide superconductors 3, a PrBa.sub.2 Cu.sub.3 O.sub.7-x layer 2 or an ScBa.sub.2 Cu.sub.3 O.sub.7-x layer 2 forming an intermediate region sandwiched by the source and drain regions. The regions are disposed on a substrate 1. An insulation layer 4 is disposed on the intermediate region. A transistor uses the intermediate region as an insulator when the gate is turned off, and as a superconductor when the gate is turned on.
    Type: Grant
    Filed: September 22, 1993
    Date of Patent: June 6, 1995
    Assignee: Fuji Electric Co., Ltd.
    Inventors: Koichi Tsuda, Toshiyuki Matsui, Takeshi Suzuki, Hiroshi Kimura, Takashi Ishii, Akihiko Ohi, Kazuo Mukae
  • Patent number: 5420101
    Abstract: The invention relates to a structured superconductive track and a process for making it from epitaxial high temperature superconductor (HTSC) layers using lift off technique, in which a HTSC track deposited on an elevated substrate region is surrounded by an insulating layer of doped HTSC lying on a lower substrate region, and the substrate region with the superconductive track formed thereon is elevated such that the superconductive track is isolated from the insulating layer.
    Type: Grant
    Filed: December 23, 1993
    Date of Patent: May 30, 1995
    Assignee: Forschungszentrum Julich GmbH
    Inventors: Carlo Copetti, Jurgen Schubert, Willi Zander, Christoph Buchal
  • Patent number: 5418389
    Abstract: A field-effect transistor (FET) is described having a source; a drain; a channel formed between the source and the drain; and a gate electrode. The channel is composed of a film layer of oxide having the perovskite structure comprised of: (1) at least one metal selected from the group consisting of the metal elements in Group IV through Group XI of the Periodic Table of Elements and Bi; and (2) at least one metal selected from the group consisting of alkali metals, alkaline earth metals and rare earth metals. The layer has a film thickness of not larger than 1000 .ANG. and the electrical resistivity not less than 2 million centimeters. The channel of the oxide film layer is provided with a metal oxide insulator layer formed directly or through another metal oxide insulator layer and a gate electrode in electrical contact therewith. It is possible to make memories using this FET. In addition, it also becomes possible to reduce the size of devices using the FET of the invention.
    Type: Grant
    Filed: November 9, 1993
    Date of Patent: May 23, 1995
    Assignee: Mitsubishi Chemical Corporation
    Inventor: Yukio Watanabe
  • Patent number: 5416072
    Abstract: A superconducting device has a superconducting channel formed of an oxide superconductor on the principal surface of a substrate. A source electrode and a drain electrode likewise formed of oxide superconductor, are electrically connected by the channel to provide for superconducting current flow. A superconducting gate electrode is isolated by a side insulating region which completely covers each of opposite side surfaces of the gate electrode. The relative thicknesses of both the source and drain electrodes are much greater than that of the channel thickness. The superconducting channel and the gate insulator are both formed by one oxide thin film, and in a preferred embodiment, the gate electrode likewise is provided by the same film which forms the gate insulator and channel.
    Type: Grant
    Filed: July 26, 1993
    Date of Patent: May 16, 1995
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Hiroshi Inada, Takao Nakamura, Michitomo Iiyama
  • Patent number: 5413982
    Abstract: A superconducting device comprising a substrate having a principal surface, a non-superconducting oxide layer having a similar crystal structure to that of the oxide superconductor, an extremely thin superconducting channel formed of a c-axis oriented oxide superconductor thin film on the non-superconducting oxide layer, a superconducting source region and a superconducting drain region formed of an a-axis oriented oxide superconductor thin film at the both sides of the superconducting channel separated from each other, which are electrically connected each other by the superconducting channel, so that superconducting current can flow through the superconducting channel between the superconducting source region and the superconducting drain region, and a gate electrode of a material which includes silicon through a gate insulator on the superconducting channel for controlling the superconducting current flowing through the superconducting channel, in which the gate electrode is embedded between the supercondu
    Type: Grant
    Filed: December 14, 1992
    Date of Patent: May 9, 1995
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Hiroshi Inada, So Tanaka, Michitomo Iiyama
  • Patent number: 5408107
    Abstract: Heterostructure barrier quantum well device with a super-lattice structure of alternating lightly doped and heavily doped spacer layers having multiple, stable current-voltage curves extending continuously through zero bias at ambient temperature. The device can be repetitively switched between the multiple current-voltage curves. Once placed on a particular curve, the device retains memory of the curve it has been set on, even if held at zero bias for extended periods of time. The device can be switched between current-voltage curve settings at higher positive or negative voltages and can be read at lower voltages. Switching between current-voltage curve settings can also be effected by additional terminal connection(s) to the spacer layer(s).
    Type: Grant
    Filed: May 20, 1993
    Date of Patent: April 18, 1995
    Assignee: The Board of Regents of the University of Texas System
    Inventors: Dean P. Neikirk, Kiran K. Gullapalli
  • Patent number: 5407903
    Abstract: For manufacturing a superconducting device, a first c-axis orientated oxide superconductor thin film having a very thin thickness is formed on a principal surface of a substrate, and a stacked structure of a gate insulator and a gate electrode is formed on a portion of the first oxide superconductor thin film. An a-axis orientated oxide superconductor thin film is grown, using the gate electrode as a mask, so that second and third superconducting regions having a relatively thick thickness are formed at both sides of the gate electrode, electrically isolated from the gate electrode. The superconducting device thus formed can functions as a super-FET.
    Type: Grant
    Filed: September 27, 1991
    Date of Patent: April 18, 1995
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Takao Nakamura, Hiroshi Inada, Michitomo Iiyama
  • Patent number: 5408108
    Abstract: A superconducting device comprises a substrate having a principal surface and a non-superconducting oxide layer having a similar crystal structure to that of the oxide superconductor, which has a projection at its center portion. A superconducting source region and a superconducting drain region formed of an .alpha.-axis oriented oxide superconductor thin film are positioned at the both sides of the projection of the non-superconducting oxide layer separated from each other and an extremely thin superconducting channel formed of a c-axis oriented oxide superconductor thin film is positioned on the projection of the non-superconducting oxide layer. The superconducting channel electrically connects the superconducting source region to the superconducting drain region, so that superconducting current can flow through the superconducting channel between the superconducting source region and the superconducting drain region.
    Type: Grant
    Filed: December 14, 1992
    Date of Patent: April 18, 1995
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Takao Nakamura, Michitomo Iiyama, Hiroshi Inada
  • Patent number: 5401714
    Abstract: A field-effect structure formed on a substrate and comprising a channel with source and drain as well as a gate that is separated from the channel by an insulating layer. The channel is made of a high T.sub.c metal-oxide superconductor, e.g., YBaCuO, having a carrier density of about 10.sup.21 /cm.sup.3 and a correlation length of about 0.2 nm. The channel thickness is preferrable in the order of 1 nm. The superconductor is preferably a single crystalline and oriented such that the superconducting behavior is strongest in the plane parallel to the substrate. With a signal of a few volts applied to the gate, the entire channel cross-section is depleted of charge carriers whereby the channel resistance can be switched between a "zero resistance" (undepleted, superconducting) state and "very high resistance" (depleted state).
    Type: Grant
    Filed: May 4, 1994
    Date of Patent: March 28, 1995
    Assignee: International Business Machines Corporation
    Inventors: Preveen Chaudhari, Carl A. Mueller, Hans P. Wolf
  • Patent number: 5399546
    Abstract: A superconducting device comprises a substrate, a non-superconducting layer formed in a principal surface of said substrate, an extremely thin superconducting channel formed of an oxide superconductor thin film on the non-superconducting layer. A superconducting source region and a superconducting drain region of a relatively thick thickness are formed of the oxide superconductor at the both sides of the superconducting channel separated from each other but electrically connected through the superconducting channel, so that a superconducting current can flow through the superconducting channel between the superconducting source region and the superconducting drain region.
    Type: Grant
    Filed: November 30, 1992
    Date of Patent: March 21, 1995
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Takao Nakamura, Michitomo Iiyama
  • Patent number: 5382565
    Abstract: This field-effect transistor comprises a conductive substrate (2) serving as the gate electrode, an insulating barrier layer (3), and a superconducting channel layer (1) on top of the barrier layer (3). The superconductor layer (1) carries a pair of mutually spaced electrodes (4, 5) forming source and drain, respectively. The substrate is provided with an appropriate gate contact (6).The substrate (2) consists of a material belonging to the same crystallographic family as the barrier layer (3). In a preferred embodiment, the substrate (2) is niobium-doped strontium titanate, the barrier layer (3) is undoped strontium titanate, and the superconductor (1) is a thin film of a material having a lattice constant at least approximately similar to the one of the materials of the substrate (2) and barrier (3) layers. A preferred material of this type is YBa.sub.2 Cu.sub.3 O.sub.7-.delta., where 0.ltoreq..delta..ltoreq.0.5.
    Type: Grant
    Filed: October 20, 1993
    Date of Patent: January 17, 1995
    Assignee: International Business Machines Corporation
    Inventors: Johannes G. Bednorz, Jochen D. Mannhart, Carl A. Mueller
  • Patent number: 5380704
    Abstract: Disclosed herein is a superconducting field effect transistor (FET) which has at least an active region formed from a film of oxide normal conductor, a plurality of electrodes formed from a film of oxide superconductor, and a means to control the current which flows between the electrodes through the active region. Having a much greater electrode distance than the conventional superconducting device, it can be produced easily by lithography without resorting to special techniques.
    Type: Grant
    Filed: August 30, 1993
    Date of Patent: January 10, 1995
    Assignee: Hitachi, Ltd.
    Inventors: Yoshinobu Tarutani, Tokuumi Fukazawa, Uki Kabasawa, Kazumasa Takagi, Akira Tsukamoto, Masahiko Hiratani, Toshikazu Nishino
  • Patent number: 5367189
    Abstract: A semiconductor device comprises a first electrode buried in one main face of a substrate and surrounded by a first insulator, a field oxide film covering the surface of the first electrode, a semiconductor layer connected with the first electrode, a second insulator covering the surface of the semiconductor layer, a second electrode connected with the semiconductor layer, a gate electrode connected with the semiconductor layer between the second insulator and the field oxide film, and an outgoing electrode connected with the first electrode.
    Type: Grant
    Filed: November 4, 1992
    Date of Patent: November 22, 1994
    Assignee: Fujitsu Limited
    Inventor: Shunji Nakamura
  • Patent number: 5358928
    Abstract: A process for formulating non-hysteretic and hysteretic Josephson junctions using HTS materials which results in junctions having the ability to operate at high temperatures while maintaining high uniformity and quality. The non-hysteretic Josephson junction is formed by step-etching a LaAlO.sub.3 crystal substrate and then depositing a thin film of TlCaBaCuO on the substrate, covering the step, and forming a grain boundary at the step and a subsequent Josephson junction. Once the non-hysteretic junction is formed the next step to form the hysteretic Josephson junction is to add capacitance to the system. In the current embodiment, this is accomplished by adding a thin dielectric layer, LaA1O.sub.3, followed by a cap layer of a normal metal where the cap layer is formed by first depositing a thin layer of titanium (Ti) followed by a layer of gold (Au). The dielectric layer and the normal metal cap are patterned to the desired geometry.
    Type: Grant
    Filed: September 22, 1992
    Date of Patent: October 25, 1994
    Assignee: Sandia Corporation
    Inventors: David S. Ginley, Vincent M. Hietala, Gert K. G. Hohenwarter, Jon S. Martens, Thomas A. Plut, Chris P. Tigges, Gregory A. Vawter, Thomas E. Zipperian
  • Patent number: 5345115
    Abstract: A superconducting interface circuit converting a signal sent from a normal conducting circuit into a small voltage swing signal suitable for a superconducting circuit includes a superconducting field effect device. The superconducting field effect device has a superconducting channel of an extremely thin oxide superconductor thin film, a superconducting source region and a superconducting drain region of an oxide superconductor thin film positioned at both ends of the superconducting channel, and a gate electrode on the superconducting channel through a gate insulator. The gate electrode of the super-FET is connected to a signal line which transmits a voltage signal from the normal conducting circuit.
    Type: Grant
    Filed: April 28, 1993
    Date of Patent: September 6, 1994
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Hitoki Tokuda, Michitomo Iiyama
  • Patent number: 5345099
    Abstract: In a CCD device, on a semiconductor substrate, and in the insulation films, plural first semiconductor regions and plural second semiconductor regions are formed buried in the insulation films, intermediating a tunneling insulation film therebetween in a manner to spatially isolate them from each other.
    Type: Grant
    Filed: May 4, 1993
    Date of Patent: September 6, 1994
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventor: Takahiro Yamada
  • Patent number: 5326986
    Abstract: A physical configuration for a parallel multi-junction superconducting quantum interference device that can be used for a variety of applications involving the detection of magnetic flux, including applications where it is desired to measure the absolute magnitude of the flux. The device of this invention features a novel geometry for a multi-junction interference device which significantly enhances the flux-to-voltage transfer function, thereby yielding a significant improvement in the device sensitivity in its use in a magnetometer, gradiometer, or other applications.
    Type: Grant
    Filed: August 20, 1992
    Date of Patent: July 5, 1994
    Assignee: University of Houston - University Park
    Inventors: John H. Miller, Jr., Terry D. Golding, Jaiming Huang
  • Patent number: 5326988
    Abstract: A superconducting device including first and second trenches formed on a principal surface of a semiconductor substrate, separated from each other, and first and second superconductor electrodes filled in the first and second trenches and planarized to have a surface coplanar with the principal surface of the semiconductor substrate. The first and second superconductor electrodes form a separation zone which is defined by opposing sides of the first and second superconductor electrodes. An insulating layer is formed to cover a portion of the first superconductor electrode, the separation zone and a portion of the second superconductor electrode, and a gate electrode is formed on the insulating layer so as to be positioned above at least the separation zone.
    Type: Grant
    Filed: December 29, 1992
    Date of Patent: July 5, 1994
    Assignee: NEC Corporation
    Inventor: Ichiro Ishida
  • Patent number: 5318952
    Abstract: A superconducting transistor is provided with a base layer made of a normal conductor metal, an emitter layer made of a superconductor for injecting hot electrons to the base layer, a collector layer made of a superconductor for trapping electrons from the base layer, a first tunnel barrier layer made of an insulator and provided between the base layer and the emitter layer, and a second tunnel barrier layer made of an insulator and provided between the base layer and the collector layer.
    Type: Grant
    Filed: August 27, 1993
    Date of Patent: June 7, 1994
    Assignee: Fujitsu Limited
    Inventor: Tsunehiro Hato
  • Patent number: 5317168
    Abstract: A superconducting field effect transistor which is very small in size and high in dimensional accuracy, has a first layer of material forming a control electrode and a second layer of another material is disposed on said first layer. A width of said first layer in a direction toward a superconducting source electrode and a superconducting drain electrode is narrower than a width of the second layer in the same direction. Polycrystalline silicon may be used as the control electrode while the second layer can be made of silicon nitride. Furthermore, a side surface of the control electrode may be coated with an insulator film. Accordingly, the above transistor has a fine structure gate electrode part that can be fabricated easily and accurately.
    Type: Grant
    Filed: November 19, 1992
    Date of Patent: May 31, 1994
    Assignee: Hitachi, Ltd.
    Inventors: Toshikazu Nishino, Ushio Kawabe, Fumio Murai, Tokuo Kure, Mutsuko Hatano, Haruhiro Hasegawa
  • Patent number: 5310706
    Abstract: A method for manufacturing a high Tc superconducting circuit elements is disclosed, which comprises the steps of preparing a single crystal conductive substrate of Sr.sub.2 RuO.sub.4 by a floating zone melting process; epitaxially growing on the (001)-surface of the Sr.sub.2 RuO.sub.4 substrate a high Tc copper oxide-based superconducting film with a thickness of 1 to 1000 nm; depositing metal pads onto said superconducting film to form electrical contacts; and applying a metal pad to the surface of the substrate to form an electrical contact.
    Type: Grant
    Filed: July 16, 1993
    Date of Patent: May 10, 1994
    Assignee: International Business Machines Corporation
    Inventors: Frank Litchenberg, Jochen Mannhart, Darrell Schlom
  • Patent number: 5311036
    Abstract: A pair of superconducting electrodes are so formed as to interpose a semiconductor therebetween, and a control electrode is formed on the semiconductor through an insulator film so as to control the superconductive weak coupling state in the semiconductor between the superconducting electrodes. The distance between the superconducting electrodes is determined by the thickness of the superconductor interposed between the two electrodes, whereby the interelectrode distance is settled with a high precision to improve the uniformity of the device characteristic.And in an arrangement where two superconducting electrodes are formed on a semiconductor layer and the superconductive weak coupling state between such two electrodes is controlled by a third electrode, the gain is increadable by furnishing a varied impurity distribution in the semiconductor layer.
    Type: Grant
    Filed: April 29, 1992
    Date of Patent: May 10, 1994
    Assignee: Hitachi, Ltd
    Inventors: Toshikazu Nishino, Mutsuko Miyake, Ushio Kawabe, Yutaka Harada, Masaaki Aoki, Mikio Hirano
  • Patent number: 5306927
    Abstract: A high current amplifier, three terminal device, comprising a Josephson tunnel junction and a Schottky diode is configured so that the Josephson junction and Schottky diode share a common base electrode which is made very thin. Electrons which cross the Schottky barrier are supplied to the Josephson junction to obtain the amplified output current.
    Type: Grant
    Filed: August 15, 1991
    Date of Patent: April 26, 1994
    Assignee: The United States of America as represented by the Secretary of the Navy
    Inventors: Bruce J. Dalrymple, Arnold H. Silver, Randy W. Simon
  • Patent number: 5298762
    Abstract: A semiconductor-insulator-semiconductor (SIS) structure diode device for providing fast optoelectronic switching with stimulated emission. The device includes a substrate which has a buffer layer disposed on top thereof. An n-type cladding layer is disposed on top of the buffer layer. An undoped i-region is disposed on top of the buffer layer. The i-region includes at least one quantum well disposed between two waveguide layers. A lightly doped p-type cladding layer is disposed on top of the i-region. A contact layer is further disposed on top of the p-type cladding layer. First and second contact terminals are included for providing a two-terminal device. The diode advantageously provides good lasing performance, significant negative differential resistance and strong light sensitivity. In an alternate embodiment, a third terminal is connected to the undoped i-region to thereby form a three terminal device.
    Type: Grant
    Filed: September 28, 1992
    Date of Patent: March 29, 1994
    Assignee: TRW Inc.
    Inventor: Szutsun S. Ou
  • Patent number: 5291274
    Abstract: An electron device comprises a first dielectric layer (103) having a first thickness determined to allow the tunneling of carriers therethrough and a first dielectric constant, a second dielectric layer (104) provided in contact with the first dielectric layer, the second dielectric layer having a second thickness substantially larger than the first thickness and a second dielectric constant that is substantially larger than the first dielectric constant, a first electrode (101) provided on the first dielectric layer for injecting the carriers, and a second electrode (108) provided in contact with the second dielectric layer for controlling a flow of the carriers through the second dielectric layer in response to a control voltage supplied thereto.
    Type: Grant
    Filed: November 20, 1991
    Date of Patent: March 1, 1994
    Assignee: Fujitsu Limited
    Inventor: Hirotaka Tamura
  • Patent number: 5274249
    Abstract: A superconducting field effect device includes a substrate with an epitaxial superconducting film upon it and an insulating layer above a thinner region of the film which protects the film from the atmosphere and isolates it from a gate electrode which is on the insulating layer above a channel region of the thin film, and the epitaxial film has thicker regions suitable for contact to source and drain electrodes. Gate electrodes may be isolated from and oppose both sides of the superconducting thin regions so that enhanced modulation of a current in the thin region is provided.The invention provides high speed and high efficiency switches and modulators.
    Type: Grant
    Filed: December 20, 1991
    Date of Patent: December 28, 1993
    Assignee: University of Maryland
    Inventors: Xiaoxing Xi, Chris Doughty, Thirumalai Venkatesan
  • Patent number: 5272357
    Abstract: A semiconductor device comprises;a collector region of first conductivity type;a base region of second conductivity type;an emitter region of the first conductivity type; a thin film provided on the emitter region and capable of flowing therein a tunnel current; anda polycrystalline layer laminated on the thin film. An energy .DELTA..phi..sub.B of potential barrier formed at a grain boundary is not less than a heat energy kT at a temperature therein.
    Type: Grant
    Filed: October 23, 1991
    Date of Patent: December 21, 1993
    Assignee: Canon Kabushiki Kaisha
    Inventor: Masakazu Morishita
  • Patent number: 5272358
    Abstract: In a superconducting device wherein the value of a superconducting current to flow between two superconducting electrodes provided in contact with a semiconductor is controlled by a control electrode provided between the superconducting electrodes, high impurity concentration regions are formed within the semiconductor so as to lie in contact with the superconducting electrodes and to extend to under ends of the control electrode.
    Type: Grant
    Filed: November 25, 1991
    Date of Patent: December 21, 1993
    Assignee: Hitachi, Ltd.
    Inventors: Toshikazu Nishino, Ushio Kawabe, Mutsuko Hatano
  • Patent number: 5266558
    Abstract: These superconducting circuit elements, namely SNS heterostructures, such as, e.g. Josephson junctions and field-effect transistors, have a sandwich structure consisting of at least one layer of high-T.sub.c superconductor material arranged adjacent to a metallic substrate, possibly with an insulating layer in between, the substrate, the superconductor and--if present--the insulator all consisting of materials having at least approximately matching molecular structures and lattice constants. Electrical contacts, such as source, drain and gate electrodes are attached to the superconductor layer and to the substrate, respectively. The electrically conductive substrate consists of a metallic oxide such as strontium ruthenate Sr.sub.2 RuO.sub.4, whereas the superconductor layer is of the copper oxide type and may be YBa.sub.2 Cu.sub.3 O.sub.7-.delta., for example. The insulator layer (10) may consist of SrTiO.sub.3.
    Type: Grant
    Filed: February 27, 1992
    Date of Patent: November 30, 1993
    Assignee: International Business Machines Corporation
    Inventors: Frank Lichtenberg, Jochen Mannhart, Darrell Schlom
  • Patent number: 5258626
    Abstract: A superconducting network which, through the use of optical illumination, can form a selectable array of superconducting microstrip transmission lines or other electrical elements. The invention uses optical illumination to produce quasiparticles which cause selected physical parts of the network to be electrically nonconductive and thereby define the nonilluminated conductor's shape, physical size, and electrical characteristics. Network reconfigurability to produce several different devices and functions from a single high or low temperature superconductive chip is a disclosed utilization of the invention. The employed optical illumination produces phase change within the superconducting material to provide specific chip architectures. Reconfiguring of the device characteristics is achieved by changing the optical input intensity, spatial orientation, wavelength or combinations of these factors. A plurality of delay line configurations are disclosed as examples.
    Type: Grant
    Filed: June 22, 1992
    Date of Patent: November 2, 1993
    Assignee: The United States of America as represented by the Secretary of the Air Force
    Inventors: Andrew H. Suzuki, Joseph E. Brandelik
  • Patent number: 5250817
    Type: Grant
    Filed: August 12, 1992
    Date of Patent: October 5, 1993
    Assignee: Microelectronics and Computer Technology Corporation
    Inventor: Richard L. Fink
  • Patent number: 5244870
    Abstract: The disclosed superconductive optoelectronic device stems from the inventor's important discovery of a phenomenon that the basic substance Cu.sub.2 O reveals photoconductivity below several temperatures T.sub.ps in steps thereof, T.sub.ps being comparable with a series of the critical temperatures of superconductivity T.sub.sc of relevant Cu-based superconductors, and such photoconductivity of the basic substance is in a conjugate relationship with the superconductivity of the above Cu-based superconductors. The device of the invention has a gate region made of the above basic substance Cu.sub.2 O and a source region and a drain region made of the above Cu-based superconductors, the source and drain regions connected to each other, so that electric current therebetween at a temperature below the step temperature T.sub.ps of the basic substance is switched and/or controlled by the incident light intensity illuminated to the gate region.
    Type: Grant
    Filed: May 10, 1991
    Date of Patent: September 14, 1993
    Assignee: The University of Tokyo
    Inventor: Taizo Masumi
  • Patent number: 5240906
    Abstract: An inverted MISFET structure with a high transition temperature superconducting channel comprises a gate substrate, an interfacial layer with one or more elements of the VIII or IB subgroup of the periodic table of elements, an insulating layer and a high transition temperature superconducting channel. An electric field, generated by a voltage applied to its gate alters the conductivity of the channel.
    Type: Grant
    Filed: April 7, 1992
    Date of Patent: August 31, 1993
    Assignee: International Business Machines Corporation
    Inventors: Johannes G. Bednorz, Jochen D. Mannhart, Carl A. Mueller, Darrell Schlom
  • Patent number: 5239187
    Abstract: Disclosed is a transistor or diode type Josephson effect device, at least two electrodes of which are made of superconductive material. If the Josephson effect is to be exerted in a semiconductor layer between the access electrodes, the distance between them should be smaller than the length of coherence, namely 10 to 1000 angstroms. According to the disclosure, the control channel between access electrodes is replaced by two channels perpendicular to the semiconductor layer, located between the two access electrodes and a layer of superconductive material placed between the substrate and the semiconductor layer. The disclosure can be applied to transistors, phototransistors and diodes with high switching speed.
    Type: Grant
    Filed: March 2, 1992
    Date of Patent: August 24, 1993
    Assignee: Thomson-CSF
    Inventors: Alain Schuhl, Stephane Tyc, Alain Friederich
  • Patent number: 5236896
    Abstract: A superconducting device includes a superconducting channel consituted of an oxide superconductor thin film formed on a substrate, a superconductor source electrode and a superconductor drain electrode formed at opposite ends of the superconducting channel, so that a superconducting current can flow through the superconducting channel between the source electrode and the drain electrode. A gate electrode is located through an insulating layer on the superconducting channel so as to control the superconducting current flowing through the superconducting channel. The oxide superconductor thin film of the superconducting channel is formed of a c-axis oriented oxide superconductor crystal, and the oxide superconductor thin film of the superconductor source electrode and the superconductor drain electrode are formed of an a-axis oriented oxide superconductor crystal. The superconducting channel is continuous with the superconductor source electrode and the superconductor drain electrode.
    Type: Grant
    Filed: October 8, 1991
    Date of Patent: August 17, 1993
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Takao Nakamura, Hiroshi Inada, Michitomo Iiyama
  • Patent number: 5231295
    Abstract: A field-effect transistor comprises, on a substrate, a layer of semiconductor material incorporating natural or artificial inclusions of superconducting material. The source, drain and gate electrodes are made on this layer. Applications: field-effect transistors with low gate control voltage. FIG. 3.
    Type: Grant
    Filed: August 16, 1991
    Date of Patent: July 27, 1993
    Assignee: Thomson-CSF
    Inventors: Stephane Tyc, Alain Schuhl
  • Patent number: 5179426
    Abstract: A transistor structure which utilizes the Josephson effect and/or tunneling effect. The Josephson transistors of the invention are composed of superconductive films and tunneling films and work at a high speed with a low energy consumption. They are suitable for the construction of integrated circuits, especially digital circuits.
    Type: Grant
    Filed: August 1, 1988
    Date of Patent: January 12, 1993
    Assignee: Seiko Epson Corporation
    Inventor: Seiichi Iwamatsu