Abstract: A field effect transistor device includes a first conductive channel disposed on a substrate, a second conductive channel disposed on the substrate, a first gate stack formed on the first conductive channel, the first gate stack including a metallic layer having a first oxygen content, a second gate stack a formed on the second conductive channel, the second gate stack including a metallic layer having a second oxygen, an ion doped source region connected to the first conductive channel and the second conductive channel, and an ion doped drain region connected to the first conductive channel and the second conductive channel.

Abstract: A semiconductor device includes a first MISFET and a second MISFET which are formed over a semiconductor substrate and have the same conductive type. The first MISFET has a first gate insulating film arranged over the semiconductor substrate, a first gate electrode arranged over the first gate insulating film, and a first source region and a first drain region. The second MISFET has a second gate insulating film arranged over the semiconductor substrate, a second gate electrode arranged over the second gate insulating film, and a second source region and a second drain region. The first and the second gate electrode are electrically coupled, the first and the second source region are electrically coupled, and the first and the second drain region are electrically coupled. Accordingly, the first and the second MISFET are coupled in parallel. In addition, threshold voltages are different between the first and the second MISFET.

Abstract: Provided is a semiconductor memory device. In the semiconductor memory device, a lower selection gate controls a first channel region that is defined at a semiconductor substrate and a second channel region that is defined at the lower portion of an active pattern disposed on the semiconductor substrate. The first threshold voltage of the first channel region is different from the second threshold voltage of the second channel region.

Abstract: A method of manufacturing a semiconductor device, a semiconductor device and systems incorporating the same include transistors having a gate metal doped with impurities. An altered work function of the transistor may alter a threshold voltage of the transistor. In certain embodiments, a gate metal of a first MOSFET is doped with impurities. A gate metal of a second MOSFET may be left undoped, doped with the same impurities with a different concentration, and/or doped with different impurities.

Abstract: Semiconductor devices including first and second fin active regions protruding vertically from a substrate and integrally formed with the substrate, a gate insulation layer formed on the first and second fin active regions, a first gate metal contacting the gate insulation layer on the first fin active region, and a second gate metal contacting the first gate metal on the first fin active region and contacting the gate insulation layer on the second fin active region.

Abstract: An object is to obtain a desired threshold voltage of a thin film transistor using an oxide semiconductor. Another object is to suppress a change of the threshold voltage over time. Specifically, an object is to apply the thin film transistor to a logic circuit formed using a transistor having a desired threshold voltage. In order to achieve the above object, thin film transistors including oxide semiconductor layers with different thicknesses may be formed over the same substrate, and the thin film transistors whose threshold voltages are controlled by the thicknesses of the oxide semiconductor layers may be used to form a logic circuit. In addition, by using an oxide semiconductor film in contact with an oxide insulating film formed after dehydration or dehydrogenation treatment, a change in threshold voltage over time is suppressed and the reliability of a logic circuit can be improved.

Abstract: A semiconductor device, includes a substrate, an element isolating film formed in the substrate, a first element formation region isolated by the element isolating film, a second element formation region positioned adjacent to the first element formation region and isolated by the element isolating film, a first well of a second conductive type formed in a whole area of the first element formation region, a first transistor of a first conductive type formed on the first element formation region, a second transistor of the first conductive type which is formed on the first element formation region and whose threshold voltage is the same as a threshold voltage of the first transistor, a second well of the second conductive type formed in a whole area of the second element formation region, and a third transistor of the first conductive type formed on the second element formation region.

Abstract: Band edge engineered Vt offset devices, design structures for band edge engineered Vt offset devices and methods of fabricating such structures is provided herein. The structure includes a first FET having a channel of a first compound semiconductor of first atomic proportions resulting in a first band structure and a first type. The structure further includes a second FET having a channel of a second compound semiconductor of second atomic proportions resulting in a second band structure and a first type. The first compound semiconductor is different from the second compound semiconductor such that the first FET has a first band structure different from second band structure, giving rise to a threshold voltage different from that of the second FET.

Abstract: A method of controlling gate induced drain leakage current of a transistor is disclosed. The method includes forming a dielectric region (516) on a surface of a substrate having a first concentration of a first conductivity type (P-well). A gate region (500) having a length and a width is formed on the dielectric region. Source (512) and drain (504) regions having a second conductivity type (N+) are formed in the substrate on opposite sides of the gate region. A first impurity region (508) having the first conductivity type (P+) is formed adjacent the source. The first impurity region has a second concentration greater than the first concentration.

Abstract: Systems and methods for reducing gate leakage current and positive bias temperature instability drift are provided. In one embodiment, a system comprises a p-channel field effect transistor (PFET) device on a semiconductor substrate, and a high voltage transistor on the substrate. The system also comprises a plurality of silicides formed in the substrate, the plurality of silicides formed proximate to the PFET device and the high voltage transistor. Further, the system comprises a buffer oxide layer formed over the substrate, the PFET device, and the high voltage transistor and a moisture barrier formed over the buffer layer, the moisture barrier comprised of silicon oxynitride. Additionally, the system comprises an interlayer dielectric device formed over the moisture barrier and a plurality of electrical contacts extending through the interlayer dielectric, the moisture barrier, and the buffer oxide layer, wherein the plurality of electrical contacts are electrically connected to the plurality of silicides.

Abstract: A transistor arrangement including a triple well structure, the triple well structure including a substrate of a first conductivity type, a first well region of a second conductivity type formed within the substrate and a second well region of the first conductivity type being separated from the substrate by the first well region. The transistor arrangement further includes a first transistor formed on or in the second well region, the first transistor including a body terminal being connected to the second well region and a second well region switch being connected to the body terminal of the first transistor.

Abstract: In one implementation, a stacked composite device comprises a group IV lateral transistor and a group III-V transistor stacked over the group IV lateral transistor. A drain of the group IV lateral transistor is in contact with a source of the group III-V transistor, a source of the group IV lateral transistor is coupled to a gate of the group III-V transistor to provide a composite source on a top side of the stacked composite device, and a drain of the group III-V transistor provides a composite drain on the top side of the stacked composite device. A gate of the group IV lateral transistor provides a composite gate on the top side of the stacked composite device, and a substrate of the group IV lateral transistor is on a bottom side of the stacked composite device.

Abstract: A method and circuit in which the drive strength of a FinFET transistor can be selectively modified, and in particular can be selectively reduced, by omitting the LDD extension formation in the source and/or in the drain of the FinFET. One application of this approach is to enable differentiation of the drive strengths of transistors in an integrated circuit by applying the technique to some, but not all, of the transistors in the integrated circuit. In particular in a SRAM cell formed from FinFET transistors the application of the technique to the pass-gate transistors, which leads to a reduction of the drive strength of the pass-gate transistors relative to the drive strength of the pull-up and pull-down transistors, results in improved SRAM cell performance.

Abstract: An electronic device, including an integrated circuit, can include a buried conductive region and a semiconductor layer overlying the buried conductive region, wherein the semiconductor layer has a primary surface and an opposing surface lying closer to the buried conductive region. The electronic device can also include a first doped region and a second doped region spaced apart from each other, wherein each is within the semiconductor layer and lies closer to primary surface than to the opposing surface. The electronic device can include current-carrying electrodes of transistors. A current-carrying electrode of a particular transistor includes the first doped region and is a source or an emitter and is electrically connected to the buried conductive region. Another current-carrying electrode of a different transistor includes the second doped region and is a drain or a collector and is electrically connected to the buried conductive region.

Abstract: There are disclosed herein various implementations of composite III-nitride semiconductor devices having turn-on prevention control. In one exemplary implementation, a normally OFF composite semiconductor device comprises a normally ON III-nitride power transistor and a low voltage (LV) device cascoded with the normally ON III-nitride power transistor to form the normally OFF composite semiconductor device. The LV device is configured to have a noise-resistant threshold voltage to provide the turn-on prevention control for the normally OFF composite semiconductor device by preventing noise current from flowing through a channel of the normally ON III-nitride power transistor in a noisy system.

Abstract: There are disclosed herein various implementations of composite semiconductor devices including a voltage protected device. In one exemplary implementation, a normally OFF composite semiconductor device comprises a normally ON III-nitride power transistor having a first output capacitance, and a low voltage (LV) device cascoded with the normally ON III-nitride power transistor to form the normally OFF composite semiconductor device, the LV device having a second output capacitance. A ratio of the first output capacitance to the second output capacitance is set based on a ratio of a drain voltage of the normally ON III-nitride power transistor to a breakdown voltage of the LV device so as to provide voltage protection for the LV device.

Abstract: A method of fabricating an integrated circuit including a first region and a second region each having different poly-silicon gate structures is provided. The method includes depositing a first poly-silicon layer over the first and the second region and depositing, within the second region, an oxide layer over the first poly-silicon layer. A second poly-silicon layer is deposited over the first poly-silicon layer and the oxide region. A portion of the second poly-silicon layer that lies over the oxide region is then stripped away.

Abstract: According to one exemplary embodiment, a rectifier circuit includes a diode. A first depletion-mode transistor is connected to a cathode of the diode. Also, at least one second depletion-mode transistor is in parallel with the first depletion-mode transistor and is configured to supply a pre-determined current range to a cathode of the diode. A pinch off voltage of the at least one second depletion-mode transistor can be more negative than a pinch off voltage of the first depletion-mode transistor and the at least one second depletion-mode transistor can be configured to supply the pre-determined current range while the first depletion-mode transistor is OFF. Also, the pre-determined current range can be greater than a leakage current of the first depletion-mode transistor.

Abstract: A method of forming an integrated circuit (IC) includes forming a first and second plurality of spacers on a substrate, wherein the substrate includes a silicon layer, and wherein the first plurality of spacers have a thickness that is different from a thickness of the second plurality of spacers; and etching the silicon layer in the substrate using the first and second plurality of spacers as a mask, wherein the etched silicon layer forms a first plurality and a second plurality of fin field effect transistor (FINFET) channel regions, and wherein the first plurality of FINFET channel regions each have a respective thickness that corresponds to the thickness of the first plurality of spacers, and wherein the second plurality of FINFET channel regions each have a respective thickness that corresponds to the thickness of the second plurality of spacers.

Abstract: A method for fabricating a field effect transistor device includes forming a first conducting channel and a second conducting channel, forming a first gate stack on the first conducting channel to partially define a first device, forming second gate stack on the second conducting channel to partially define a second device, implanting ions to form a source region and a drain region connected to the first conducting channel and the second conducting channel, forming a masking layer over second device, a portion of the source region and a portion of the drain region, performing a first annealing process operative to change a threshold voltage of the first device, removing a portion of the masking layer to expose the second device, and performing a second annealing process operative to change the threshold voltage of the first device and a threshold voltage of the second device.

Abstract: In a gate electrode (40) provided on a gate insulating film (30), a depletion layer (42) is formed at a junction surface between a P-type semiconductor layer (41) and a gate insulating film (30). Since a region of the depletion layer (42) inside the gate electrode (40) changes due to temperature change, inducing a change in an effect of a gate voltage to channel formation, a threshold voltage changes to a larger extent than in a case of a typical MOS transistor. This is used to control the MOS transistor to have a desired temperature characteristic. A temperature compensation circuit may be eliminated and the circuit scale may be reduced.

Abstract: One or more embodiments relate to an apparatus comprising: a first transistor including a fin; and a second transistor including a fin, the fin of the first transistor having a lower charge carrier mobility than the fin of the second transistor.

Abstract: A technique for and structures for camouflaging an integrated circuit structure. The integrated circuit structure is formed by a plurality of layers of material having a controlled outline. A layer of conductive material having a controlled outline is disposed among said plurality of layers to provide artifact edges of the conductive material that resemble one type of transistor (operable vs. non-operable), when in fact another type of transistor was used.

Abstract: A semiconductor device including a first transistor of a first conductivity type provided on a first active region of a semiconductor region, and a second transistor of a second conductivity type provided on a second active region of the semiconductor region. The first transistor includes a first gate insulating film and a first gate electrode, the first gate insulating film contains a high-k material and a first metal, and the first gate electrode includes a lower conductive film, a first conductive film and a first silicon film. The second transistor includes a second gate insulating film and a second gate electrode, the second gate insulating film contains a high-k material and a second metal, and the second gate electrode includes a second conductive film made of the same material as the first conductive film, and a second silicon film.

Abstract: A semiconductor storage device includes a semiconductor substrate, a first insulator, a laminated insulator including a second insulator having fixed charges more than those of the first insulator, a single-layer insulator, memory cells between the semiconductor substrate and the first insulator, each memory cells separated from an adjacent memory cell by a cavity portion and including a tunnel insulator, a charge accumulation layer, an insulator, and a control gate electrode, a first selection gate transistor between the semiconductor substrate and the first insulator, a second selection gate transistor between the semiconductor substrate and the first insulator, between one memory cell and the first selection gate transistor, and in contact with the laminated insulator on a first side face on a memory cell side thereof, and a high-voltage peripheral circuit transistor between the semiconductor substrate and the first insulator, and in contact with the single-layer insulator on a side face thereof.

Abstract: A depletion transistor includes a source region and a drain region of a first conductivity type, a channel region of the first conductivity type arranged between the source region and the drain region and a first gate electrode arranged adjacent the channel region and dielectrically insulated from the channel region by a gate dielectric. The depletion transistor further includes a first discharge region of a second conductivity type arranged adjacent the gate dielectric and electrically coupled to a terminal for a reference potential. The depletion transistor can be included in a charging circuit.

Abstract: A semiconductor device includes a first MISFET and a second MISFET, wherein the first MISFET includes a semiconductor substrate 100, a first gate insulating film 101a and a first gate electrode 102a formed on the first region of the semiconductor substrate, and first side walls (103a, 120a) formed on the side surface of the first gate electrode 102a, and the second MISFET includes a second gate insulating film 101b and a second gate electrode 102b formed on the second region of the semiconductor substrate 100, and second side walls (103b, 120b) formed on the side surface of the second gate electrode 102b. The width of the first side wall is smaller than the width of the second side wall, and the second side wall includes the second spacer 103b containing a higher concentration of hydrogen than the first spacer 103a.

Abstract: Semiconductor devices and methods of manufacture thereof are disclosed. A preferred embodiment includes providing a workpiece having a first orientation and at least one second orientation. The semiconductor device is implanted with a dopant species using a first implantation process in the first orientation of the workpiece. The semiconductor device is implanted with the dopant species using a second implantation process in the at least one second orientation of the workpiece, wherein the second implantation process is different than the first implantation process.

Abstract: According to one embodiment, a non-volatile semiconductor memory device includes a plurality of memory cells and a transistor. The transistor includes a gate insulating film, a gate electrode on the gate insulating film, a sidewall insulating film on both side surfaces of the gate electrode, a source diffusion layer corresponding to the sidewall insulating film, a first hollow formed in a position at a height less than a bottom surface of the gate insulating film directly below an outer side surface of the sidewall insulating film of another side of the gate electrode, a second hollow formed in the first hollow at a position at a height less than the first hollow, and a drain diffusion layer corresponding to another side of the gate electrode and including a low-concentration drain region formed on a bottom surface of the second hollow and a high-concentration drain region.

Abstract: A semiconductor structure with a metal gate structure includes a first type field-effect transistor having a first gate including: a high k dielectric material on a substrate, a first metal layer on the high k dielectric material layer and having a first work function, and a first aluminum layer on the first metal layer. The first aluminum layer includes an interfacial layer including aluminum, nitrogen and oxygen. The device also includes a second type field-effect transistor having a second gate including: the high k dielectric material on the substrate, a second metal layer on the high k dielectric material layer and having a second work function different from the first work function, and a second aluminum layer on the second metal layer.

Abstract: Provided are a semiconductor device and a method of fabricating the semiconductor device. The semiconductor device can include first transistors that include a first gate insulating layer having a first thickness and second transistors include a second gate insulating layer having a second thickness less than the first thickness. At least one of the transistors formed on the first or second gate insulating layers is directly over a dummy well.

Abstract: Sophisticated gate electrode structures may be formed by providing a cap layer including a desired species that may diffuse into the gate dielectric material prior to performing a treatment for stabilizing the sensitive gate dielectric material. In this manner, complex high-k metal gate electrode structures may be formed on the basis of reduced temperatures and doses for a threshold adjusting species compared to conventional strategies. Moreover, a single metal-containing electrode material may be deposited for both types of transistors.

Abstract: The present invention relates to a method for gate leakage reduction and Vt shift control, in which a first ion implantation is performed on PMOS region and NMOS region of a substrate to implant fluorine ions, carbon ions, or both in the gate dielectric or the semiconductor substrate, and a second ion implantation is performed only on the NMOS region of the substrate to implant fluorine ions, carbon ions, or both in the gate dielectric or the semiconductor substrate in the NMOS region, with the PMOS region being covered by a mask layer. Thus, the doping concentrations obtained by the PMOS region and the NMOS region are different to compensate the side effect caused by the different equivalent oxide thickness and to avoid the Vt shift.

Abstract: A semiconductor device with a high-voltage transistor and a low-voltage transistor includes an isolation insulating film between a first element region of the high-voltage transistor and a second element region of the low-voltage transistor, a first gate insulating film on a semiconductor substrate in the first element region, a first gate electrode on the first gate insulating film, a second gate insulating film on the semiconductor substrate in the second element region, and a second gate electrode on the second gate insulating film. The isolation insulating film includes a first isolation region adjacent to a surrounding area of the first element region and a second isolation region adjacent to a surrounding area of the second element region. A bottom of the second isolation region is lower than a bottom of the first isolation region. The first gate insulating film is thicker than the second gate insulating film.

Abstract: Techniques for combining transistors having different threshold voltage requirements from one another are provided. In one aspect, a semiconductor device comprises a substrate having a first and a second nFET region, and a first and a second pFET region; a logic nFET on the substrate over the first nFET region; a logic pFET on the substrate over the first pFET region; a SRAM nFET on the substrate over the second nFET region; and a SRAM pFET on the substrate over the second pFET region, each comprising a gate stack having a metal layer over a high-K layer. The logic nFET gate stack further comprises a capping layer separating the metal layer from the high-K layer, wherein the capping layer is further configured to shift a threshold voltage of the logic nFET relative to a threshold voltage of one or more of the logic pFET, SRAM nFET and SRAM pFET.

Abstract: Multiple threshold voltage (Vt) field-effect transistor (FET) devices and techniques for the fabrication thereof are provided. In one aspect, a FET device is provided including a source region; a drain region; at least one channel interconnecting the source and drain regions; and a gate, surrounding at least a portion of the channel, configured to have multiple threshold voltages due to the selective placement of at least one band edge metal throughout the gate.

Abstract: A transistor arrangement includes a first transistor having a drift region and a number of second transistors, each having a source region, a drain region and a gate electrode. The second transistors are coupled in series to form a series circuit that is coupled in parallel with the drift region of the first transistor.

Abstract: A semiconductor device, includes a substrate, an element isolating film formed in the substrate, a first element formation region isolated by the element isolating film, a second element formation region positioned adjacent to the first element formation region and isolated by the element isolating film, a first well of a second conductive type formed in a whole area of the first element formation region, a first transistor of a first conductive type formed on the first element formation region, a second transistor of the first conductive type which is formed on the first element formation region and whose threshold voltage is the same as a threshold voltage of the first transistor, a second well of the second conductive type formed in a whole area of the second element formation region, and a third transistor of the first conductive type formed on the second element formation region.

Abstract: Techniques for combining transistors having different threshold voltage requirements from one another are provided. In one aspect, a semiconductor device comprises a substrate having a first and a second nFET region, and a first and a second pFET region; a logic nFET on the substrate over the first nFET region; a logic pFET on the substrate over the first pFET region; a SRAM nFET on the substrate over the second nFET region; and a SRAM pFET on the substrate over the second pFET region, each comprising a gate stack having a metal layer over a high-K layer. The logic nFET gate stack further comprises a capping layer separating the metal layer from the high-K layer, wherein the capping layer is further configured to shift a threshold voltage of the logic nFET relative to a threshold voltage of one or more of the logic pFET, SRAM nFET and SRAM pFET.

Abstract: A semiconductor device includes first and second FETs having the same conductivity type. The first FET includes a first gate electrode, a first side wall, and first extension regions respectively provided in a first active region on both sides of the first gate electrodes. The second FET includes a second gate electrode, a second side wall, and second extension regions respectively provided in a second active region on both sides of the second gate electrode. An overlap of each of the first extension regions and the first gate electrode in a gate length direction is longer than an overlap of each of the second extension regions and the second gate electrode. The distance between the first gate electrode and the first side wall is shorter than the distance between the second gate electrode and the second side wall.

Abstract: A semiconductor device can output a reference voltage for an arbitrary potential and can detect the voltage of each cell in a battery including multiple cells very precisely. The device includes a depletion-type MOSFET 21 and an enhancement type MOSFET 22, and has a floating structure that isolates depletion-type MOSFET 21 and enhancement type MOSFET 22 from a ground terminal. The depletion-type MOSFET 21 and enhancement type MOSFET 22 are connected in series to each other, wherein the depletion-type MOSFET 21 is connected to high-potential-side terminal and the enhancement type MOSFET 22 is connected to low-potential-side terminal. The semiconductor device having the configuration described above is disposed in a voltage detecting circuit section in a control IC for a battery including multiple cells.

Abstract: In sophisticated semiconductor devices, high-k metal gate electrode structures may be provided in an early manufacturing stage wherein the threshold voltage adjustment for P-channel transistors may be accomplished on the basis of a threshold voltage adjusting semiconductor alloy, such as a silicon/germanium alloy, for long channel devices, while short channel devices may be masked during the selective epitaxial growth of the silicon/germanium alloy. In some illustrative embodiments, the threshold voltage adjustment may be accomplished without any halo implantation processes for the P-channel transistors, while the threshold voltage may be tuned by halo implantations for the N-channel transistors.

Abstract: Semiconductors devices and methods of making semiconductor devices are provided. According to one embodiment, a semiconductor device, having more than two types of threshold voltages, can be employed in a logic integrated circuit with an embedded SRAM. The semiconductor device can include at least two transistors. The two transistors can be the same conductivity type (e.g., n-type or p-type). In addition, the two transistors can have disparate voltage thresholds.

Abstract: A Direct Silicon Bonded substrate can include a first substrate and a second substrate in which the second substrate can be rotated to an azimuthal twist angle of 45 degrees in comparison to the first substrate. Disclosed are a semiconductor device and a method for making a semiconductor device that includes a DSB substrate with an adjusted thickness based upon the threshold voltage (Vt). In other words, a thicker substrate or layer can correspond to a high threshold voltage (HVt) and a thinner substrate or layer can correspond to a low threshold voltage (LVt) in order to improve mobility in LVt devices.

Abstract: A voltage reference is created from an operational amplifier circuit having two substantially identical P-channel metal oxide semiconductor (P-MOS) transistors with each one having a different gate dopant. The different gate dopants result in different threshold voltages for each of the two otherwise substantially identical P-MOS transistors. The difference between these two threshold voltages is then used to create the voltage reference equal to the difference. The two P-MOS transistors are configured as a differential pair in the operational amplifier circuit and the output of the operational amplifier is used as the voltage reference.

Abstract: A semiconductor memory device provided with a cell array section and a peripheral circuit section, the device includes: a back gate electrode; a stacked body provided on the back gate electrode; a plurality of semiconductor pillars extending in a stacking direction; connection members, each of the connection members connecting one of the semiconductor pillars to another one of the semiconductor pillars; a back-gate electrode contact applying a potential to the back gate electrode; a gate electrode provided in the peripheral circuit section; and a gate electrode contact applying a potential to the gate electrode, the back gate electrode and the gate electrode respectively including: a lower semiconductor layer; a conductive layer provided on the lower semiconductor layer; and an upper semiconductor layer provided on the conductive layer, the connection members being provided in or on the upper semiconductor layer, the back-gate electrode contact and the gate electrode contact being in contact with the conducti

Abstract: The circuit includes an E-mode transistor with gate-source junction, a D-mode transistor with gate-source junction, a component generating a voltage drop between the source of the D-mode transistor and the drain of the E-mode transistor, and a connection between the drain of the E-mode transistor and the gate of the D-mode transistor. The gate of the E-mode transistor is provided for an input signal, and the drain of the E-mode transistor is provided for an output signal.

Abstract: An integrated circuit (IC) includes an active region; a pair of active field effect transistors (FETs) in the active region; and an isolation FET located between the pair of active FETs in the active region, the isolation FET configured to provide electrical isolation between the pair of active FETs, wherein the isolation FET has at least one different physical parameter or electrical parameter from the pair of active FETs.

Abstract: The invention relates to integrated circuit fabrication, and more particularly to a metal gate structure. An exemplary structure for a CMOS semiconductor device comprises a substrate comprising a P-active region, an N-active region, and an isolation region interposed between the P- and N-active regions; a P-metal gate electrode over the P-active region, that extends over the isolation region; and an N-metal gate electrode having a first width over the N-active region, that extends over the isolation region and has a contact section in the isolation region electrically contacting the P-metal gate electrode, wherein the contact section has a second width greater than the first width.

Abstract: A semiconductor device includes a first transistor having a threshold voltage (Vth) adjusted to a first Vth by a first dopant having a first peak of concentration at a first depth; and a second transistor having the same channel-type as that of the first transistor and having a Vth adjusted to a second Vth by a second dopant having a second peak of concentration at a second depth equal to the first depth and higher concentration than the first dopant; wherein the first dopant and the second dopant are dopants comprising the same constituent element.