With Channel Conductivity Dopant Same Type As That Of Source And Drain Patents (Class 257/403)
  • Patent number: 10388789
    Abstract: A method for reducing series resistance for transistors includes forming a conductive gate over and insulated from a semiconductor substrate, forming source and/or drain extension regions within the substrate and adjacent to respective source and/or drain regions, and forming source and/or drain regions within the substrate. The source and/or drain extension regions are formed from a material alloyed with a first dopant and a second dopant, the first dopant configured to increase a lattice structure of the material forming the source and/or drain extension regions.
    Type: Grant
    Filed: December 5, 2017
    Date of Patent: August 20, 2019
    Assignee: International Business Machines Corporation
    Inventors: Mona A. Ebrish, Oleg Gluschenkov
  • Patent number: 9461169
    Abstract: A device and method for inducing stress in a semiconductor layer includes providing a substrate having a dielectric layer formed between a first semiconductor layer and a second semiconductor layer and processing the second semiconductor layer to form an amorphized material. A stress layer is deposited on the first semiconductor layer. The wafer is annealed to memorize stress in the second semiconductor layer by recrystallizing the amorphized material.
    Type: Grant
    Filed: May 28, 2010
    Date of Patent: October 4, 2016
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Kangguo Cheng, Bruce B. Doris, Ali Khakifirooz, Pranita Kulkarni, Ghavam G. Shahidi
  • Patent number: 9269830
    Abstract: A junction field effect transistor comprising: a semiconductor substrate having a first conductivity type; a channel region having a second conductivity type different from the first conductivity type, and being formed in a surface of the semiconductor substrate; a first buried region having the second conductivity type, being formed within the channel region, and having an impurity concentration higher than the channel region; a first gate region having the first conductivity type, and being formed in a surface of the channel region; and first drain/source region and a second drain/source region both having the second conductivity type, which are formed each on an opposite side of the first gate region in the surface of the channel region, in which the first buried region is not formed below the second drain/source region, but is formed below the first drain/source region.
    Type: Grant
    Filed: October 24, 2012
    Date of Patent: February 23, 2016
    Assignee: Panasonic Intellectual Property Management Co., Ltd.
    Inventors: Tomohiro Matsunaga, Tsuneichiro Sano
  • Patent number: 9013007
    Abstract: A depletion type MOS transistor includes a well region having a first conductivity type and formed on a semiconductor substrate, a gate insulating film formed on the well region, and a gate electrode formed on the gate insulating film. Source and drain regions having a second conductivity type different from the first conductivity type are formed on respective sides of the gate electrode and within the well region. A first low concentration impurity region has the second conductivity type and is formed below the gate insulating film between the source and drain regions and within the well region. A second low concentration impurity region has the first conductivity type and is formed below the first low concentration impurity region between the source and drain regions and within the well region.
    Type: Grant
    Filed: March 28, 2011
    Date of Patent: April 21, 2015
    Assignee: Seiko Instruments Inc.
    Inventor: Hirofumi Harada
  • Patent number: 8952455
    Abstract: In the case of using an analog buffer circuit, an input voltage is required to be added a voltage equal to a voltage between the gate and source of a polycrystalline silicon TFT; therefore, a power supply voltage is increased, thus a power consumption is increased with heat. In view of the foregoing problem, the invention provides a depletion mode polycrystalline silicon TFT as a polycrystalline silicon TFT used in an analog buffer circuit such as a source follower circuit. The depletion mode polycrystalline silicon TFT has a threshold voltage on its negative voltage side; therefore, an input voltage does not have to be increased as described above. As a result, a power supply voltage requires no increase, thus a low power consumption of a liquid crystal display device in particular can be realized.
    Type: Grant
    Filed: September 26, 2011
    Date of Patent: February 10, 2015
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Jun Koyama
  • Patent number: 8901538
    Abstract: A nano resonator includes a substrate, a first insulating layer disposed on the substrate, a first source disposed on the first insulating layer at a first position, a first drain disposed on the first insulating layer at a second position spaced apart from the first position so that the first drain faces the first source, a first nano-wire channel having a first end connected to the first source and a second end connected to the first drain, and having a doping type and a doping concentration that are identical to a doping type and a doping concentration of the first source and the first drain, and a second nano-wire channel disposed at a predetermined distance from the first nano-wire channel in a direction perpendicular to the substrate or a direction parallel to the substrate.
    Type: Grant
    Filed: March 18, 2013
    Date of Patent: December 2, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jie Ai Yu, Duck Hwan Kim, In Sang Song, Jing Cui
  • Patent number: 8809137
    Abstract: An improved HEMT formed from a GaN material system is disclosed which has reduced gate leakage current and eliminates the problem of current constrictions resulting from deposition of the gate metal over the step discontinuities formed over the gate mesa. One or more GaN based materials are layered and etched to form a gate mesa with step discontinuities defining source and drain regions. In order to reduce the leakage current, the step discontinuities are back-filled with an insulating material, such as silicon nitride (SiN), forming a flat surface relative to the source and drain regions, to enable to the gate metal to lay flat. By back-filling the source and drain regions with an insulating material, leakage currents between the gate and source and the gate and drain are greatly reduced. In addition, current constrictions resulting from the deposition of the gate metal over a step discontinuity are virtually eliminated.
    Type: Grant
    Filed: September 8, 2011
    Date of Patent: August 19, 2014
    Assignee: Northrop Grumman Systems Corporation
    Inventors: Rajinder Randy Sandhu, Michael Edward Barsky, Michael Wojtowicz
  • Patent number: 8803233
    Abstract: A transistor includes a semiconductor layer, and a gate dielectric is formed on the semiconductor layer. A gate conductor is formed on the gate dielectric and an active area is located in the semiconductor layer underneath the gate dielectric. The active area includes a graded dopant region that has a higher doping concentration near a top surface of the semiconductor layer and a lower doping concentration near a bottom surface of the semiconductor layer. This graded dopant region has a gradual decrease in the doping concentration. The transistor also includes source and drain regions that are adjacent to the active region. The source and drain regions and the active area have the same conductivity type.
    Type: Grant
    Filed: September 23, 2011
    Date of Patent: August 12, 2014
    Assignee: International Business Machines Corporation
    Inventors: Kangguo Cheng, Bruce B. Doris, Ali Khakifirooz, Pranita Kulkarni, Tak H. Ning
  • Patent number: 8716764
    Abstract: A semiconductor device and a manufacturing method thereof are provided. The fin semiconductor device includes a fin formed on a substrate and an insulating material layer formed on the substrate and surrounding the fin. The fin has a semiconductor layer that has a source region portion and a drain region portion. The fin includes a first channel control region, a second channel control region, and a channel region between the two channel control regions, all of which are positioned between the source region portion and the drain region portion. The two channel control regions may have the same conductivity type, different from the channel region.
    Type: Grant
    Filed: May 17, 2013
    Date of Patent: May 6, 2014
    Assignees: Semiconductor Manufacturing International (Shanghai) Corporation, Semiconductor Manufacturing International (Beijing) Corporation
    Inventor: Mieno Fumitake
  • Patent number: 8637939
    Abstract: A semiconductor device includes a channel layer formed over a substrate, a gate formed over the channel layer, junction regions formed on both sides of the channel layer to protrude from the substrate, and a buried barrier layer formed between the channel layer and the junction regions.
    Type: Grant
    Filed: June 28, 2010
    Date of Patent: January 28, 2014
    Assignee: Hynix Semiconductor Inc.
    Inventor: Kyung-Doo Kang
  • Patent number: 8633547
    Abstract: Structures for spanning gap in body-bias voltage routing structure. In an embodiment, a structure is comprised of at least one metal wire.
    Type: Grant
    Filed: June 16, 2008
    Date of Patent: January 21, 2014
    Inventors: Robert Masleid, James B. Burr, Michael Pelham
  • Patent number: 8569128
    Abstract: A semiconductor structure includes a first PMOS transistor element having a gate region with a first gate metal associated with a PMOS work function and a first NMOS transistor element having a gate region with a second metal associated with a NMOS work function. The first PMOS transistor element and the first NMOS transistor element form a first CMOS device. The semiconductor structure also includes a second PMOS transistor that is formed in part by concurrent deposition with the first NMOS transistor element of the second metal associated with a NMOS work function to form a second CMOS device with different operating characteristics than the first CMOS device.
    Type: Grant
    Filed: December 3, 2010
    Date of Patent: October 29, 2013
    Assignee: SuVolta, Inc.
    Inventors: Lucian Shifren, Pushkar Ranade, Sachin R. Sonkusale
  • Patent number: 8445968
    Abstract: A semiconductor device with improved transistor operating and flicker noise characteristics includes a substrate, an analog NMOS transistor and a compressively-strained-channel analog PMOS transistor disposed on the substrate. The device also includes a first etch stop liner (ESL) and a second ESL which respectively cover the NMOS transistor and the PMOS transistor. The relative measurement of flicker noise power of the NMOS and PMOS transistors to flicker noise power of reference unstrained-channel analog NMOS and PMOS transistors at a frequency of 500 Hz is less than 1.
    Type: Grant
    Filed: April 21, 2011
    Date of Patent: May 21, 2013
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Tetsuji Ueno, Hwa-sung Rhee, Ho Lee
  • Patent number: 8299546
    Abstract: A method of forming a semiconductor device is provided, in which extension regions are formed atop the substrate in a vertical orientation. In one embodiment, the method includes providing a semiconductor substrate doped with a first conductivity dopant. Raised extension regions are formed on first portions of the semiconductor substrate that are separated by a second portion of the semiconductor substrate. The raised extension regions have a first concentration of a second conductivity dopant. Raised source regions and raised drain regions are formed on the raised extension regions. The raised source regions and the raised drain regions each have a second concentration of the second conductivity dopant, wherein the second concentration is greater than the first concentration. A gate structure is formed on the second portion of the semiconductor substrate.
    Type: Grant
    Filed: March 25, 2010
    Date of Patent: October 30, 2012
    Assignee: International Business Machines Corporation
    Inventors: Zhibin Ren, Kevin K. Chan, Chung-Hsun Lin, Xinhui Wang
  • Patent number: 8093630
    Abstract: The invention provides a semiconductor device and a lateral diffused metal-oxide-semiconductor transistor. The semiconductor device includes a substrate having a first conductive type. A gate is disposed on the substrate. A source doped region is formed in the substrate, neighboring with a first side of the gate, wherein the source doped region has a second conductive type different from the first conductive type. A drain doped region is formed in the substrate, neighboring with a second side opposite to the first side of the gate. The drain doped region is constructed by a plurality of first doped regions with the first conductive type and a plurality of second doped regions with the second conductive type, wherein the first doped regions and the second doped regions are alternatively arranged.
    Type: Grant
    Filed: June 2, 2009
    Date of Patent: January 10, 2012
    Assignee: Vanguard International Semiconductor Corporation
    Inventors: Jimmy Lin, Shang-Hui Tu, Ming-Horng Hsiao
  • Patent number: 8093664
    Abstract: A peripheral circuit includes at least a first transistor. The first transistor comprises a gate electrode formed on a surface of a semiconductor layer via a gate insulating film. A channel region of a first conductivity type having a first impurity concentration is formed on a surface of the semiconductor layer directly below and in the vicinity of the gate electrode. A source-drain diffusion region of the first conductivity type is formed on the surface of the semiconductor layer to sandwich the gate electrode and has a second impurity concentration greater than the first impurity concentration. An overlapping region of the first conductivity type is formed on the surface of the semiconductor layer directly below the gate electrode where the channel region and the source-drain diffusion region overlap. The overlapping region has a third impurity concentration greater than the second impurity concentration.
    Type: Grant
    Filed: January 26, 2009
    Date of Patent: January 10, 2012
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Kenji Gomikawa, Mitsuhiro Noguchi
  • Patent number: 8068157
    Abstract: An image sensor includes a photoelectric converter, a source-follower transistor, and a selection transistor. The photoelectric converter generates electric charge in response to received light, and the electric charge varies a voltage of a detection node. The source-follower transistor is coupled between the detection node and an output node and has a first threshold voltage. The selection transistor is coupled between the source-follower transistor and a voltage node with a power supply voltage or a boosted voltage applied thereon, and has a second threshold voltage with a magnitude that is less than a magnitude of the first threshold voltage such that the source-follower transistor operates in saturation.
    Type: Grant
    Filed: July 14, 2008
    Date of Patent: November 29, 2011
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sang-Il Jung, Min-Young Jung
  • Publication number: 20110248358
    Abstract: A method of manufacturing a semiconductor device, wherein thermal annealing of the source/drain regions is performed before reverse Halo implantation to form a reverse Halo implantation region. The method comprises: removing the dummy gate to expose the gate dielectric layer, so as to form an opening; performing reverse Halo implantation on the substrate via the opening, so as to form a reverse Halo implantation region in the channel of the device; activating the dopants in the reverse Halo implantation region by annealing; and performing subsequent device processing. Deterioration of the gate stack due to the reverse Halo ions implantation may be avoided by the present invention, such that the reverse Halo ions implantation may be applied to the device with a metal gate stack, and the short channel effects may be alleviated and controlled, thereby the performance of the device is enhanced.
    Type: Application
    Filed: June 25, 2010
    Publication date: October 13, 2011
    Applicant: INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES
    Inventors: Haizhou Yin, Huilong Zhu, Zhijiong Luo
  • Patent number: 7973361
    Abstract: A high breakdown voltage semiconductor device is formed using an SOI substrate comprising a support substrate, an insulating film, and an active layer. The high breakdown voltage semiconductor device comprises an N-type well region and a P-type drain offset region formed on the active layer, a P-type source region formed on the well region, a P-type drain region formed on the drain offset region, a gate insulating film formed in at least a region interposed between the source region and the drain offset region of the active layer, and a gate electrode formed on the gate insulating film. The device further comprises an N-type deep well region formed under the drain offset region. A concentration peak of N-type impurity for formation of the deep well region is located deeper than a concentration peak of P-type impurity for formation of the drain offset region.
    Type: Grant
    Filed: February 27, 2006
    Date of Patent: July 5, 2011
    Assignee: Panasonic Corporation
    Inventors: Yoshinobu Sato, Hiroyoshi Ogura, Hisao Ichijo, Teruhisa Ikuta, Toru Terashita
  • Publication number: 20110140179
    Abstract: A semiconductor device includes: a rectifying element; an electrode pad electrically connected to the rectifying element; and a resistance and a depletion transistor arranged between the rectifying element and the electrode pad, and electrically connected to each other. The semiconductor device has a configuration in which the rectifying element, the resistance, the depletion transistor, and the electrode pad are serially connected. The semiconductor device is configured to generate a gate potential of the depletion transistor based on a difference in potential across the resistance and to produce a depletion layer in a channel of the depletion transistor based on the gate potential. As a result, a semiconductor device having reasonably large current at low voltage and small current at high voltage can be obtained.
    Type: Application
    Filed: October 11, 2010
    Publication date: June 16, 2011
    Applicant: MITSUBISHI ELECTRIC CORPORATION
    Inventors: Shigeru Kusunoki, Shinichi Ishizawa
  • Patent number: 7947555
    Abstract: In a method of making a silicon carbide semiconductor device having a MOSFET, after a mask is placed on a surface of a first conductivity type drift layer of silicon carbide, ion implantation is performed by using the mask to form a lower layer of a deep layer extending in one direction. A first conductivity type current scattering layer having a higher concentration than the drift layer is formed on the surface of the drift layer. After another mask is placed on a surface of the current scattering layer, ion implantation is performed by using the other mask to form an upper layer of the deep layer at a position corresponding to the lower layer in such a manner that the lower layer and the upper layer are connected together.
    Type: Grant
    Filed: April 9, 2009
    Date of Patent: May 24, 2011
    Assignee: Denso Corporation
    Inventors: Atsuya Akiba, Eiichi Okuno
  • Patent number: 7915107
    Abstract: This invention describes a method of building complementary logic circuits using junction field effect transistors in silicon. This invention is ideally suited for deep submicron dimensions, preferably below 65 nm. The basis of this invention is a complementary Junction Field Effect Transistor which is operated in the enhancement mode. The speed-power performance of the JFETs becomes comparable with the CMOS devices at sub-70 nanometer dimensions. However, the maximum power supply voltage for the JFETs is still limited to below the built-in potential (a diode drop). To satisfy certain applications which require interface to an external circuit driven to higher voltage levels, this invention includes the structures and methods to build CMOS devices on the same substrate as the JFET devices.
    Type: Grant
    Filed: June 26, 2009
    Date of Patent: March 29, 2011
    Assignee: SuVolta, Inc.
    Inventor: Ashok K. Kapoor
  • Patent number: 7687834
    Abstract: This invention describes a method of building complementary logic circuits using junction field effect transistors in silicon. This invention is ideally suited for deep submicron dimensions, preferably below 65 nm. The basis of this invention is a complementary Junction Field Effect Transistor which is operated in the enhancement mode. The speed-power performance of the JFETs becomes comparable with the CMOS devices at sub-70 nanometer dimensions. However, the maximum power supply voltage for the JFETs is still limited to below the built-in potential (a diode drop). To satisfy certain applications which require interface to an external circuit driven to higher voltage levels, this invention includes the structures and methods to build CMOS devices on the same substrate as the JFET devices.
    Type: Grant
    Filed: November 3, 2008
    Date of Patent: March 30, 2010
    Assignee: SuVolta, Inc.
    Inventor: Ashok K. Kapoor
  • Patent number: 7655990
    Abstract: The present invention proposes a voltage-clipping device utilizing a pinch-off mechanism formed by two depletion boundaries. A clipping voltage of the voltage-clipping device can be adjusted in response to a gate voltage; a gap of a quasi-linked well; and a doping concentration and a depth of the quasi-linked well and a well with complementary doping polarity to the quasi-linked well. The voltage-clipping device can be integrated within a semiconductor device as a voltage stepping down device in a tiny size, compared to traditional transformers.
    Type: Grant
    Filed: June 15, 2006
    Date of Patent: February 2, 2010
    Assignee: System General Corp.
    Inventors: Chiu-Chih Chiang, Chih-Feng Huang, You-Kuo Wu, Long Shih Lin
  • Publication number: 20090315123
    Abstract: A high voltage device with constant current source and the manufacturing method thereof. The device includes a P type silicon substrate (1), an oxide layer (6), a drain metal (2), a source metal (3), a gate metal (4), a P+substrate contact region (51), a N+drain region (52), an N+source region (53), an N?channel region (54) connecting the said N+drain region (52) and N+source region (53), and an N?drain region (92) enveloping the said N+drain region (52); the drain metal (2) fills drain through hole (82) and connects the N+drain region (52); the source metal (3) fills source through hole (83), and connects the N+source region (53) and P+substrate contact region (51); the source metal (3) and gate metal (4) are electrically connected by connecting metal (34). The manufacturing method includes steps of forming N+drain region, N+source region, N?drain region, P+substrate contact region, N?drain region and metal layer.
    Type: Application
    Filed: June 24, 2009
    Publication date: December 24, 2009
    Applicant: Nanker(Guang Zhou)Semiconductor Manufacturing Crop.
    Inventor: Wei-Kuo WU
  • Patent number: 7619288
    Abstract: A method for manufacturing a thin film transistor substrate includes a step of forming a plurality of island-like semiconductor films above an insulating transparent substrate; a step of forming a gate insulating film on each of the island-like semiconductor films; a step of forming first conductivity type LDD regions on both sides in the first island-like semiconductor film by leaving a channel region and forming a first conductivity type normally-on channel region having an impurity density equivalent to that of the LDD region in the second island-like semiconductor film; a step of forming a first gate electrode partially covering the LDD region and forming a second gate electrode above the normally-on channel region, and a step of forming a first conductivity type source/drain region having an impurity density higher than that of the LDD region in regions on the both sides of the gate electrode.
    Type: Grant
    Filed: May 16, 2006
    Date of Patent: November 17, 2009
    Assignee: Sharp Kabushiki Kaisha
    Inventor: Kazushige Hotta
  • Publication number: 20090134476
    Abstract: An accumulation mode field effect transistor includes a substrate, an insulated gate on the substrate, source and drain regions on the substrate on opposite sides of the insulated gate, a channel region that is doped a first conductivity type at a first doping concentration, and that extends into the substrate beneath the insulated gate to a channel region depth, and a counter-doped region (for example, a portion of the substrate, a tub in the substrate or a well in the substrate) beneath the channel region that is doped a second conductivity type at a second doping concentration to define a semiconductor junction therebetween at the channel region depth.
    Type: Application
    Filed: November 11, 2008
    Publication date: May 28, 2009
    Inventor: William R. Richards, JR.
  • Publication number: 20090114999
    Abstract: According to some embodiments of the invention, transistors of a semiconductor device have a channel region in a channel-portion hole. Methods include forming embodiments of the transistor having a channel-portion hole disposed in a semiconductor substrate. A channel-portion trench pad and a channel-portion layer are sequentially formed at a lower portion of the channel-portion hole. A word line insulating layer pattern and a word line pattern are sequentially stacked on the channel-portion layer and fill the channel-portion hole, disposed on the semiconductor substrate. The channel-portion layer is formed to contact the semiconductor substrate through a portion of sidewall of the channel-portion hole, and forms a channel region under the word line pattern. Punchthrough is prevented between electrode impurity regions corresponding to source and drain regions.
    Type: Application
    Filed: January 8, 2009
    Publication date: May 7, 2009
    Applicant: Samsung Electroncs Co., Ltd.
    Inventors: Hyeoung-Won SEO, Du-Heon SONG, Sang-Hyun LEE
  • Patent number: 7453281
    Abstract: An anti-counterfeiting circuit that is incorporated into an authentic integrated circuit (IC) design, which induces a random failure in a counterfeited IC when the counterfeit IC is manufactured from a reverse-engineered authentic IC. The anti-counterfeiting circuit uses two signals of differing frequencies, which activate a disrupt signal when the two signals meet a predetermined failure criteria, for example, equivalent rising edges. The disrupt signal causes a signal gate or similar element within the counterfeited IC to fail, disrupt, or in some way change a designed behavior of the IC. The disrupt signal may be reset so that the failure will occur again when predetermined failure criteria are met. The authentic IC functions according to design because at least one of the elements in the anti-counterfeit circuit is a camouflage circuit, thus, in an authentic IC the anti-counterfeit circuit is not operatively coupled.
    Type: Grant
    Filed: January 11, 2007
    Date of Patent: November 18, 2008
    Assignee: International Business Machines Corporation
    Inventors: Brent Alan Anderson, Edward Joseph Nowak
  • Patent number: 7442971
    Abstract: By providing a self-biasing semiconductor switch, an SRAM cell having a reduced number of individual active components may be realized. In particular embodiments, the self-biasing semiconductor device may be provided in the form of a double channel field effect transistor that allows the formation of an SRAM cell with less than six transistor elements and, in preferred embodiments, with as few as two individual transistor elements.
    Type: Grant
    Filed: January 28, 2005
    Date of Patent: October 28, 2008
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Frank Wirbeleit, Manfred Horstmann, Christian Hobert
  • Patent number: 7432565
    Abstract: A III-V based, implant free MOS heterostructure field-effect transistor device comprises a gate insulator layer overlying a compound semiconductor substrate; ohmic contacts coupled to the compound semiconductor substrate proximate opposite sides of an active device region defined within the compound semiconductor substrate; and a gate metal contact electrode formed on the gate insulator layer in a region between the ohmic contacts. The ohmic contacts have portions thereof that overlap with portions of the gate insulator layer within the active device region. The overlapping portions ensure avoidance of an undesirable gap formation between an edge of the ohmic contact and a corresponding edge of the gate insulator layer.
    Type: Grant
    Filed: September 27, 2005
    Date of Patent: October 7, 2008
    Assignee: Freescale Semiconductor, Inc.
    Inventor: Matthias Passlack
  • Patent number: 7417277
    Abstract: Conventional capacitors constituted of a FET incur degradation in frequency response. A semiconductor integrated circuit includes a semiconductor substrate, an N-type FET, a P-type FET, and capacitors. The N-type FET includes N-type impurity diffusion layers, a P-type impurity-implanted region, a gate insulating layer, and a gate electrode. The P-type FET includes P-type impurity diffusion layers, an N-type impurity-implanted region, a gate insulating layer, and a gate electrode. The capacitor includes N-type impurity diffusion layers, an N-type impurity-implanted region, a capacitance insulating layer, and an upper electrode. The capacitor includes P-type impurity diffusion layers, a P-type impurity-implanted region, a capacitance insulating layer, and an upper electrode.
    Type: Grant
    Filed: December 1, 2006
    Date of Patent: August 26, 2008
    Assignee: NEC Electronics Corporation
    Inventors: Hiroaki Ohkubo, Yasutaka Nakashiba
  • Patent number: 7388260
    Abstract: Structures for spanning gap in body-bias voltage routing structure. In an embodiment, a structure is comprised of at least one metal wire.
    Type: Grant
    Filed: March 31, 2004
    Date of Patent: June 17, 2008
    Assignee: Transmeta Corporation
    Inventors: Robert P. Masleid, James B. Burr, Michael Pelham
  • Patent number: 7385263
    Abstract: The present invention is related to a metal-oxide semiconductor field-effect transistor (MOSFET) having a symmetrical layout such that the resistance between drains and sources is reduced, thereby reducing power dissipation. Drain pads, source pads, and gates are placed on the MOSFET such that the distances between drains, sources, and gates are optimized to reduce resistance and power dissipation. The gates may be arranged in a trapezoidal arrangement in order to maximize a ratio of the gate widths to gate lengths for current driving while reducing resistance and power dissipation.
    Type: Grant
    Filed: May 2, 2006
    Date of Patent: June 10, 2008
    Assignee: Atmel Corporation
    Inventors: Maud Pierrel, Bilal Manai
  • Patent number: 7361947
    Abstract: A photoelectric conversion element includes a semiconductor layer including a pair of p+ regions in which p-type impurities are doped, and a p? region which is disposed between the p+ regions and has a lower p-type impurity concentration than the p+ regions. A gate electrode is formed over the p? region via a gate insulation film, thus, a p-MOS structure is formed. A width of the gate electrode is less than a width of the p? region. A p? region, which is a portion of the p? region and is located immediately below the gate electrode, forms a light receiving layer, and p? regions, which are portions of the p? region and are located away from below the gate electrode, form LDD regions. The photoelectric conversion element is fabricated on the same substrate as a thin-film transistor for a driving circuit, thereby constructing a display device with an input function.
    Type: Grant
    Filed: December 27, 2005
    Date of Patent: April 22, 2008
    Assignee: Toshiba Matsushita Display Technology Co., Ltd.
    Inventor: Norio Tada
  • Patent number: 7326977
    Abstract: An FET (field effect transistor) having source, drain and channel regions of a conductivity type in a semiconductor body of opposite conductivity type. The channel region is located at the lower extremity of the source and drain regions so as to be spaced from the surface of the semiconductor body by a distance d.
    Type: Grant
    Filed: October 3, 2005
    Date of Patent: February 5, 2008
    Assignee: Northrop Grumman Corporation
    Inventors: Nathan Bluzer, Donald R. Lampe
  • Patent number: 7288817
    Abstract: The present invention teaches a method of forming a MOSFET transistor having a silicide gate which is not subject to problems produced by etching a metal containing layer when forming the gate stack structure. A gate stack is formed over a semiconductor substrate comprising a gate oxide layer, a conducting layer, and a first insulating layer. Sidewall spacers are formed adjacent to the sides of the gate stack structure and a third insulating layer is formed over the gate stack and substrate. The third insulating layer and first insulating layer are removed to expose the conducting layer and, at least one unetched metal-containing layer is formed over and in contact with the conducting layer. The gate stack structure then undergoes a siliciding process with different variations to finally form a silicide gate.
    Type: Grant
    Filed: January 12, 2005
    Date of Patent: October 30, 2007
    Assignee: Micron Technology, Inc.
    Inventors: Werner Juengling, Richard H. Lane
  • Patent number: 7282768
    Abstract: A high-reliable depletion-type MOS field-effect transistor as a process monitor is provided. A diode formed in polycrystalline silicon and a diode formed in a semiconductor substrate form a bi-directional diode. The bi-directional diode connects a gate electrode with the semiconductor substrate in the depletion-type MOS field-effect transistor through metal wirings.
    Type: Grant
    Filed: July 1, 2005
    Date of Patent: October 16, 2007
    Assignee: Seiko Instruments Inc.
    Inventor: Hirofumi Harada
  • Patent number: 7274056
    Abstract: The invention includes a semiconductor construction having a pair of channel regions that have sub-regions doped with indium and surrounded by boron. A pair of transistor constructions are located over the channel regions and are separated by an isolation region. The transistors have gates that are wider than the underlying sub-regions. The invention also includes a semiconductor construction that has transistor constructions with insulative spacers along gate sidewalls. Each transistor construction is between a pair source/drain regions that extend beneath the spacers. A source/drain extension extends the source/drain region farther beneath the transistor constructions on only one side of each of the transistor constructions. The invention also includes methods of forming semiconductor constructions.
    Type: Grant
    Filed: August 24, 2005
    Date of Patent: September 25, 2007
    Assignee: Micron Technology, Inc.
    Inventor: Luan C. Tran
  • Patent number: 7274076
    Abstract: A threshold voltage adjusted long-channel transistor fabricated according to short-channel transistor processes is described. The threshold-adjusted transistor includes a substrate with spaced-apart source and drain regions formed in the substrate and a channel region defined between the source and drain regions. A layer of gate oxide is formed over at least a part of the channel region with a gate formed over the gate oxide. The gate further includes at least one implant aperture formed therein with the channel region of the substrate further including an implanted region within the channel between the source and drain regions. Methods for forming the threshold voltage adjusted transistor are also disclosed.
    Type: Grant
    Filed: October 20, 2003
    Date of Patent: September 25, 2007
    Assignee: Micron Technology, Inc.
    Inventor: Ethan Williford
  • Patent number: 7271457
    Abstract: A Fermi threshold voltage FET has Germanium implanted to form a shallow abrupt transition between the semiconductor substrate dopant type, or well dopant type, and a counter doping layer of opposite type closely adjacent the surface of the semiconductor substrate. Germanium is a charge neutral impurity in silicon that significantly reduces the diffusion motion of other impurity dopants, such as As, P, In, and B in the regions of silicon where Ge resides in significant quantities (i.e. greater than 1E19 cm sup3).
    Type: Grant
    Filed: March 4, 2005
    Date of Patent: September 18, 2007
    Assignee: BAE Systems Information and Electronic Systems Integration Inc.
    Inventor: Robert M. Quinn
  • Patent number: 7227227
    Abstract: The invention includes a semiconductor construction having a pair of channel regions that have sub-regions doped with indium and surrounded by boron. A pair of transistor constructions are located over the channel regions and are separated by an isolation region. The transistors have gates that are wider than the underlying sub-regions. The invention also includes a semiconductor construction that has transistor constructions with insulative spacers along-gate sidewalls. Each transistor construction is between a pair source/drain regions that extend beneath the spacers. A source/drain extension extends the source/drain region farther beneath the transistor constructions on only one side of each of the transistor constructions. The invention also includes methods of forming semiconductor constructions.
    Type: Grant
    Filed: August 24, 2005
    Date of Patent: June 5, 2007
    Assignee: Micron Technology, Inc.
    Inventor: Luan C. Tran
  • Patent number: 7176530
    Abstract: A semiconductor technology combines a normally off n-channel channel-junction insulated-gate field-effect transistor (“IGFET”) (104) and an n-channel surface-channel IGFET (100 or 160) to reduce low-frequency 1/f noise. The channel-junction IGFET is normally of materially greater gate dielectric thickness than the surface-channel IGFET so as to operate across a greater voltage range than the surface-channel IGFET. Alternatively or additionally, the channel-junction IGFET may conduct current through a field-induced surface channel. A p-channel surface-channel IGFET (102 or 162), which is typically of approximately the same gate-dielectric thickness as the n-channel surface-channel IGFET, is preferably combined with the two n-channel IGFETs to produce a complementary-IGFET structure. A further p-channel IGFET (106, 180, 184, or 192), which is typically of approximately the same gate dielectric thickness as the n-channel channel-junction IGFET, is also preferably included.
    Type: Grant
    Filed: March 17, 2004
    Date of Patent: February 13, 2007
    Assignee: National Semiconductor Corporation
    Inventors: Constantin Bulucea, Philipp Lindorfer
  • Patent number: 7129544
    Abstract: In one embodiment, a compound semiconductor vertical FET device (11) includes a first trench (29) formed in a body of semiconductor material (13), and a second trench (34) formed within the first trench (29) to define a channel region (61). A doped gate region (59) is then formed on the sidewalls and the bottom surface of the second trench (34). Source regions (26) are formed on opposite sides of the double trench structure (28). Localized gate contact regions (79) couple individual doped gate regions (59) together. Contacts (84,85,87) are then formed to the localized gate contact regions (79), the source regions (26), and an opposing surface (21) of the body of semiconductor material (13). The structure provides a compound semiconductor vertical FET device (11, 41, 711, 712, 811, 812) having enhanced blocking capability and improved switching performance.
    Type: Grant
    Filed: October 6, 2004
    Date of Patent: October 31, 2006
    Assignee: Semiconductor Components Industries, L.L.C.
    Inventor: Peyman Hadizad
  • Patent number: 7098512
    Abstract: Layout patterns for the deep well region to facilitate routing the body-bias voltage in a semiconductor device are provided and described. The layout patterns include a diagonal sub-surface mesh structure, an axial sub-surface mesh structure, a diagonal sub-surface strip structure, and an axial sub-surface strip structure. A particular layout pattern is selected for an area of the semiconductor device according to several factors.
    Type: Grant
    Filed: October 10, 2003
    Date of Patent: August 29, 2006
    Assignee: Transmeta Corporation
    Inventors: Mike Pelham, James B. Burr
  • Patent number: 7081646
    Abstract: There are disclosed TFTs that have excellent characteristics and can be fabricated with a high yield. The TFTs are fabricated, using an active layer crystallized by making use of nickel. Gate electrodes are comprising tantalum. Phosphorus is introduced into source/drain regions. Then, a heat treatment is performed to getter nickel element in the active layer and to drive it into the source/drain regions. At the same time, the source/drain regions can be annealed out. The gate electrodes of tantalum can withstand this heat treatment.
    Type: Grant
    Filed: August 28, 2001
    Date of Patent: July 25, 2006
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Shunpei Yamazaki
  • Patent number: 7071518
    Abstract: A regular Schottky diode or a device that has a Schottky diode characteristic and an MOS transistor are coupled in series to provide a significant improvement in leakage current and breakdown voltage with only a small degradation in forward current. In the reverse bias case, there is a small reverse bias current but the voltage across the Schottky diode remains small due the MOS transistor. Nearly all of the reverse bias voltage is across the MOS transistor until the MOS transistor breaks down. This transistor breakdown, however, is not initially destructive because the Schottky diode limits the current. As the reverse bias voltage continues to increase the Schottky diodes begins to absorb more of the voltage. This increases the leakage current but the breakdown voltage is a somewhat additive between the transistor and the Schottky diode.
    Type: Grant
    Filed: May 28, 2004
    Date of Patent: July 4, 2006
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Vijay Parthasarathy, Vishnu K. Khemka, Ronghua Zhu, Amitava Bose
  • Patent number: 7049656
    Abstract: A semiconductor configuration includes a semiconductor body with a first connection zone of a first conductivity type, a second connection zone of the first conductivity type, a channel zone of the first conductivity type, and at least one control electrode surrounded by an insulation layer. The channel zone is formed between the first connection zone and the second connection zone. The at least one control electrode extends, adjacent to the channel zone, from the first connection zone to the second connection zone. The first connection zone, the second connection zone and the at least one control electrode extend in the vertical direction such that, when a voltage is applied between the first and second connection zones, a current path along the lateral direction is formed in the channel zone.
    Type: Grant
    Filed: May 30, 2003
    Date of Patent: May 23, 2006
    Assignee: Infineon Technologies AG
    Inventor: Jenoe Tihanyi
  • Patent number: 7023060
    Abstract: A method for programming a read-only memory cell including a transistor whose source and drain, which have a second type of doping, are formed in a semiconductor substrate with a first type of doping, includes a step of carrying out a contradoping in a region of the source, the region being adjacent to the conduction channel 4, to make it a region with the first type of doping so as to prevent a transistor effect from occurring.
    Type: Grant
    Filed: January 4, 1999
    Date of Patent: April 4, 2006
    Assignee: SGS-Thomson Microelectronics S.A.
    Inventor: Richard Pierre Fournel
  • Patent number: 7019379
    Abstract: A semiconductor device includes a heavily doped layer 25 of p-type formed in the surface of an n-type well 21, an intermediately doped layer 26 of p-type formed to adjoin and surround the heavily p-doped layer 25, and an isolation region 22 formed to surround the heavily p-doped layer 25 and the intermediately p-doped layer 26. The heavily p-doped layer 25 has a higher dopant concentration than the well 21. The intermediately p-doped layer 26 has a higher dopant concentration than the well 21 and a lower dopant concentration than the heavily p-doped layer 25.
    Type: Grant
    Filed: November 12, 2003
    Date of Patent: March 28, 2006
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventor: Hirotsugu Honda