Abstract: There is provided a semiconductor device having a novel structure in which high reliability and high field effect mobility can be simultaneously achieved. In an insulated gate transistor formed on a single crystal silicon substrate, pinning regions 105 and 106 are formed at the ends of a channel formation region 102. The pinning regions 105 and 106 suppress the expansion of a depletion layer from the drain side to prevent a short channel effect. In addition, they also serve as a path for extracting minority carriers generated as a result of impact ionization to prevent breakdown phenomena induced by carrier implantation.

Abstract: The present invention provides novel structures of MOS field effect transistor which operate with high speed and low power consumption. This has been achieved through providing epitaxial growth layers on a substrate of high impurity doping concentration in which the thickness of epitaxial growth layers is controlled with a degree of accuracy on the order of a single atom layer.

Abstract: In a semiconductor device including high-voltage, middle-voltage, and low voltage transistors having operating voltages different from one another, a gate length and a thickness of a gate oxide film are increased as the operating voltage is increased. Accordingly, in the high-voltage transistor, an electric field produced at a channel is relaxed. In the low-voltage transistor, a structure is made finer. A concentration of a well and an impurity amount implanted into a surface portion of a substrate are set to be identical with each other in all the transistors. Accordingly, the semiconductor device can be speedily manufactured at a high yield.

Abstract: A semiconductor device and fabrication method thereof are provided, which include an opposite-polarity region formed in a predetermined location under a gate channel region, having a conductive property opposite to that of a surrounding well region. The gate voltage is controlled so that a second depleted layer region is induced concurrently with the opposite-polarity region by the applied gate voltage and can be coupled with a first depleted region which is formed under the channel region and is controllable by the applied gate voltage. In this structure of the semiconductor device, drain current of the device is rendered more responsive to the applied gate voltage, and leakage currents at a certain applied drain voltage and at zero gate voltage are reduced, thereby reducing the standby currents of the semiconductor device.

Abstract: An isolation structure is provided that includes a substrate (10), a refill material such as a refill oxide (22), a gate dielectric such as a gate oxide layer (24), and a gate conductor layer such a polysilicon gate layer (26). The substrate (10) has an active region (12), an active region (14), and a trench region provided between the active region (12) and the active region (14). The active region (14) includes a top corner (32) that is provided where an upper surface of the active region (14) and the trench wall of the trench region that is adjacent to the active region (14) meet. The refill oxide (22) is positioned within the trench region and extends to cover at least a portion of the top corner. The gate oxide layer (24) is provided on the upper surface of the active region (14). The polysilicon gate layer (26) is provided on an upper surface of the gate oxide layer (24).

Abstract: The invention is directed to reducing incidental capacitance associated with a MOS transistor, especially such a transistor as used with a solid-state image-pickup device, without reducing the channel conductance of the MOS transistor. To such end, N.sup.+ -type high-concentration fields are formed near the surface of a P-type well field that in a semiconductor substrate. An N-type low-concentration field is formed between and surrounding the N.sup.+ -type high-concentration fields. A depletion layer is formed by making PN junctions between N.sup.+ -type high-concentration fields and the well field in a reverse-bias state to deplete the perimeter of the N.sup.+ -type high-concentration fields and the entire N-type low-concentration field.

Abstract: A static self-locking micro-circuit-breaker includes a first MOS depletion transistor of a first type connected by its drain to a first main terminal and by its gate to a second main terminal, a second MOS depletion transistor of second type connected by its drain to the second main terminal and by its source to the source of the first transistor, a third MOS depletion transistor of the first type connected by its drain to the first main terminal, by its gate to the second main terminal, and by its source to the gate of the second transistor.

Abstract: An active FET body device which comprises an active FET region including a gate, a body region and electrical connection between said gate and said body region that is located within the active FET region is provided along with various methods for fabricating the devices. The electrical connection extends over substantially the entire width of the FET.

Abstract: Transistors have source, drain and channel regions all of the same conductivity type. The channel region is very thin, not more than about 500 .ANG. and preferably about 300 .ANG. or even 100 .ANG. in thickness. A very thin oxide layer having a thickness of much less than about 100 .ANG., such as 20 .ANG. and preferably about 5 to about 10 .ANG., isolates a gate electrode from the channel region. When operated at temperatures at or below 150.degree. K, such as 77.degree. K, very low threshold voltages, well below 25 millivolts, are achieved. Gigahertz speed complementary MOS transistors, formed by adjacent NNN and PPP devices exhibit power-delay products of about 1E-16 joules operating at supply voltages on order 100 millivolts or lower, making this technology of particular interest for multi-gigahertz processing rates at very low power.

Abstract: An n-semiconductor layer is arranged on a low-resistance n-substrate. A drain electrode is in ohmic contact with the n-substrate. A source electrode forms a Schottky junction with the n-semiconductor layer. A gate electrode is arranged adjacent to the source electrode on the n-semiconductor layer through a gate insulating film. When a voltage is applied to the gate electrode to lower the Schottky barrier height at the interface between the source electrode and the n-semiconductor layer, electrons are injected from the source electrode into the n-semiconductor layer, and a current flows in the semiconductor device. A diffusion layer which prevents a decrease in manufacturing time is not required to form in the n-semiconductor layer, and a channel which causes an increase in ON state voltage is not present.

Abstract: A pair of complementary CJIGFETs (100 and 160) are created from a body of semiconductor material (102 and 104). Each CJIGFET is formed with (a) a pair of laterally separated source/drain zones (112 and 114 or 172 and 174) situated along the upper surface of the semiconductor body, (b) a channel region (110 or 170) extending between the source/drain zones, and (c) a gate electrode (118 or 178) overlying, and electrically insulated from, the channel region. The gate electrode of each CJIGFET has a Fermi energy level within 0.3 ev of the middle of the energy band gap of the semiconductor material. One of the transistors typically conducts current according to a field-induced-channel mode while the other transistor conducts current according to a metallurgical-channel mode. The magnitude of the threshold voltage for each CJIGFET is normally no more than 0.5 V.

Abstract: A high-breakdown-voltage semiconductor device has a first offset layer and a second offset layer the dosage of which is higher than that of the first offset layer. When the gate is in the ON state, the first offset layer functions as a resurf layer. When the gate is in the OFF state, part of the charge in the first offset layer is neutralized by a drain current flowing through an element having a low ON-resistance, however, the second offset layer functions as a resurf layer. When the drain current is ?Acm.sup.-1 !, the amount of charge of electrons is q?C!, and the drift speed of carriers is .upsilon..sub.drift ?cms.sup.-1 !, the dosage n.sub.2 of the second offset layer is given by n.sub.2 .gtoreq.I.sub.D /(q.upsilon..sub.drift)?cms.sup.-2 !.

Abstract: A pair of complementary MOSFET's having regions of a common conductivity type separating the source and drain regions thereof which are provided on a support structure formed of an electrical insulating layer on a semiconductor material base. MOSFET's has a gate oxide layer on which is provided a gate semiconductor structure, with these structures each being of a common conductivity type and located across the gate oxide layers from the corresponding common conductivity type region.

Abstract: A field controlled semiconductor device of SiC comprises superimposed in the order mentioned at least a drain (12), a highly doped substrate layer (1) and a low doped n-type drift layer (2). It has also a highly doped n-type source region layer (6) and a source (11) connected thereto. A doped channel region layer (4) connects the source region layer to the drift layer, and a current is intended to flow therethrough when the device is in an on-state. The device has also a gate electrode (9). The channel region layer has a substantially lateral extension and is formed by a low doped n-type layer (4). The gate electrode (9) is arranged to influence the channel region layer from above for giving a conducting channel (17) created therein from the source region layer to the drift layer a substantially lateral extension.

Abstract: A depletion type transistor formed on a semiconductor substrate includes a drain region and a source region formed in distinct areas on the substrate. An inversion layer is formed in the surface area between the drain and the source regions. The transistor further includes two insulated gates: a floating gate located above the substrate and insulated from the inversion layer by an insulating layer in such a way as to cover the inversion layer, and a control gate provided above the floating gate and insulated from the floating gate by the insulating layer.

Abstract: An accumulation-mode power MOSFET includes a trenched gate that is formed in a semiconductor material of a first conductivity type. A region of second conductivity type is formed in the substrate (which may include an epitaxial layer) and a PN junction formed by the region of second conductivity type is connected in parallel with the current path through the accumulation-mode MOSFET. The diode is designed to have a breakdown voltage was causes the diode to break down before the oxide layer surrounding the gate can be ruptured or otherwise damaged when the MOSFET is in an off condition.

Abstract: A Fermi-threshold field effect transistor includes spaced-apart source and drain regions which extend beyond the Fermi-tub in the depth direction and which may also extend beyond the Fermi-tub in the lateral direction. In order to compensate for the junction with the substrate, the doping density of the substrate region is raised to counteract the shared charge. Furthermore, the proximity of the source and drain regions leads to a potential leakage due to the drain field which can be compensated for by reducing the maximum tub depth compared to a low capacitance Fermi-FET and a contoured-tub Fermi-FET while still satisfying the Fermi-FET criteria. The tub depth is maintained below a maximum tub depth. Short channel effects may also be reduced by providing source and drain extension regions in the substrate, adjacent the source and drain regions and extending towards the channel regions.

Abstract: A depletion mode power MOSFET has a gate electrode formed of material that is refractory, or resistant, to high temperature encountered during device fabrication. A depletion channel region which is formed in a base region of a MOSFET and which interconnects the source and drain regions is formed after a high temperature drive to form the base region, but before a gate oxide and gate and source electrodes are formed at lower temperatures. The depletion channel region is thus subjected to reduced temperatures and grows only slightly in thickness, so that it can be easily depleted. The gate oxide, similarly, is subjected to reduced temperatures, and, particularly when made thin, exhibits high insensitivity to radiation exposure.

Abstract: A Fermi-FET, including but not limited to a tub-FET, a contoured-tub Fermi-FET or a short channel Fermi-FET includes a drain extension region of the same conductivity type as the drain region and a drain pocket implant region of opposite conductivity type from the drain region. The drain pocket implant region acts as a drain field stop to reduce or prevent drain-to-source field reach-through. Reduced low drain field threshold voltage, significantly reduced drain induced barrier lowering and reduced threshold dependence on channel length may be obtained, resulting in higher performance in short channels.

Abstract: An integrated digital circuit is protected from reverse engineering by fabricating all transistors of like conductivity with a common size and geometric layout, providing a common layout for different logic cells, connecting doped circuit elements of like conductivity with electrically conductive doped implants in the substrate rather than metalized interconnections, and providing non-functional apparent interconnections that are interrupted by non-discernable channel stops so that all cells falsely appear to have a common interconnection scheme. The camouflage is enhanced by providing a uniform pattern of metal leads over the transistor array, with a uniform pattern of heavily doped implant taps from the transistors for connection to the leads; undesired tap-lead connections are blocked by channel stops.

Abstract: A germanium-based field effect transistor has a passivation layer of aluminum oxide below a germanium channel and aluminum oxide gate oxide layer formed over the channel. The aluminum oxide layers are treated to reduce the density of surface state impurities, particularly arsenic released in the oxide layer as a result of forming the oxide layer. The low surface state germanium channel has very low phase noise and is suitable for use as a local oscillator in a heterodyne receiver.

Abstract: Sub-micron PMOSFETs including n.sup.+ polysilicon gates and buried channels having impurity concentrations comprising indium or gallium are provided. The buried channel PMOSFETs have improved short channel characteristics and are particularly suitable for use in CMOS technologies.

Abstract: A method of forming a high density cell in electrically erasable and programmable read only memory (EEPROM) is disclosed. The doubling efficiency is achieved through providing two floating gates in a single cell, unlike what is found in prior art. While the polysilicon control gate is formed by conventional means, the floating gates are formed through a novel method of forming additional polysilicon spacers which are then coupled with lightly doped drain (LDD) regions to function as floating gates. Furthermore, the cell is turned on and off through the modulation of the LDD resistance and not through charge saturation methods of prior art. Finally, it is shown that through the use of two floating gates, rather than one, two bits of information can be stored in one cell with the concomitant advantage of doubled efficiency.

Abstract: An adjustable threshold voltage MOS device having an asymmetric pocket region is disclosed herein. The pocket region abuts one of a source or drain proximate the device's channel region. The pocket region has the same conductivity type as the device's bulk (albeit at a higher dopant concentration) and, of course, the opposite conductivity type as the device's source and drain. An MOS device having such pocket region may have its threshold voltage adjusted by applying a potential directly to its pocket region. This capability is realized by providing a contact or conductive tie electrically coupled to the pocket region. This "pocket tie" is also electrically coupled to a metallization line (external to the device) which can be held at a specified potential corresponding to a potential required to back-bias the device by a specified amount.

Abstract: A current limiter (15) is formed between a silicon substrate (10) and a source region (17) by a channel implant region (20). The channel implant region (20) is not modulated by a gate structure so the maximum voltage that can flow between the silicon substrate (10) and the source region (17) is determined by the doping profile of the ever-present channel implant region (20). A pinch-off structure (12) is used to form a depletion region which can support a large voltage potential between the silicon substrate (10) and the source region (17). In an alternate embodiment, a bipolar device is formed such that a limited current flow can be directed into a base region (32) which is used to modulate a current flow between silicon substrate (30) and an emitter region (38). Using the current limiters (15,35) it is possible to form an AC current limiter (50) that will limit the current flow regardless of the polarity of the voltage placed across two terminals (51,52).

Abstract: In a NAND type non-volatile memory device, an ion-implanting region is formed only in the source/drain region (or only in the drain region) of a depletion-type transistor for string selection, so that its junction depth is greater than that of the other transistors, to thereby improve the current-driving capability of each memory element.

Abstract: In fabricating a buried p-channel MOS transistor using an n-type substrate, a shallow n-type diffused layer is formed by ion implantation in each of intended source and drain regions so as to become oppositely adjacent to the shallow p-type diffused layer under the gate electrode. Then p-type diffused layers to serve as source and drain are formed by ion implantation through the n-type diffused layers, and the implanted impurities are activated. In consequence, impurity concentration at the substrate surface becomes lower in the section right under each end of the gate electrode than in the gate middle section. This measure brings about suppression of the short channel effect inherent to conventional buried-channel MOS transistors and makes it possible to shorten the physical gate length.

Abstract: A CMOS integrated circuit, in which the PMOS devices each include a buried channel region (26). The P+ source/drain regions (54) and (56) are separated from the channel region (26) by N-type lateral field isolating regions (58) and (60). Whenever a voltage negative enough to turn on the channel is applied, the isolating regions will be inverted by the electric fields from the comers of the gate. Thus, the value of the transistor's threshold voltage is not changed. However, these lateral field isolating regions provide an electric field modification which helps to minimize drain-induced barrier lowering, and thereby reduces the leakage current of the device in the off state. Preferably the lateral field isolating regions are formed by a doping which is maximal at the same depth (below the gate oxide) at which the threshold-voltage-adjust doping of the channel is maximal. The preferred CMOS process provides lateral field isolating regions on the PMOS devices, and also provides LDD regions on the NMOS devices.

Abstract: A MIS device comprising a pair of first doped layers of a second conductivity type forming source/drain regions in a semiconductor base structure of a first conductivity type, and a gate electrode formed in a region between the first doped layers of the second conductivity type on a gate insulating film formed on the semiconductor base structure having a three-layer structure consisting of a second doped layer of the first conductivity type, a third doped layer of the second conductivity type and a fourth doped layer of the first conductivity type having an impurity concentration higher than that of the semiconductor base structure, which are formed in that order in the direction of depth from the surface of a channel region extending between the source/drain regions, the thickness of the third doped layer is determined so that the third doped layer is depleted by the respective built-in potentials of pn junctions formed by the second doped layer and the third doped layer and by the fourth doped layer and the

Abstract: A depletion type transistor formed on a semiconductor substrate includes a drain region and a source region formed in distinct areas on the substrate. An inversion layer is formed in the surface area between the drain and the source regions. The transistor further includes two insulated gates: a floating gate located above the substrate and insulated from the inversion layer by an insulating layer in such a way as to cover the inversion layer, and a control gate provided above the floating gate and insulated from the floating gate by the insulating layer.

Abstract: A MOSFET transistor device with a gate formed over a lightly doped semiconductor substrate with a gate, and a source region and a drain region. V.sub.T1 ions are uniformly implanted into the surface of the substrate forming a V.sub.T region with substantially uniform doping in the upper portion of the substrate near the surface thereof. A gate oxide layer is formed on the substrate. A gate conductor is deposited over the gate oxide layer. A large angle implant is implanted into the region of the device over the source region. Then ions are implanted to form the source and drain regions which are self-aligned with the gate.

Abstract: A current limiter (15) is formed between a silicon substrate (10) and a source region (17) by a channel implant region (20). The channel implant region (20) is not modulated by a gate structure so the maximum voltage that can flow between the silicon substrate (10) and the source region (17) is determined by the doping profile of the ever-present channel implant region (20). A pinch-off structure (12) is used to form a depletion region which can support a large voltage potential between the silicon substrate (10) and the source region (17). In an alternate embodiment, a bipolar device is formed such that a limited current flow can be directed into a base region (32) which is used to modulate a current flow between silicon substrate (30) and an emitter region (38). Using the current limiters (15, 35) it is possible to form an AC current limiter (50) that will limit the current flow regardless of the polarity of the voltage placed across two terminals (51, 52).

Abstract: Articles according to the invention comprise an improved organic thin film transistor (TFT) that can have substantially higher source/drain current on/off ratio than conventional organic TFTs. An exemplary TFT according to the invention comprises, in addition to a p-type first organic material layer (e.g., .alpha.-6T), an n-type second organic material layer (e.g., Alq) in contact with the first material layer. TFTs according to the invention can be advantageously used in, for instance, active liquid crystal displays and electronic memories.

Abstract: A vertical trench power MOS transistor with low on-resistance is obtained by eliminating the inversion region of a conventional structure. In one embodiment, a deep-depletion region is formed between the trench gates to provide forward blocking capability. In another embodiment, forward blocking is achieved by depletion from the trench gates and a junction depletion from a P diffusion between the gates. Both embodiments are preferably fabricated in a cellular geometry. The device may also be provided in a horizontal conduction configuration in which the MOS gate is disposed on the upper surface of the semiconductor wafer over the deep-depletion region.

Abstract: An N-channel and P-channel MOSFET include counterdoping of a threshold voltage (V.sub.T) ion implant for reducing substrate sensitivity and source/drain junction capacitance. An arsenic (As) compensated boron (B) implant is provided in the N-channel MOSFET. A boron (B) compensated arsenic (As) implant is provided in the P-channel MOSFET.

Abstract: AMOS transistor with enhanced electrical characteristics and a method for manufacturing the same. In the channel region, a first impurity region is provided for adjusting a threshold voltage, a second impurity region is provided which serves as a diffusion barrier, and a third impurity region is provided for preventing a punchthrough. These regions are formed sequentially at subsequently shallower depths in the substrate. The disclosed transistor minimizes short-channel effects and punchthrough without reducing the current driving capability of the device.

Abstract: An insulated gate field effect transistor which may be of the thin film type including a non-single crystalline semiconductor layer containing hydrogen or a halogen and having an intrinsic conductivity type. The semiconductor layer is disposed over a substrate including a channel region disposed in the semiconductor layer. Source and drain regions form respective junctions with the channel region where the channel region is disposed between the source and drain regions whereby charge carriers move through the channel region between the source and drain regions in a path substantially parallel to said substrate. A gate insulating film contacts the channel region and includes silicon and nitrogen. A gate electrode contacts the gate insulating film. At least a portion of the channel region contains at least one of oxygen, nitrogen, and carbon in an amount of not exceeding 5.times.10.sup.18 atoms/cm.sup.3.

Abstract: A Fermi-threshold field effect transistor includes a contoured-tub region of the same conductivity type as the source, drain and channel regions and having nonuniform tub depth. The contoured-tub is preferably deeper under the source and/or drain regions than under the channel region. Thus, the tub-substrate junction is deeper under the source and/or drain regions than under the channel region. The diffusion capacitance is thereby reduced compared to a tub having a uniform tub depth, so that a high saturation current is produced at low voltages. The contoured-tub may be formed by an additional implant into the substrate using the gate as a mask.

Abstract: A semiconductor device (10) includes first and second electrically coupled MOS transistors (16, 28) in which the current gain of the second MOS transistor (16) is greater than the current gain of the first MOS transistor (28). Higher carrier mobility is obtained in the second MOS transistor (16) relative to the first MOS transistor (28) by fabrication of the second MOS transistor (16) as a buried channel device. The first MOS transistor (28) includes a gate electrode (44) of the second conductivity type separated from a channel region (46) of the first conductivity type by a gate electric layer (48). The second MOS transistor (16) includes a gate electrode (40) of a first conductivity type overlying a substrate (11) also of the first conductivity type. A channel surface layer (60) of a second conductivity type resides in the substrate (11 ) and is separated from the gate electrode (40) by a gate dielectric layer (58).

Abstract: Disclosed is a MOSFET for controlling the flow of a large number of carriers from one source/drain region to the other source/drain region by applying a voltage to a gate. This MOSFET includes a semiconductor substrate and a transistor. The transistor includes a gate provided on the semiconductor substrate, one source/drain region and the other source/drain region both having a first conductivity type. The MOSFET includes first and second wells of a second conductivity type formed apart from each other on opposite sides of the gate in the main surface of the semiconductor substrate. The first well is such a small well as to accommodate only one source/drain region, while the second well is such a small well as to accommodate only the other source/drain region. The one source/drain region and the other source region are formed in the first and second wells, respectively. No distortion due to thermal stresses remains in the resultant MOSFET, and consequently a highly reliable MOSFET is obtained.

Abstract: A MOSFET device (100) having a silicon carbide substrate (102). A channel region (106) of a first conductivity type and an epitaxial layer (104) of a second conductivity type are located above the silicon carbide substrate (102). First and second source/drain regions (118), also of the first conductivity type are located directly within the channel region (106). No well region is placed between the first and second source/drain regions (118) and the channel region (106). A gate (120) is separated from the channel region (106) by an insulator layer (110). Insulator layer (110) has a thin portion (114) and a thick portion (116).

Abstract: A high saturation current, low leakage, Fermi threshold field effect transistor includes a predetermined minimum doping concentration of the source and drain facing the channel to maximize the saturation current of the transistor. Source and drain doping gradient regions between the source/drain and the channel, respectively, of thickness greater than 300 .ANG. are also provided. The threshold voltage of the Fermi-FET may also be lowered from twice the Fermi potential of the substrate, while still maintaining zero static electric field in the channel perpendicular to the substrate, by increasing the doping concentration of the channel from that which produces a threshold voltage of twice the Fermi potential. By maintaining a predetermined channel depth, preferably about 600 .ANG., the saturation current and threshold voltage may be independently varied by increasing the source/drain doping concentration facing the channel and by increasing the excess carrier concentration in the channel, respectively.

Abstract: The present invention is directed to a charge transfer apparatus. A reset gate (RG) is formed of an N-channel MOSFET of depletion type in which a carrier concentration of a channel region is set in a range from 10.sup.15 to 5.times.10.sup.16 cm.sup.-3. Also, a circuit for generating a reset pulse that is supplied to the reset gate (RG) is constructed as follows. A drain voltage source (12) and a drain of a transistor (Tr) are connected via a junction (a), and two resistors (R1) and (R2) are connected in series between the anode of the drain voltage source (12) and the ground. A junction (b) between the resistors (R1) and (R2) and the reset gate (RG) are connected together via an input line (13) and a high resistance (Rh) is inserted into the input line (13). Further, a coupling capacitor (Cc) is connected between a clock pulse input terminal (.phi.in) and the input line (13).

Abstract: A trench MOSFET that includes a charge carrier getter region to substantially deplete a plurality of body regions during an off-state of this MOSFET to produce a very low off-state leakage current. In a first class of embodiments, this charge carrier getter region is a thin layer of material, of opposite conductivity type to that of the body regions, and located between a plurality of gate regions and the body regions. In a second class of embodiments, the gate regions are of opposite conductivity type to the body regions to function as a charge carrier getter region as well as a gate region.

Abstract: A high current Fermi-FET includes an injector region of the same conductivity type as the Fermi-Tub region and the source and drain regions, located adjacent the source region and facing the drain region. The injector region is preferably doped at a doping level which is intermediate the relatively low doping concentration of the Fermi-Tub and the relatively high doping concentration of the source region. The injector region controls the depth of the carriers injected into the channel and maximizes injection of carriers into the channel at a predetermined depth below the gate. The injector region may also extend to the Fermi-tub depth to decrease bottom leakage current. Alternatively, a bottom leakage current control region may be used to decrease bottom leakage current. Lower pinch-off voltage and increased saturation current are obtained by providing a gate sidewall spacer which extends from adjacent the source injector region to adjacent the sidewall of the polysilicon gate electrode of the Fermi-FET.

Abstract: A field effect transistor includes a polycrystalline silicon gate having a semiconductor junction therein. The semiconductor junction is formed of first and second oppositely doped polycrystalline silicon layers, and extends parallel to the substrate face. The polycrystalline silicon gate including the semiconductor junction therein is perfectly formed by implanting ions into the top of the polycrystalline silicon gate simultaneous with implantation of the source and drain regions. The semiconductor junction thus formed does not adversely impact the performance of the field effect transistor, and provides a low resistance ohmic gate contact. The gate need not be masked during source and drain implant, resulting in simplified fabrication.

Abstract: An improved Fermi FET structure with low gate and diffusion capacity allows conduction carriers to flow within the channel at a predetermined depth in the substrate below the gate, without requiring an inversion layer to be created at the surface of the semiconductor. The low capacity Fermi FET is preferably implemented using a Fermi Tub having a predetermined depth, and with a conductivity type opposite the substrate conductivity type and the same conductivity type as the drain and source diffusions.

Abstract: A polysilicon gate (42) of an N-channel MOSFET (40) includes a P+ doped central portion (42a), and N+ doped lateral portions (42b,42c) which face an N-type source (24c) and drain (26c) respectively. An N-type dopant is implanted into the surface portion of a P-type channel region (18) to reduce the surface doping and adjust the transistor threshold voltage to approximately 0.8 volts. The lowered channel doping reduces the electric field at the drain (26c) and suppresses injection of hot electrons from the drain (26c) into the gate oxide (14), and also reduces the electric field across the gate oxide (14) and suppresses charging thereof by hot electrons.

Abstract: A field effect transistor signal switching device includes a semiconductor substrate including an active region; an input electrode disposed on the substrate and including a source electrode disposed on the active region and a source pad; first and second output electrodes respectively including first and second drain electrodes disposed on the active region; and first and second control electrodes disposed on the substrate for controlling the selective transmission of an input signal applied to the input electrode to the first and second output electrodes, the first and second control electrodes respectively including first and second gate electrodes disposed on the active region between the source electrode and the first and second drain electrodes, respectively, first and second gate pads, and first and second connecting portions disposed on the substrate respectively electrically connecting the first and second gate electrodes to the first and second gate pads.

Abstract: Herein disclosed is a CMOSFET, in which an n-channel MISFET Qn has a gate electrode 11n made of n-type polycrystalline silicon, in which a p-channel MISFET Qp has a gate electrode 11p made of p-type polycrystalline silicon, In which the n-channel MISFET Qn and the p-channel MISFET Qp have their respective channel regions formed with heavily doped impurity layers 12p and 12n having the conductivity types identical to those of their wells 3 and 2, and in which the individual heavily doped impurity layers 12p and 12n have their respective surfaces formed with counter-doped layers 13n and 13p having the opposite conductivity types.