Abstract: An IGFET has a non-single crystalline semiconductor layer formed on an insulating surface of a substrate. In a first embodiment, the semiconductor layer is intrinsic n- or p- type and the concentration of oxygen, carbon, or nitrogen in the layer is not higher than 5.times.10.sup.18 atoms/cm.sup.3, source and drain regions are formed in the semiconductor layer by selectively doping with an n-type or p-type impurity and selectively crystallizing the doped portion, and a channel region between the source and drain includes a hydrogen or halogen element. In another embodiment, the semiconductor layer is doped with a dangling bond neutralizer and a P-, I, or N- type channel region is formed in the layer. and a part of the channel region near the source-channel and drain-channel boundaries is selectively crystallized. Alternatively, the source and drain regions may be selectively crystallized without crystallizing the source-channel and drain-channel boundaries.

Abstract: The present invention is directed to a high voltage field effect transistor (FET) constructed on the major surface of a substrate of a first conductivity type. The FET includes a drain region of a second conductivity type located in the major surface and a generally annular drift region of the second conductivity type, located in the major surface and outside of the drain region. A generally annular gate is located on the major surface and outside of the drift region, and a generally annular source region is located in the major surface and outside of the gate. A first channel stop is located in the major surface and outboard of the source region, and a second channel stop located in the major surface and beneath the gate, having at least two portions in close proximity to each other. A channel region is located in the major surface and between the two second channel stop portions. The second channel stop blocks communication between the source region and the drift region except through the channel region.

Abstract: A semiconductor memory device having a non-volatile memory transistor and a selection transistor formed near the non-volatile memory transistor. The channel region surface of the memory transistor is formed to have the same conductivity type with a lower density than the channel region surface of the selection transistor or opposite conductivity type so that the characteristic of the memory transistor shifts to the negative side resulting in a sufficient read margin for an erased cell even at a control voltage of 0.

Abstract: A static random access memory (SRAM) cell uses a pair of conventional cross-coupled MOSFET devices including an inversion layer, and a pair of inversion-free Fermi threshold FET devices, of the same conductivity type as the cross-coupled transistor pair, for resistive loads. The Fermi-FETs provide a high valued resistor, the value of which is independent of current variations and which is easily fabricated without the need to control polycrystalline silicon grain size. The Fermi-FETs may also provide temperature compensation of the SRAM cell so that it is operable over a wide range of temperature. Fermi-FETs may also be used for the pass transistors of the SRAM cell with the Fermi-FET's low gate capacitance minimizing the loading of the word line. A high speed, dense SRAM cell is provided. The Fermi-FET may also be used in other applications which require low input capacitance, high value constant resistance and temperature compensation.

Abstract: A thin-film semiconductor device having a vertical TFT which includes a gate insulating film formed on a sidewall of a throughhole formed in an insulating layer; a thin-film semiconductor layer formed on the gate insulating film; and a gate electrode formed within the insulating layer. The gate electrode, the gate insulating film, and the thin-film semiconductor layer together form a lateral MOS structure. The thin-film semiconductor layer is connected to a bit line at the bottom of the throughhole and to a storage node of a capacitor formed over the switching transistor.

Abstract: The present invention provides a semiconductor device having a well, formed in a semiconductor substrate by using a mask in which a mask pattern width of a portion corresponding to an opening diameter is equal to or less than twice the diffusion depth of the well layer, and a gate electrode formed to have the well layer as a channel region of a MOS transistor. The well formed in this manner has a substantially semi-circular section to facilitate impurity concentration control in the substrate surface. When a plurality of types of opening patterns having small pattern widths are formed in a single mask, MOS transistors having different threshold voltages can be formed in a single process.

Abstract: An output circuit for sequentially receiving and converting charge collected in the photoelements of an image sensor and converting such charge into an output voltage. The output circuit includes a buried-channel LDD transistor having gate, source and drain electrodes. The source electrode provides a floating diffusion. When the transistor is turned off, a potential well is provided in the floating diffusion which collects charge. An output source-follower amplifier also employing buried-channel LDD transistors is connected to the floating diffusion and produces the output voltage.