Abstract: An integrated circuit including a dielectric layer and a method for manufacturing. One embodiment provides a substrate having a first side and a second side and at least one dielectric layer. The dielectric layer includes a zirconium oxide and at least one dopant selected from the group consisting of hafnium and titanium and having a first side and a second side. The first side of the dielectric layer is arranged at least on a subarea of the first side of the semiconductor substrate.

Abstract: A method is disclosed to reduce parasitic capacitance in a metal high dielectric constant (MHK) transistor. The method includes forming a MHK gate stack upon a substrate, the MHK gate stack having a bottom layer of high dielectric constant material, a middle layer of metal, and a top layer of one of amorphous silicon or polycrystalline silicon. The method further forms a depleted sidewall layer on sidewalls of the MHK gate stack so as to overlie the middle layer and the top layer, and not the bottom layer. The depleted sidewall layer is one of amorphous silicon or polycrystalline silicon. The method further forms an offset spacer layer over the depleted sidewall layer and over exposed surfaces of the bottom layer.

Abstract: A transistor device includes a semiconductor substrate, a source doping region and a drain doping region in the semiconductor, a channel region between the source doping region and the drain doping region, a gate stack on the channel region, wherein the gate stack includes an amorphous interfacial layer, a crystalline metal oxide gate dielectric layer and a gate conductor.

Abstract: A method of fabricating a double gate FET on a silicon substrate includes the steps of sequentially epitaxially growing a lower gate layer of crystalline rare earth silicide material on the substrate, a lower gate insulating layer of crystalline rare earth insulating material, an active layer of crystalline semiconductor material, an upper gate insulating layer of crystalline rare earth insulating material, and an upper gate layer of crystalline rare earth conductive material. The upper gate layer and the upper gate electrically insulating layer are etched and a contact is deposited on the upper gate layer to define an upper gate structure. An impurity is implanted into the lower gate layer to define a lower gate area aligned with the upper gate structure. A source and drain are formed in the active layer and contacts are deposited on the source and drain, respectively.

Abstract: It is possible to prevent the deterioration of device characteristic as much as possible. A semiconductor device includes: a semiconductor substrate; a gate insulating film provided above the semiconductor substrate and containing a metal, oxygen and an additive element; a gate electrode provided above the gate insulating film; and source/drain regions provided in the semiconductor substrate on both sides of the gate electrode. The additive element is at least one element selected from elements of Group 5, 6, 15, and 16 at a concentration of 0.003 atomic % or more but 3 atomic % or less.

Abstract: A metal-oxide-semiconductor (MOS) device having a body of single-crystal strontium titanate or barium titanate (10) is provided in which the body comprises a doped semiconductor region (24) adjacent a dielectric region (26). The body may further comprise a doped conductive region separated from the semiconductor region by the dielectric region. The material characteristics of single-crystal strontium titanate when doped in various ways are exploited to provide the insulating, conducting and semiconducting components of a MOS stack. Advantageously, the use of a single body avoids the presence of interface layers between the stack components which improves the characteristics of MOS devices such as field effect transistors.

Abstract: The present invention provides a high-k gate dielectric/metal gate MOSFET that has a reduced parasitic capacitance. The inventive structure includes at least one metal oxide semiconductor field effect transistor (MOSFET) 100 located on a surface of a semiconductor substrate 12. The least one MOSFET 100 includes a gate stack including, from bottom to top, a high-k gate dielectric 28 and a metal-containing gate conductor 30. The metal-containing gate conductor 30 has gate corners 31 located at a base segment of the metal-containing gate conductor. Moreover, the metal-containing gate conductor 30 has vertically sidewalls 102A and 102B devoid of the high-k gate dielectric 28 except at the gate corners 31. A gate dielectric 18 laterally abuts the high-k gate dielectric 28 present at the gate corners 31 and a gate spacer 36 laterally abuts the metal-containing gate conductor 30.

Abstract: An electronic device including a semiconductor layer having silicon as a major component; and a dielectric film epitaxially grown directly on a major surface of the semiconductor layer, wherein the dielectric film consists of a dielectric material having a Ruddlesden-Popper type structure, the Ruddlesden-Popper type structure is expressed by a chemical formula An+1BnO3n+1, the element A including at least one selected from a group consisting of Ba, Sr, Ca and Mg, a percentage of Mg content in the element A is not larger than 10%, and the element B includes at least one selected from a group consisting of Ti, Zr and Hf.

Abstract: Disclosed is a method to fabricate a semiconductor device, and a device fabricated in accordance with the method. The method includes providing a substrate comprised of silicon; performing a shallow trench isolation process to delineate nFET and pFET active areas and, within each active area, forming a gate structure over a surface of the substrate, the gate structure comprising in order from the surface of the substrate, a layer of high dielectric constant oxide, a layer comprised of a metal, a layer comprised of amorphous silicon, and a layer comprised of polycrystalline silicon. The layer comprised of amorphous silicon is provided to substantially prevent regrowth of the high dielectric constant oxide layer in a vertical direction during at least a deposition and processing of the polycrystalline silicon layer and/or metal layer.

Abstract: An integrated circuit having a substrate on which first and second active regions are defined. The first active region comprises a first transistor and the second active region comprises a second transistor having a first type stress. A barrier layer is provided over the substrate to reduce outdiffusion of dopants in the first active region.

Abstract: A method of forming an electropositive metal-containing capping layer atop a stack of a high k gate dielectric/interfacial layer that avoids chemically and physically altering the high k gate dielectric and the interfacial layer is provided. The method includes chemical vapor deposition of an electropositive metal-containing precursor at a temperature that is about 400° C. or less. The present invention also provides semiconductor structures such as, for example, MOSCAPs and MOSFETs, that include a chemical vapor deposited electropositive metal-containing capping layer atop a stack of a high k gate dielectric and an interfacial layer. The presence of the CVD electropositive metal-containing capping layer does not physically or chemically alter the high k gate dielectric and the interfacial layer.

Abstract: A transistor device may comprise a source having a first ferromagnetic contact thereto, a drain having a second ferromagnetic contact thereto, an electrically conductive gate positioned over a channel region separating the source and the drain, and an electrically insulating layer disposed between the gate and the channel region. The first and second ferromagnetic contacts have anti-parallel magnetic orientations relative to each other. The electrically insulating layer includes a number of paramagnetic impurities each having two spin states such that electrons interacting with the paramagnetic impurities cause the paramagnetic impurities to flip between the two spin states.

Abstract: The present invention provides a semiconductor device includes a substrate including a semiconducting region and isolation regions, a gate structure including a high-k gate dielectric layer atop the semiconducting region of the substrate and a metal gate conductor layer atop the high-k gate dielectric; protective nitride spacers enclosing the high-k gate dielectric layer between the metal gate conductor layer and the semiconducting region of the substrate, the protective nitride spacers separating the isolation regions from the high-k dielectric; and a polysilicon gate conductor overlying the metal gate conductor layer and enclosing the protective nitride spacers between at least the high-k dielectric layer, the semiconducting region, and a portion of the polysilicon gate conductor.

Abstract: The present invention is directed to a method of fabricating a high-K dielectric films having a high degree of crystallographic alignment at grain boundaries of the film. A disclosed method involves providing a substrate and then depositing a material used in forming the high-K dielectric film and also using an ion beam to assist in the preferential formation of crystal lattices having a selected crystallographic orientation. The resultant dielectric film having a high degree of crystallographic alignment at grain boundaries of the film. Another disclosed method involves providing a substrate and then angularly depositing a material onto the substrate in order to assist in the preferential formation of crystal lattices having a selected crystallographic orientation. The resultant dielectric film having a high degree of crystallographic alignment at grain boundaries of the film.

Abstract: A method of manufacturing a semiconductor device comprises: forming a gate insulator on a substrate, the gate insulator including a high-dielectric film in whole or part; forming a first metal film on the gate insulator; forming a second metal film on the first metal film; and forming a reaction film between the gate insulator and the first metal film by letting the high-dielectric film and the first metal film react with each other through a thermal treatment.

Abstract: In one embodiment, the present invention includes a double gate transistor having a silicon fin formed on a buried oxide layer and first and second insulation layers formed on a portion of the silicon fin, where at least the second insulation layer has a pair of portions extending onto respective first and second portions of the silicon fin to each act as a self-aligned spacer structure. Other embodiments are described and claimed.

Abstract: A method contains the steps of (a) heating a silicon substrate in a reaction chamber; and (b) supplying film-forming gas containing source gas, nitridizing gas, and nitridation enhancing gas to a surface of the heated silicon substrate, to deposit on the silicon substrate an Hf1-xAlxO:N film (0.1<x<0.3) having a higher specific dielectric constant than that of silicon oxide, and incorporating N, by thermal CVD. The method can form an oxide film of Hf1-xAlxO (0<x<0.3) having desired characteristics, as a gate insulation film.

Abstract: A CMOS structure includes a v-shape surface in an nMOSFET region. The v-shape surface has an orientation in a (100) plane and extends into a Si layer in the nMOSFET region. The nMOSFET gate dielectric layer is a high-k material, such as Hf02. The nMOSFET has a metal gate layer, such as Ta. Poly-Si is deposited on top of the metal gate layer.

Abstract: A semiconductor device structure is described, including a MOS transistor, a silicon-rich silicon nitride layer having a refractive index of about 2.00-2.30, and a dielectric layer. The silicon-rich silicon nitride layer is disposed between the MOS transistor and the dielectric layer, and covers the source/drain region, the spacer and the gate conductor of the MOS transistor.

Abstract: A semiconductor apparatus is disclosed. The semiconductor apparatus comprises a gate electrode formed on a surface of a semiconductor substrate with a gate insulating film provided therebetween. The semiconductor apparatus further comprises a gate sidewall insulating film having a three-layered structure formed of a first nitride film, an oxide film, and a second nitride film, which are formed on a sidewall of an upper portion of the gate electrode, and a gate sidewall insulating film having a two-layered structure formed of the oxide film and the second nitride film, which are formed on a sidewall of a lower portion of the gate electrode. The semiconductor apparatus further comprises a raised source/drain region formed of an impurity region formed in a surface layer of the semiconductor substrate and an impurity region grown on the impurity region.

Abstract: A dielectric layer containing a hafnium tantalum oxide film and a method of fabricating such a dielectric layer produce a dielectric layer for use in a variety of electronic devices. Embodiments include structures for capacitors, transistors, memory devices, and electronic systems with dielectric layers containing a hafnium tantalum oxide film structured as one or more monolayers.

Abstract: A semiconductor apparatus is disclosed. The semiconductor apparatus comprises a gate electrode formed on a surface of a semiconductor substrate with a gate insulating film provided therebetween. The semiconductor apparatus further comprises a gate sidewall insulating film having a three-layered structure formed of a first nitride film, an oxide film, and a second nitride film, which are formed on a sidewall of an upper portion of the gate electrode, and a gate sidewall insulating film having a two-layered structure formed of the oxide film and the second nitride film, which are formed on a sidewall of a lower portion of the gate electrode. The semiconductor apparatus further comprises a raised source/drain region formed of an impurity region formed in a surface layer of the semiconductor substrate and an impurity region grown on the impurity region.

Abstract: It is made possible to provide a semiconductor device that has the effective work function of the connected metal optimized at the interface between a semiconductor and the metal. A semiconductor device includes: a semiconductor film; an oxide film formed on the semiconductor film, the oxide film including at least one of Hf and Zr, and at least one element selected from the group consisting of V, Cr, Mn, Nb, Mo, Tc, W, and Re being added to the oxide film; and a metal film formed on the oxide film.

Abstract: Encapsulation of a gate stack comprising a high-k dielectric material may be accomplished on the basis of a silicon nitride material that is deposited in a sequence of two deposition processes, in which the first process may be performed on the basis of a moderately low process temperature, thereby passivating sensitive surfaces without unduly contaminating the same, while, in a second deposition process, a moderately high process temperature may be used to provide enhanced material characteristics and a reduced overall cycle time compared to conventional ALD or multi-layer deposition techniques.

Abstract: A P-type MOSFET 120 includes a semiconductor substrate (N-well 102b); a gate insulating film formed on the semiconductor substrate, composed of a high-dielectric-constant film 108 which contains a silicate compound containing a first element selected from the group consisting of Hf, Zr and any of lanthanoids, together with N; a gate electrode formed on the gate insulating film, and is configured by a polysilicon film 114 containing a P-type impurity; and a blocking oxide film 110 formed between the gate insulating film and the gate electrode, blocking a reaction between the first element and the polysilicon film 114, and having a relative dielectric constant of 8 or above.

Abstract: CMOS devices with transistors having different gate dielectric materials and methods of manufacture thereof are disclosed. A CMOS device is formed on a workpiece having a first region and a second region. A first gate dielectric material is deposited over the second region. A first gate material is deposited over the first gate dielectric material. A second gate dielectric material comprising a different material than the first gate dielectric material is deposited over the first region of the workpiece. A second gate material is deposited over the second gate dielectric material. The first gate material, the first gate dielectric material, the second gate material, and the second gate dielectric material are then patterned to form a CMOS device having a symmetric Vt for the PMOS and NMOS FETs.

Abstract: Disclosed herein is a semiconductor device, including: an insulating film provided on a semiconductor substrate so as to have a trench pattern; a gate insulating film provided so as to cover an inner wall of the trench pattern; and a gate electrode formed so as to be filled in the trench pattern through the gate insulating film and so as to protrude more widely than the trench pattern on both sides of the trench pattern on the insulating film.

Abstract: A semiconductor device includes a semiconductor substrate; an insulation film provided on the semiconductor substrate; and an electrode provided on the insulation film, and containing boron and a semiconductor material, wherein at least one element of the group V and carbon is introduced into an interface between the insulation film and the electrode.

Abstract: A semiconductor device includes first and second transistor devices. The first device includes a first substrate region, a first gate electrode, and a first gate dielectric. The first gate dielectric is located between the first substrate region and the first gate electrode. The second device includes a second substrate region, a second gate electrode, and a second gate dielectric. The second gate dielectric is located between the second substrate region and the second gate electrode. The first gate dielectric includes a first high-k layer having a dielectric constant of 8 or more. Likewise, the second gate dielectric includes a second high-k layer having a dielectric constant of 8 or more. The second high-k layer has a different material composition than the first high-k layer.

Abstract: By providing a CMP stop layer in a metal gate stack, the initial height thereof may be efficiently reduced after the definition of the deep drain and source areas, thereby providing enhanced process conditions for forming highly stressed dielectric materials. Consequently, the dielectric material may be positioned more closely to the channel region substantially without deteriorating gate conductivity.

Abstract: A circuit and method are disclosed for reducing device mismatch due to trench isolation related stress. One or more extended active regions are formed on the substrate, wherein the active regions being extended from one or more ends thereof, and one or more operational devices are placed on one or more active regions, wherein the extended active region has at least a length twice as much as a distance between gates of two neighboring operational devices.

Abstract: An semiconductor device (1) of the invention includes a semiconductor substrate provided with a channel region (21), a source region (22) and a drain region (23), a gate insulating film (3) laminated on the channel region (21), and a gate electrode (5). The gate insulating film (3) is formed of an insulative inorganic material as a main material, and further contains hydrogen. The absorbance of infrared radiation of which wave number is in the range of 3200 to 3500 cm?1 is 0.02 or less when the gate insulating film (3) to which an electric field has never been applied is measured with Fourier Transform Infrared Spectroscopy at room temperature.

Abstract: A semiconductor device includes: a high dielectric constant gate insulating film formed on an active region in a substrate; a gate electrode formed on the high dielectric constant gate insulating film; and an insulating sidewall formed on each side surface of the gate electrode. The high dielectric constant gate insulating film is continuously formed so as to extend from under the gate electrode to under the insulating sidewall. At least part of the high dielectric constant gate insulating film located under the insulating sidewall has a smaller thickness than a thickness of part of the high dielectric constant gate insulating film located under the gate electrode.

Abstract: A new method is provided for creating an inductor on the surface of a silicon substrate. The invention provides overlying layers of oxide fins beneath a metal inductor. The oxide fins provide the stability support for the overlying metal inductor while also allowing horizontal air columns to simultaneously exist underneath the inductor. Overlying layers of air cavities that are spatially inserted between the created overlying layers of oxide fins can be created under the invention by repetitive application of the mask used. The presence of the air wells on the surface of the substrate significantly reduces parasitic capacitances and series resistance of the inductor associated with the substrate.

Abstract: An apparatus for evaluating a field-effect transistor includes a pulse generator, a current/voltage converter, a switch and a first constant-voltage source. The pulse generator can be electrically connected to a gate electrode of a field-effect transistor. The current/voltage converter includes an input terminal. The input terminal can be electrically connected to a first source/drain region of the field-effect transistor. The switch can be electrically connected to a second source/drain region of the field-effect transistor. The switch switches between a connection state and a disconnection state. The first constant-voltage source can be electrically connected to the second source/drain region through the switch.

Abstract: Method of fabricating TFTs (thin-film transistors) having a crystallized silicon film and a gate-insulating film. First, an amorphous silicon film is formed on an insulating substrate. A first dielectric film is formed from silicon oxide on the amorphous silicon film. Holes are formed in the first dielectric film to selectively expose the surface of the amorphous silicon film. Nickel is introduced as the metal element into the amorphous silicon film. The film is heat-treated, thus forming crystallized silicon film. This crystalline silicon film is etched together with the silicon oxide film to form an active layer. The etched silicon oxide film acts as the aforementioned gate-insulating film. Even after the crystallization step, the silicon oxide film is left behind. As a result, the interface with the crystalline silicon film is kept in a good state.

Abstract: A MOSFET having a nitrided gate dielectric and its manufacture are disclosed. The method comprises providing a substrate and depositing a non-high-k dielectric material on the substrate. The non-high-k dielectric comprises two layers. The first layer adjacent the substrate is essentially nitrogen-free, and the second layer includes between about 1015 atoms/cm3 to about 1022 atoms/cm3 nitrogen. The MOSFET further includes a high-k dielectric material on the nitrided, non-high-k dielectric. The high-k dielectric preferably includes HfSiON, ZrSiON, or nitrided Al2O3. Embodiments further include asymmetric manufacturing techniques wherein core and peripheral integrated circuit areas are separately optimized.

Abstract: Embodiments of the invention provide a device with a metal gate, a high-k gate dielectric layer and reduced oxidation of a substrate beneath the high-k gate dielectric layer. An oxygen barrier, or capping, layer on the high-k gate dielectric layer and metal gate may prevent such oxidation during processes such as spacer formation and annealing of ion implanted regions.

Abstract: An N-type Schottky barrier Source/Drain Transistor (N-SSDT) that uses ytterbium silicide (YbSi2-x) for the source and drain is described. The structure includes a suitable capping layer stack.

Abstract: Example embodiments relate to a semiconductor device and a method of manufacturing the same. A semiconductor device according to example embodiments may have reduced disturbances during reading operations and a reduced short channel effect. The semiconductor device may include a semiconductor substrate having a body and a pair of fins protruding from the body. Inner spacer insulating layers may be formed on an upper portion of an inner sidewall of the pair of fins so as to reduce the entrance to the region between the pair of fins. A gate electrode may cover a portion of the external sidewalls of the pair of fins and may extend across the inner spacer insulating layers so as to define a void between the pair of fins. Gate insulating layers may be interposed between the gate electrode and the pair of fins.

Abstract: Provided is a field effect transistor, provided with a gate electrode 15, a source electrode 13, and a drain electrode 14 formed on a substrate, including a channel layer 11 formed of an oxide containing In, Zn, or Sn as the main component, and a gate insulating layer 12 provided between the channel layer 11 and the gate electrode 15, in which the gate insulating layer 12 is formed of an amorphous oxide containing Ga as the main component.

Abstract: In a transistor adapted to suppress characteristic degradation resulting from fluorine contained in a deposited film, the concentration of fluorine contained in a gate insulating film (3) is reduced to 1.0×1020 atoms/cm3 or less. As a result, the transistor can provide excellent reliability even when it is continuously driven for a long period of time at a relatively high temperature.

Abstract: A metal oxide semiconductor (MOS) transistor with a Y structure metal gate is provided. The MOS transistor includes a substrate, a Y structure metal gate positioned on the substrate, two doping regions disposed in the substrate on two sides of the Y structure metal structure, a spacer, an insulating layer positioned outside the spacer, a dielectric layer positioned outside the insulating layer and a bevel edge covering the spacer. The spacer has a vertical sidewall, and the vertical sidewall surrounds a recess. A part of the Y structure metal gate is disposed in the recess, and a part of the Y structure metal gate is positioned on the bevel edge.

Abstract: A dielectric film containing HfAlO3 and a method of fabricating such a dielectric film produce a reliable gate dielectric having an equivalent oxide thickness thinner than attainable using SiO2. A gate dielectric is formed by atomic layer deposition employing a hafnium sequence and an aluminum sequence. The hafnium sequence uses HfCl4 and water vapor. The aluminum sequence uses either trimethylaluminium, Al(CH3)3, or DMEAA, an adduct of alane (AlH3) and dimethylehtylamine [N(CH3)2(C2H5)], with distilled water vapor. These gate dielectrics containing a HfAlO3 film are thermodynamically stable such that the HfAlO3 film will have minimal reactions with a silicon substrate or other structures during processing.

Abstract: In a method for manufacturing a semiconductor device having an N-channel field effect transistor, the N-channel field effect transistor is formed by a process including the steps of forming a high dielectric constant gate insulating film on a substrate, forming a gate electrode on the high dielectric constant gate insulating film, forming an extension region by introducing N-type impurities into the substrate by using at least the gate electrode as a mask, and forming a pocket region by introducing P-type impurities under the extension region in the substrate by using at least the gate electrode as a mask. An amount of arsenic (As) that is introduced as the N-type impurities is in a range that is equal to or lower than a prescribed value that is determined based on a thickness of the high dielectric constant gate insulating film.

Abstract: A semiconductor structure and a method of forming the same. The semiconductor structure includes a semiconductor substrate, a gate dielectric layer on top of the semiconductor substrate. The structure also includes a first metal containing region on top of the gate dielectric layer. The structure also includes a second metal containing region on top of the gate dielectric layer wherein the first and second metal containing regions are in direct physical contact with each other. The structure further includes a gate electrode layer on top of both the first and second metal containing regions and the gate electrode layer is in direct physical contact with both the first and second metal containing regions. The structure further includes a patterned photoresist layer on top of the gate electrode layer.

Abstract: A high-k dielectric and metal gate stack with minimal overlap with an adjacent oxide isolation region and related methods are disclosed. One embodiment of the gate stack includes a high dielectric constant (high-k) dielectric layer, a tuning layer and a metal layer positioned over an active region defined by an oxide isolation region in a substrate, wherein an outer edge of the high-k dielectric layer, the tuning layer and the metal layer overlaps the oxide isolation region by less than approximately 200 nanometers. The gate stack and related methods eliminate the regrowth effect in short channel devices by restricting the amount of overlap area between the gate stack and adjacent oxide isolation regions.

Abstract: A semiconductor device may include a semiconductor substrate having a first region and a second region. The nitrogen-incorporated active region may be formed within the first region. A first gate electrode may be formed on the nitrogen-incorporated active region. A first gate dielectric layer may be interposed between the nitrogen-incorporated active region and the first gate electrode. The first gate dielectric layer may include a first dielectric layer and a second dielectric layer. The second dielectric layer may be a nitrogen contained dielectric layer. A second gate electrode may be formed on the second region. A second gate dielectric layer may be interposed between the second region and the second gate electrode. The first gate dielectric layer may have the same or substantially the same thickness as the second gate dielectric layer, and the nitrogen contained dielectric layer may contact with the nitrogen-incorporated active region.

Abstract: The present invention generally is a method for forming a high-k dielectric layer, comprising depositing a hafnium compound by atomic layer deposition to a substrate, comprising, delivering a hafnium precursor to a surface of the substrate, reacting the hafnium precursor and forming a hafnium containing layer to the surface, delivering a nitrogen precursor to the hafnium containing layer, forming at least one hafnium nitrogen bond and depositing the hafnium compound to the surface.

Abstract: The present invention is a method of film deposition that comprises a film-depositing step of supplying a high-melting-point organometallic material gas and a nitrogen-containing gas to a processing vessel that can be evacuated, so as to deposit a thin film of a metallic compound of a high-melting-point metal on a surface of an object to be processed placed in the processing vessel. A partial pressure of the nitrogen-containing gas during the film-depositing step is 17% or lower, in order to increase carbon density contained in the thin film.