Gate Insulator Includes Material (including Air Or Vacuum) Other Than Sio 2 Patents (Class 257/410)
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Patent number: 7872291Abstract: A method of enhanced atomic layer deposition is described. In an embodiment, the enhancement is the use of plasma. Plasma begins prior to flowing a second precursor into the chamber. The second precursor reacts with a prior precursor to deposit a layer on the substrate. In an embodiment, the layer includes at least one element from each of the first and second precursors. In an embodiment, the layer is TaN. In an embodiment, the precursors are TaF5 and NH3. In an embodiment, the plasma begins during the purge gas flow between the pulse of first precursor and the pulse of second precursor. In an embodiment, the enhancement is thermal energy. In an embodiment, the thermal energy is greater than generally accepted for ALD (>300 degrees Celsius). The enhancement assists the reaction of the precursors to deposit a layer on a substrate.Type: GrantFiled: September 17, 2007Date of Patent: January 18, 2011Assignee: Round Rock Research, LLCInventors: Shuang Meng, Garo J. Derderian, Gurtej Singh Sandhu
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Patent number: 7871915Abstract: The present disclosure provides a method of fabricating a semiconductor device that includes providing a substrate having a first region and a second region, forming first and second gate stacks in the first and second regions, respectively, the first gate stack including a first dummy gate and the second gate stack including a second dummy gate, removing the first dummy gate in the first gate stack thereby forming a first trench and removing the second dummy gate in the second gate stack thereby forming a second trench, forming a first metal layer in the first trench and in the second trench, removing at least a portion of the first metal layer in the first trench, forming a second metal layer in the remainder of the first trench and in the remainder of the second trench, reflowing the second metal layer, and performing a chemical mechanical polishing (CMP).Type: GrantFiled: March 26, 2009Date of Patent: January 18, 2011Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Peng-Soon Lim, Yong-Tian Hou, Chien-Hao Chen, Chi-Chun Chen
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Patent number: 7872298Abstract: Performance and reliability of a semiconductor device including a non-volatile memory are improved. A memory cell of the non-volatile memory includes, over an upper portion of a semiconductor substrate, a select gate electrode formed via a first dielectric film and a memory gate electrode formed via a second dielectric film formed of an ONO multilayered film having a charge storing function. The first dielectric film functions as a gate dielectric film, and includes a third dielectric film made of silicon oxide or silicon oxynitride and a metal-element-containing layer made of a metal oxide or a metal silicate formed between the select gate electrode and the third dielectric film. A semiconductor region positioned under the memory gate electrode and the second dielectric film has a charge density of impurities lower than that of a semiconductor region positioned under the select gate electrode and the first dielectric film.Type: GrantFiled: July 13, 2007Date of Patent: January 18, 2011Assignee: Renesas Electronics CorporationInventors: Yasuhiro Shimamoto, Digh Hisamoto, Tetsuya Ishimaru, Shinichiro Kimura
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Patent number: 7863694Abstract: A thin film transistor having an improved gate dielectric layer is disclosed. The gate dielectric layer comprises a poly(hydroxyalkyl acrylate-co-acrylonitrile) based polymer. The resulting gate dielectric layer has a high dielectric constant and can be crosslinked. Higher gate dielectric layer thicknesses can be used to prevent current leakage while still having a large capacitance for low operating voltages. Methods for producing such gate dielectric layers and/or thin film transistors comprising the same are also disclosed.Type: GrantFiled: October 14, 2008Date of Patent: January 4, 2011Assignee: Xerox CorporationInventors: Ping Liu, Yiliang Wu, Yuning Li, Paul F. Smith
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Patent number: 7863139Abstract: A method of fabricating a double gate FET on a silicon substrate includes the steps of sequentially epitaxially growing a lower gate layer of crystalline rare earth silicide material on the substrate, a lower gate insulating layer of crystalline rare earth insulating material, an active layer of crystalline semiconductor material, an upper gate insulating layer of crystalline rare earth insulating material, and an upper gate layer of crystalline rare earth conductive material. The upper gate layer and the upper gate electrically insulating layer are etched and a contact is deposited on the upper gate layer to define an upper gate structure. An impurity is implanted into the lower gate layer to define a lower gate area aligned with the upper gate structure. A source and drain are formed in the active layer and contacts are deposited on the source and drain, respectively.Type: GrantFiled: November 25, 2009Date of Patent: January 4, 2011Inventor: Petar B. Atanakovic
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Publication number: 20100327376Abstract: A method forms a metal high dielectric constant (MHK) transistor and includes: providing a MHK stack disposed on a substrate, the MHK stack including a first layer of high dielectric constant material, a second overlying layer, and a third overlying layer; selectively removing only the second and third layers, without removing the first layer, to form an upstanding portion of a MHK gate structure; forming a first sidewall layer on sidewalls of the upstanding portion of the MHK gate structure; forming a second sidewall layer on sidewalls of the first sidewall layer; removing a portion of the first layer to form exposed surfaces; forming an offset spacer layer over the second sidewall layer and over the first layer, and forming in the substrate extensions that underlie the first and second sidewall layers and that extend under a portion but not all of the upstanding portion of the MHK gate structure.Type: ApplicationFiled: September 13, 2010Publication date: December 30, 2010Applicant: International Business Machines CorporationInventors: Leland Chang, Jeffrey W. Sleight, Isaac Lauer, Renee T. Mo
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Patent number: 7851835Abstract: A display substrate includes a substrate, a first insulating layer, an undercut compensating member, a first electrode, a second insulating layer and a first conductive pattern. The first insulating layer is formed on the substrate. The undercut compensating member is formed on the first insulating layer. The undercut compensating member has an etching rate smaller than that of the first insulating layer. The first electrode is formed on a portion of the undercut compensating member. The second insulating layer is formed on the first insulating layer. The second insulating layer has a contact hole through which a portion of the first electrode and a remaining portion of the undercut compensating member. The first conductive pattern electrically connected to the first electrode through the contact hole.Type: GrantFiled: July 27, 2006Date of Patent: December 14, 2010Assignee: Samsung Electronics Co., Ltd.Inventors: Shin-Tack Kang, Dong-Hyeon Ki, Sung-Man Kim, Sang-Hoon Lee
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Publication number: 20100308412Abstract: A high-k metal gate stack and structures for CMOS devices and a method for forming the devices. The gate stack includes a high-k dielectric having a high dielectric constant greater than approximately 3.9, a germanium (Ge) material layer interfacing with the high-k dielectric, and a conductive electrode layer disposed above the high-k dielectric or the Ge material layer. The gate stack optimizes a shift of the flatband voltage or the threshold voltage to obtain high performance in p-FET devices.Type: ApplicationFiled: June 3, 2009Publication date: December 9, 2010Applicant: International Business Machines CorporationInventors: Hemanth Jagannathan, Takashi Ando, Vijay Narayanan
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Patent number: 7847325Abstract: A discrete trap memory, comprising a silicon substrate layer, a bottom oxide layer on the silicon substrate layer, a Fullerene layer on the bottom oxide layer, a top oxide layer on the Fullerene layer, and a gate layer on the top oxide layer; wherein the Fullerene layer comprises spherical, elliptical or endohedral Fullerenes that act as charge traps.Type: GrantFiled: March 12, 2009Date of Patent: December 7, 2010Assignee: Infineon Technologies AGInventors: Gerhard Poeppel, Georg Tempel
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Patent number: 7847356Abstract: Disclosed is a method to fabricate a semiconductor device, and a device fabricated in accordance with the method. The method includes providing a substrate comprised of silicon; performing a shallow trench isolation process to delineate nFET and pFET active areas and, within each active area, forming a gate structure over a surface of the substrate, the gate structure comprising in order from the surface of the substrate, a layer of high dielectric constant oxide, a layer comprised of a metal, a layer comprised of amorphous silicon, and a layer comprised of polycrystalline silicon. The layer comprised of amorphous silicon is provided to substantially prevent regrowth of the high dielectric constant oxide layer in a vertical direction during at least a deposition and processing of the polycrystalline silicon layer and/or metal layer.Type: GrantFiled: August 18, 2009Date of Patent: December 7, 2010Assignee: International Business Machines CorporationInventors: Tze-Chiang Chen, Bruce B. Doris, Vijay Narayanan, Vamsi Paruchuri
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Publication number: 20100301428Abstract: Electronic apparatus and methods of forming the electronic apparatus include a tantalum silicon oxynitride film on a substrate for use in a variety of electronic systems. The tantalum silicon oxynitride film may be structured as one or more monolayers. The tantalum silicon oxynitride film may be formed using a monolayer or partial monolayer sequencing process. Metal electrodes may be disposed on a dielectric containing a tantalum silicon oxynitride film.Type: ApplicationFiled: August 12, 2010Publication date: December 2, 2010Inventors: Leonard Forbes, Kie Y. Ahn, Arup Bhattacharyya
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Patent number: 7843007Abstract: A method is disclosed to reduce parasitic capacitance in a metal high dielectric constant (MHK) transistor. The method includes forming a MHK gate stack upon a substrate, the MHK gate stack having a bottom layer of high dielectric constant material, a middle layer of metal, and a top layer of one of amorphous silicon or polycrystalline silicon. The method further forms a depleted sidewall layer on sidewalls of the MHK gate stack so as to overlie the middle layer and the top layer, and not the bottom layer. The depleted sidewall layer is one of amorphous silicon or polycrystalline silicon. The method further forms an offset spacer layer over the depleted sidewall layer and over exposed surfaces of the bottom layer.Type: GrantFiled: August 12, 2009Date of Patent: November 30, 2010Assignee: International Business Machines CorporationInventors: Leland Chang, Isaac Lauer, Renee T. Mo, Jeffrey W. Sleight
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Patent number: 7842996Abstract: A memory cell of a nonvolatile semiconductor memory includes a semiconductor region, source/drain areas arranged separately from each other in the semiconductor region, a tunnel insulating film arranged on a channel region between the diffusion areas, a floating gate electrode arranged on the tunnel insulating film, an inter-electrode insulator arranged on the floating gate electrode, and a control gate electrode arranged on the inter-electrode insulator. The inter-electrode insulator includes lanthanoid-based metal Ln, aluminum Al, and oxygen O, and a composition ratio Ln/(Al+Ln) between the lanthanoid-based metal and the aluminum takes a value within the range of 0.33 to 0.39.Type: GrantFiled: June 19, 2008Date of Patent: November 30, 2010Assignee: Kabushiki Kaisha ToshibaInventors: Shoko Kikuchi, Akira Takashima, Naoki Yasuda, Koichi Muraoka
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Patent number: 7838406Abstract: The present invention is a semiconductor device including a semiconductor substrate having a trench, a first insulating film provided on side surfaces of the trench, a second insulating film of a material different from the first insulating film provided to be embedded in the trench, a word line provided extending to intersect with the trench above the semiconductor substrate, a gate insulating film of a material different from the first insulating film separated in an extending direction of the word line by the trench and provided under a central area in a width direction of the word line, and a charge storage layer separated in the extending direction of the word line by the trench and provided under both ends in the width direction of the word line to enclose the gate insulating film, and a method for manufacturing the same.Type: GrantFiled: December 24, 2008Date of Patent: November 23, 2010Assignee: Spansion LLCInventors: Takayuki Maruyama, Fumihiko Inoue
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Patent number: 7834408Abstract: It is possible to prevent the deterioration of device characteristic as much as possible. A semiconductor device includes: a semiconductor substrate; a gate insulating film provided above the semiconductor substrate and containing a metal, oxygen and an additive element; a gate electrode provided above the gate insulating film; and source/drain regions provided in the semiconductor substrate on both sides of the gate electrode. The additive element is at least one element selected from elements of Group 5, 6, 15, and 16 at a concentration of 0.003 atomic % or more but 3 atomic % or less.Type: GrantFiled: January 22, 2009Date of Patent: November 16, 2010Assignee: Kabushiki Kaisha ToshibaInventors: Yuuichi Kamimuta, Akira Nishiyama, Yasushi Nakasaki, Tsunehiro Ino, Masato Koyama
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Patent number: 7833890Abstract: Example embodiments relate to a semiconductor device and a method of manufacturing the same. A semiconductor device according to example embodiments may have reduced disturbances during reading operations and a reduced short channel effect. The semiconductor device may include a semiconductor substrate having a body and a pair of fins protruding from the body. Inner spacer insulating layers may be formed on an upper portion of an inner sidewall of the pair of fins so as to reduce the entrance to the region between the pair of fins. A gate electrode may cover a portion of the external sidewalls of the pair of fins and may extend across the inner spacer insulating layers so as to define a void between the pair of fins. Gate insulating layers may be interposed between the gate electrode and the pair of fins.Type: GrantFiled: June 9, 2009Date of Patent: November 16, 2010Assignee: Samsung Electronics Co., Ltd.Inventors: Won-joo Kim, June-mo Koo, Seung-hwan Song, Suk-pil Kim, Yoon-dong Park, Jong-jin Lee
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Patent number: 7834405Abstract: A semiconductor device includes a semiconductor substrate, wherein the semiconductor substrate includes a core area for core circuits and a peripheral area for peripheral circuits. The semiconductor device includes a core oxide on the semiconductor substrate in the core area, a portion of the core oxide being nitrided, a first polysilicon pattern on the core oxide, an I/O oxide including pure oxide on the semiconductor substrate in the peripheral area, and a second polysilicon pattern on the I/O oxide.Type: GrantFiled: July 15, 2005Date of Patent: November 16, 2010Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Zhen-Cheng Wu, Yung-Cheng Lu, Pi-Tsung Chen, Ying-Tsung Chen
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Patent number: 7833865Abstract: A semiconductor device includes a silicon substrate; an insulation layer formed on the silicon substrate, the insulation layer containing an oxide of an element of at least one kind selected from at least Hf, Zr, Ti and Ta; an electrode formed on the insulation layer; and a metal oxide layer containing La and Al, the metal oxide layer being provided at at least one of an interface between the silicon substrate and the insulation layer and an interface between the insulation layer and the electrode.Type: GrantFiled: May 5, 2008Date of Patent: November 16, 2010Assignee: Kabushiki Kaisha ToshibaInventors: Masamichi Suzuki, Daisuke Matsushita, Takeshi Yamaguchi
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Publication number: 20100276763Abstract: A transistor comprises a gate (110) comprising a gate electrode (111) and a gate dielectric (112), an electrically insulating cap (120, 720) over the gate, and a source/drain contact (130) adjacent to the gate. The electrically insulating cap prevents electrical contact between the gate and the source/drain contact. In one embodiment, the electrically insulating cap is formed in a trench (160, 660) that is self-aligned to the gate and that is created by the removal of a sacrificial cap using an aqueous solution comprising a carboxylic acid and a corrosion inhibitor.Type: ApplicationFiled: July 15, 2010Publication date: November 4, 2010Inventors: Willy Rachmady, Vijay Ramachandrarao, Oleg Golonzka, Arnel M. Fajardo
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Patent number: 7825043Abstract: A method for fabricating a capacitor in a semiconductor device includes: forming a bottom electrode; forming a ZrxAlyOz dielectric layer on the bottom electrode using an atomic layer deposition (ALD) method, wherein the ZrxAlyOz dielectric layer comprises a zirconium (Zr) component, an aluminum (Al) component and an oxygen (O) component mixed in predetermined mole fractions of x, y and z, respectively; and forming a top electrode on the ZrxAlyOz dielectric layer.Type: GrantFiled: June 28, 2006Date of Patent: November 2, 2010Assignee: Hynix Semiconductor Inc.Inventor: Kee-Jeung Lee
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Publication number: 20100270626Abstract: There is provided an improved method for depositing thin films using precursors to deposit binary oxides by atomic layer deposition (ALD) techniques. Also disclosed is an ALD method for depositing a high-k dielectric such as hafnium lanthanum oxide (HfLaO) on a substrate. Embodiments of the present invention utilize a combination of ALD precursor elements and cycles to deposit a film with desired physical and electrical characteristics. Electronic components and systems that integrate devices fabricated with methods consistent with the present invention are also disclosed.Type: ApplicationFiled: April 27, 2009Publication date: October 28, 2010Inventor: Petri I. Raisanen
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Patent number: 7821809Abstract: A nonvolatile memory device including one resistor and one transistor. The resistor may correspond to a resistance layer electrically connected to a first impurity region and a second impurity region of the transistor.Type: GrantFiled: November 7, 2005Date of Patent: October 26, 2010Assignee: Samsung Electronics Co., Ltd.Inventors: In-Kyeong Yoo, Myoung-Jae Lee, Sun-Ae Seo, David Seo
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Patent number: 7820504Abstract: Embodiments of this invention relate to a method for manufacturing isolation structures with different depths in a monolithically integrated semiconductor electronic device. An inventive method according to an embodiment of the invention comprises a first step of defining active areas on a semiconductor material substrate, a second step of forming isolation structures by realising trenches in said substrate and then filling them with field oxide, a third step of defining lithographically at least a first device area, and a fourth step of realising a digging in the substrate and in the field oxide of said first device area.Type: GrantFiled: July 12, 2004Date of Patent: October 26, 2010Inventors: Daniela Brazzelli, Livio Baldi, Giorgio Servalli
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Patent number: 7821083Abstract: A semiconductor device includes a structure of a gate electrode/a high-k dielectric insulating film containing aluminum and having a dielectric constant greater than that of a silicon oxide film/the silicon oxide film/a silicon substrate, and is provided with a diffusion layer formed by diffusing an aluminum atom or an aluminum ion to the silicon oxide film or an interface between the silicon oxide film and the silicon substrate by a heat treatment. A laminated film or a mixed film of hafnium oxide and aluminum oxide having a ratio of hafnium and aluminum ranging from about 2:8 to 8:2 is used as the high-k dielectric film. The heat treatment is performed at any temperature from about 500 to 1000° C. for any period of time from about 1 to 100 seconds.Type: GrantFiled: June 12, 2008Date of Patent: October 26, 2010Assignee: Tokyo Electron LimitedInventors: Wenwu Wang, Wataru Mizubayashi, Koji Akiyama
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Patent number: 7820558Abstract: A film with small hysteresis and high voltage resistance is obtained by reducing the carbon content in a gate insulating film on a SiC substrate. Specifically, the carbon content in the gate insulating film is set to 1×1020 atoms/cm3 or less. For this, using a plasma processing apparatus, a silicon oxide film is formed on the SiC substrate and then the formed silicon oxide film is reformed by exposure to radicals containing nitrogen atoms. Thus, the gate insulating film excellent in electrical properties is obtained.Type: GrantFiled: June 21, 2007Date of Patent: October 26, 2010Assignees: Tohoku University, Foundation for Advancement of International ScienceInventors: Tadahiro Ohmi, Akinobu Teramoto, Koutaro Tanaka
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Patent number: 7816242Abstract: A semiconductor device includes a plate of semiconductor layer, an insulator layer formed on the plate of semiconductor layer and brought into contact with the plate of semiconductor layer by at least two adjacent faces, a thickness of the insulator layer in the vicinity of a boundary line between the two adjacent faces being larger than that of the insulator layer in a region other than the vicinity of the boundary line, and a band of conductor layer formed facing a middle portion of the plate-like semiconductor layer via the insulator layer.Type: GrantFiled: October 21, 2008Date of Patent: October 19, 2010Assignee: Kabushiki Kaisha ToshibaInventor: Mizuki Ono
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Publication number: 20100258881Abstract: The present invention, in one embodiment, provides a method of forming a semiconductor device that includes providing a substrate including a first conductivity type region and a second conductivity type region; forming a gate stack including a gate dielectric atop the first conductivity type region and the second conductivity type region of the substrate and a first metal gate conductor overlying the high-k gate dielectric; removing a portion of the first metal gate conductor that is present in the first conductivity type region to expose the gate dielectric present in the first conductivity type region; applying a nitrogen based plasma to the substrate, wherein the nitrogen based plasma nitrides the gate dielectric that is present in the first conductivity type region and nitrides the first metal gate conductor that is present in the second conductivity type region; and forming a second metal gate conductor overlying at least the gate dielectric that is present in the first conductivity type region.Type: ApplicationFiled: April 14, 2009Publication date: October 14, 2010Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Michael P. Chudzik, Wiliam K. Henson, Rashmi Jha, Yue Liang, Ravikumar Ramachandran, Richard S. Wise
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Patent number: 7812411Abstract: The present invention provides a high-k gate dielectric/metal gate MOSFET that has a reduced parasitic capacitance. The inventive structure includes at least one metal oxide semiconductor field effect transistor (MOSFET) 100 located on a surface of a semiconductor substrate 12. The least one MOSFET 100 includes a gate stack including, from bottom to top, a high-k gate dielectric 28 and a metal-containing gate conductor 30. The metal-containing gate conductor 30 has gate corners 31 located at a base segment of the metal-containing gate conductor. Moreover, the metal-containing gate conductor 30 has vertically sidewalls 102A and 102B devoid of the high-k gate dielectric 28 except at the gate corners 31. A gate dielectric 18 laterally abuts the high-k gate dielectric 28 present at the gate corners 31 and a gate spacer 36 laterally abuts the metal-containing gate conductor 30.Type: GrantFiled: September 4, 2009Date of Patent: October 12, 2010Assignee: International Business Machines CorporationInventor: Kangguo Cheng
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Patent number: 7812412Abstract: According to the present invention, a semiconductor device having a field effect transistor is provided. The field effect transistor comprises a gate insulating film 2 formed on a semiconductor layer 1 and a gate electrode 5 formed on the gate insulating film 2. The gate insulating film 2 has a silicon oxide film including a metal element 4 and nitrogen 3, and characteristics of the silicon oxide film are modified by adding the metal element 4 and nitrogen 3. Respective concentration distributions of the metal element 4 and nitrogen 3 in the gate insulating film 2 have maximum values on an interface side between the gate insulating film 2 and the gate electrode 5, and gradually decrease toward the semiconductor layer 1.Type: GrantFiled: September 21, 2006Date of Patent: October 12, 2010Assignee: NEC CorporationInventors: Kouji Watanabe, Nobuyuki Ikarashi, Kouji Masuzaki
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Patent number: 7812410Abstract: A microelectronic device, including at least one transistor including: on a substrate, a semiconductor zone with a channel zone covered with a gate dielectric zone, a mobile gate, suspended above the gate dielectric zone and separated from the gate dielectric zone by an empty space, which the gate is located at an adjustable distance from the gate dielectric zone, and a piezoelectric actuation device including a stack formed by at least one layer of piezoelectric material resting on a first biasing electrode, and a second biasing electrode resting on the piezoelectric material layer, wherein the gate is attached to the first biasing electrode and is in contact with the first biasing electrode, and the piezoelectric actuation device is configured to move the gate with respect to the channel zone.Type: GrantFiled: July 7, 2008Date of Patent: October 12, 2010Assignee: Commissariat a l'Energie AtomiqueInventors: Michael Collonge, Maud Vinet, Olivier Thomas
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Publication number: 20100244156Abstract: Methods for protecting gate stacks during fabrication of semiconductor devices and semiconductor devices fabricated from such methods are provided. In an embodiment, a method for fabricating a semiconductor device comprises forming a gate stack comprising a first gate stack-forming layer overlying a semiconductor substrate and forming first sidewall spacers about sidewalls of the gate stack. After the step of forming the first sidewall spacers, a portion of the first gate stack-forming layer is exposed. The exposed portion is anisotropically etched using the gate stack and the first sidewall spacers as an etch mask. Second sidewall spacers are formed adjacent the first sidewall spacers after the step of anisotropically etching.Type: ApplicationFiled: June 14, 2010Publication date: September 30, 2010Applicant: GLOBALFOUNDRIES INC.Inventors: Rohit Pal, Man Fai Ng, David Brown
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Publication number: 20100244155Abstract: In sophisticated transistor elements including a high-k gate metal stack, the integrity of the sensitive gate materials may be ensured by a spacer element that may be concurrently used as an offset spacer for defining a lateral offset of a strain-inducing semiconductor alloy. The cap material of the sophisticated gate stack may be removed without compromising integrity of the offset spacer by providing a sacrificial spacer element. Consequently, an efficient strain-inducing mechanism may be obtained in combination with the provision of a sophisticated gate stack with the required material integrity, while reducing overall process complexity compared to conventional strategies.Type: ApplicationFiled: March 29, 2010Publication date: September 30, 2010Inventors: Richard Carter, Sven Beyer, Martin Trentzsch
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Patent number: 7804145Abstract: It is made possible to provide a semiconductor device that has the effective work function of the connected metal optimized at the interface between a semiconductor and the metal. A semiconductor device includes: a semiconductor film; an oxide film formed on the semiconductor film, the oxide film including at least one of Hf and Zr, and at least one element selected from the group consisting of V, Cr, Mn, Nb, Mo, Tc, W, and Re being added to the oxide film; and a metal film formed on the oxide film.Type: GrantFiled: February 19, 2009Date of Patent: September 28, 2010Assignee: Kabushiki Kaisha ToshibaInventors: Tatsuo Shimizu, Masato Koyama
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Patent number: 7804144Abstract: A gate oxide and method of fabricating a gate oxide that produces a more reliable and thinner equivalent oxide thickness than conventional SiO2 gate oxides are provided. Gate oxides formed from alloys such as cobalt-titanium are thermodynamically stable such that the gate oxides formed will have minimal reactions with a silicon substrate or other structures during any later high temperature processing stages. The process shown is performed at lower temperatures than the prior art, which inhibits unwanted species migration and unwanted reactions with the silicon substrate or other structures. Using a thermal evaporation technique to deposit the layer to be oxidized, the underlying substrate surface smoothness is preserved, thus providing improved and more consistent electrical properties in the resulting gate oxide.Type: GrantFiled: July 21, 2008Date of Patent: September 28, 2010Assignee: Micron Technology, Inc.Inventors: Kie Y. Ahn, Leonard Forbes
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Patent number: 7804130Abstract: Forming a high-?/metal gate field effect transistor using a gate last process in which the channel region has a curved profile thus increasing the effective channel length improves the short channel effect. During the high-?/metal gate process, after the sacrificial materials between the sidewall spacers are removed, the exposed semiconductor substrate surface at the bottom of the gate trench cavity is etched to form a curved recess. Subsequent deposition of high-? gate dielectric layer and gate electrode metal into the gate trench cavity completes the high-?/metal gate field effect transistor having a curved channel region that has a longer effective channel length.Type: GrantFiled: August 26, 2008Date of Patent: September 28, 2010Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventor: Ka-Hing Fung
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Publication number: 20100237403Abstract: Atomic layer deposition (ALD) can be used to form a dielectric layer of zirconium aluminum oxynitride (ZrAlON) for use in a variety of electronic devices. Forming the dielectric layer may include depositing zirconium oxide using atomic layer deposition and precursor chemicals, followed by depositing aluminum nitride using precursor chemicals, and repeating. The dielectric layer may be used as the gate insulator of a MOSFET, a capacitor dielectric, and a tunnel gate insulator in flash memories.Type: ApplicationFiled: May 28, 2010Publication date: September 23, 2010Inventors: Kie Y. Ahn, Leonard Forbes
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Patent number: 7800164Abstract: A method of forming a semiconductor device includes forming a first dielectric layer over a semiconductor substrate, forming a plurality of discrete storage elements over the first dielectric layer, thermally oxidizing the plurality of discrete storage elements to form a second dielectrics over the plurality of discrete storage elements, and forming a gate electrode over the second dielectric layer, wherein a significant portion of the gate electrode is between pairs of the plurality of discrete storage elements. In one embodiment, portions of the gate electrode is in the spaces between the discrete storage elements and extends to more than half of the depth of the spaces.Type: GrantFiled: March 4, 2009Date of Patent: September 21, 2010Assignee: Freescale Semiconductor, Inc.Inventors: Ramachandran Muralidhar, Rajesh A. Rao, Michael A. Sadd, Bruce E. White
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Patent number: 7800133Abstract: In an MIS-type GaN-FET, a base layer made of a conductive nitride including no oxygen, here, TaN, is provided on a surface layer as a nitride semiconductor layer to cover at least an area of a lower face of a gate insulation film made of Ta2O5 under a gate electrode.Type: GrantFiled: February 12, 2008Date of Patent: September 21, 2010Assignee: Fujitsu LimitedInventors: Masahito Kanamura, Toshihide Kikkawa
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Patent number: 7795156Abstract: Disclosed is a producing method of a semiconductor device comprising a step of forming a tunnel insulating film of a flash device comprising a first nitridation step of forming a first silicon oxynitride film by nitriding a silicon oxide film formed on a semiconductor silicon base by one of plasma nitridation and thermal nitridation, the plasma nitridation carrying out nitridation process by using a gas activated by plasma discharging a first gas including a first compound which has at least a nitrogen atom in a chemical formula thereof, and the thermal nitridation carrying out nitridation process using heat by using a second gas including a second compound which has at least a nitrogen atom in a chemical formula thereof, and a second nitridation step of forming a second silicon oxynitride film by nitriding the first silicon oxynitride film by the other of the plasma nitridation and the thermal nitridation.Type: GrantFiled: October 31, 2005Date of Patent: September 14, 2010Assignee: Hitachi Kokusai Electric Inc.Inventors: Tadashi Terasaki, Akito Hirano, Masanori Nakayama, Unryu Ogawa
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Patent number: 7790592Abstract: Disclosed is a method to fabricate a semiconductor device, and a device fabricated in accordance with the method. The method includes providing a substrate comprised of silicon; performing a shallow trench isolation process to delineate nFET and pFET active areas and, within each active area, forming a gate structure over a surface of the substrate, the gate structure comprising in order from the surface of the substrate, a layer of high dielectric constant oxide, a layer comprised of a metal, a layer comprised of amorphous silicon, and a layer comprised of polycrystalline silicon. The layer comprised of amorphous silicon is provided to substantially prevent regrowth of the high dielectric constant oxide layer in a vertical direction during at least a deposition and processing of the polycrystalline silicon layer and/or metal layer.Type: GrantFiled: October 30, 2007Date of Patent: September 7, 2010Assignee: International Business Machines CorporationInventors: Tze-Chiang Chen, Bruce B. Doris, Vijay Narayanan, Vamsi Paruchuri
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Patent number: 7791149Abstract: An integrated circuit including a dielectric layer and a method for manufacturing. One embodiment provides a substrate having a first side and a second side and at least one dielectric layer. The dielectric layer includes a zirconium oxide and at least one dopant selected from the group consisting of hafnium and titanium and having a first side and a second side. The first side of the dielectric layer is arranged at least on a subarea of the first side of the semiconductor substrate.Type: GrantFiled: July 10, 2008Date of Patent: September 7, 2010Assignee: Qimonda AGInventor: Tim Boescke
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Patent number: 7786539Abstract: In order to provide a dielectric film which can avoid both boron leakage and an increase of the leak current, a semiconductor apparatus which has the dielectric film, a production method of the dielectric film and a production method of the semiconductor apparatus, a dielectric film layered product is applied which includes: a semiconductor substrate (2); a first hafnium-containing silicon oxide nitride layer (3a) made from a microcrystalline structure; a second hafnium-containing silicon oxide nitride layer (3b) made from a non-crystalline structure; and a layered film which is made from the first and second hafnium-containing silicon oxide nitride layers that are layered on the semiconductor substrate, and which has a nitrogen ratio of 15-40 atomic percent.Type: GrantFiled: January 11, 2008Date of Patent: August 31, 2010Assignee: Elpida Memory, Inc.Inventors: Takakazu Kiyomura, Takuo Ohashi
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Patent number: 7785996Abstract: A nonvolatile memory device and a method of manufacturing the same are provided. The nonvolatile memory device includes a semiconductor substrate on which a source region, a drain region, and a channel region are formed, a silicon oxide layer formed on the channel region, a transition metal oxide layer having trap particles that trap electrons, formed on the silicon oxide layer, and a gate electrode formed on the transition metal oxide layer.Type: GrantFiled: October 19, 2005Date of Patent: August 31, 2010Assignee: Samsung Electronics Co., Ltd.Inventors: Jung-hyun Lee, Kyu-sik Kim
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Publication number: 20100213553Abstract: Methods for forming a semiconductor device comprising a semiconductor substrate are provided. In accordance with an exemplary embodiment, a method comprises forming a channel layer overlying the semiconductor substrate, forming a channel capping layer having a first surface overlying the channel layer, oxidizing the first surface of the channel capping layer, and depositing a high-k dielectric layer overlying the channel capping layer.Type: ApplicationFiled: February 23, 2009Publication date: August 26, 2010Applicant: ADVANCED MICRO DEVICES, INC.Inventors: Michael HARGROVE, Richard J. CARTER, Ying H. TSANG, George KLUTH, Kisik CHOI
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Publication number: 20100213554Abstract: A gate structure includes a gate disposed on a substrate, a first spacer disposed on the substrate and surrounding the gate and a second spacer disposed on the first spacer and surrounding the gate, the second spacer is lower than the first spacer.Type: ApplicationFiled: February 23, 2009Publication date: August 26, 2010Inventors: I-Chang Wang, Ming-Tsung Chen, Ling-Chun Chou, Po-Chao Tsao, Tsung-Hung Chang, Hui-Ling Chen, Cheng-Yen Wu, Chieh-Te Chen, Shin-Chi Chen
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Patent number: 7781814Abstract: The semiconductor integrated circuit device employs on the same silicon substrate a plurality of kinds of MOS transistors with different magnitudes of tunnel current flowing either between the source and gate or between the drain and gate thereof. These MOS transistors include tunnel-current increased MOS transistors at least one of which is for use in constituting a main circuit of the device. The plurality of kinds of MOS transistors also include tunnel-current reduced or depleted MOS transistors at least one of which is for use with a control circuit. This control circuit is inserted between the main circuit and at least one of the two power supply units.Type: GrantFiled: May 19, 2008Date of Patent: August 24, 2010Assignee: Renesas Technology Corp.Inventors: Nozomu Matsuzaki, Hiroyuki Mizuno, Masashi Horiguchi
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Patent number: 7776732Abstract: A method is disclosed to reduce parasitic capacitance in a metal high dielectric constant (MHK) transistor. The method includes forming a MHK gate stack upon a substrate, the MHK gate stack having a bottom layer of high dielectric constant material, a middle layer of metal, and a top layer of one of amorphous silicon or polycrystalline silicon. The method further forms a depleted sidewall layer on sidewalls of the MHK gate stack so as to overlie the middle layer and the top layer, and not the bottom layer. The depleted sidewall layer is one of amorphous silicon or polycrystalline silicon. The method further forms an offset spacer layer over the depleted sidewall layer and over exposed surfaces of the bottom layer.Type: GrantFiled: September 10, 2007Date of Patent: August 17, 2010Assignee: International Business Machines CorporationInventors: Leland Chang, Isaac Lauer, Renee T. Mo, Jeffrey W. Sleight
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Publication number: 20100200937Abstract: Various techniques for changing the workfunction of the substrate by using a SiGe channel which, in turn, changes the bandgap favorably for a p-type metal oxide semiconductor field effect transistors (pMOSFETs) are disclosed. In the various techniques, a SiGe film that includes a low doped SiGe region above a more highly doped SiGe region to allow the appropriate threshold voltage (Vt) for pMOSFET devices while preventing pitting, roughness and thinning of the SiGe film during subsequent cleans and processing is provided.Type: ApplicationFiled: February 9, 2009Publication date: August 12, 2010Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Stephen W. Bedell, Ashima B. Chakravarti, Michael P. Chudzik, Judson R. Holt, Dominic J. Schepis
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Patent number: 7772671Abstract: A semiconductor device including a semiconductor substrate having on its surface a recess and at least one projection formed in the recess. The projection has a channel region and an element isolating insulating film is formed in the recess. A MIS type semiconductor element is formed on the semiconductor substrate and includes a gate electrode formed on the channel region of the projection via a gate insulating film. Source and drain regions are formed to pinch the channel region of the projection therebetween. A channel region of the MIS type semiconductor element is formed to reach the at least one projection located adjacent to the MIS type semiconductor element in its channel width direction via the recess. A top surface of the at least one projection is located higher than the top surface of the element isolating insulating film by 20 nm or more.Type: GrantFiled: February 8, 2008Date of Patent: August 10, 2010Assignee: Kabushiki Kaisha ToshibaInventors: Kyoichi Suguro, Kiyotaka Miyano, Ichiro Mizushima, Yoshitaka Tsunashima, Takayuki Hiraoka, Yasushi Akasaka, Tsunetoshi Arikado
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Patent number: 7772706Abstract: A spacer is adjacent to a conductive line. Vias that do not completely land on the conductive line land on the spacer and do not punch through into a volume below the spacer.Type: GrantFiled: December 27, 2007Date of Patent: August 10, 2010Assignee: Intel CorporationInventors: Sridhar Balakrishnan, Boyan Boyanov