Abstract: The dopant profile of a transistor may be obtained on the basis of an in situ doped strain-inducing semiconductor alloy wherein a graded dopant concentration may be established along the height direction. Consequently, the semiconductor alloy may be positioned in close proximity to the channel region, thereby enhancing the overall strain-inducing efficiency, while not unduly compromising the finally obtained dopant profile. Furthermore, additional implant species may be incorporated prior to selectively growing the semiconductor alloy, thereby avoiding implantation-induced relaxation of the internal strain.

Abstract: In sophisticated transistor elements, enhanced profile uniformity along the transistor width direction may be accomplished by using a gate material in an amorphous state, thereby reducing channeling effects and line edge roughness. In sophisticated high-k metal gate approaches, an appropriate sequence may be applied to avoid a change of the amorphous state prior to performing the critical implantation processes for forming drain and source extension regions and halo regions.

Abstract: The abrupt metal-insulator transition device includes: an abrupt metal insulator transition material layer including an energy gap of less than or equal to 2 eV and holes within a hole level; and two electrodes contacting the abrupt metal-insulator transition material layer. Here, each of the two electrodes is formed by thermally treating a stack layer of a first layer formed on the abrupt metal-insulator transition material layer and comprising Ni or Cr, a second layer formed on the first layer and comprising In, a third layer formed on the second layer and comprising Mo or W, and a fourth layer formed on the third layer and comprising Au.

Abstract: Embodiments of the invention generally relate to transistors with high-k dielectric spacer liner to mitigate lateral oxide encroachment. In this regard a semiconductor device is introduced having a substrate, a high-k gate dielectric layer on the substrate, a metal gate electrode on the high-k gate dielectric layer, and a high-k dielectric layer on either side of and adjacent to the metal gate electrode and high-k gate dielectric layer, extending a distance away from the metal gate electrode and high-k gate dielectric layer on the substrate. Other embodiments are also disclosed and claimed.

Abstract: A low resistance contact is formed to a metal gate or a transistor including a High-K gate dielectric in a high integration density integrated circuit by applying a liner over a gate stack, applying a fill material between the gate stacks, planarizing the fill material to support high-resolution lithography, etching the fill material and the liner selectively to each other to form vias and filling the vias with a metal, metal alloy or conductive metal compound such as titanium nitride.

Abstract: A semiconductor device includes a Si crystal having a crystal surface in the vicinity of a (111) surface, and an insulation film formed on said crystal surface, at least a part of said insulation film comprising a Si oxide film containing Kr or a Si nitride film containing Ar or Kr.

Abstract: A semiconductor device 100 includes a silicon substrate 102, an N-type MOSFET 118 including a first high dielectric constant film 111 and a polycrystalline silicon film 114 on the silicon substrate 102, and a P-type MOSFET 120 including a second high dielectric constant film 12 and a polycrystalline silicon film 114 juxtaposed to N-type MOSFET 118 on the silicon substrate 102. The second high dielectric constant film 112 is formed to have the film thickness thinner than the film thickness of the first high dielectric constant film 111. The first high dielectric constant film 111 and the second high dielectric constant film 112 contains one or more element(s) selected from Hf and Zr.

Abstract: Semiconductor devices and methods of manufacture thereof are disclosed. A preferred embodiment comprises a method of forming a barrier layer. The method of forming the barrier layer includes providing a workpiece, forming a first material layer over the workpiece, the first material layer comprising a nitride-based metal compound. A second material layer is formed over the first material layer. The second material layer comprises Ta or Ti. The barrier layer comprises the first material layer and at least the second material layer.

Abstract: Doped aluminum oxide layers having a porous aluminum oxide layer and methods of their fabrication. The porous aluminum oxide layer may be formed by evaporation physical vapor deposition techniques to facilitate formation of a high-purity aluminum oxide layer. A dopant material is embedded in the pores of the porous aluminum oxide layer and subsequently converted to a dielectric form. The degree of porosity of the porous aluminum oxide layer may be controlled during formation to facilitate control of the level of doping of the doped aluminum oxide layer. Such doped aluminum oxide layers are useful as gate dielectric layers, intergate dielectric layers and capacitor dielectric layers in various integrated circuit devices.

Abstract: A semiconductor device includes: a semiconductor substrate; a source region and a drain region formed in the upper part of the semiconductor substrate so as to be spaced; a channel region formed in a part of the semiconductor substrate between the source region and the drain region; a first dielectric film formed on the channel region of the semiconductor substrate; a second dielectric film formed on the first dielectric film and having a higher permittivity than the first dielectric film; a third dielectric film formed on at least an end surface of the second dielectric film near the drain region out of end surfaces of the second dielectric film near the source and drain regions; and a gate electrode formed on the second dielectric film and the third dielectric film.

Abstract: Semiconductor structures, such as, for example, field effect transistors (FETs) and/or metal-oxide-semiconductor capacitor (MOSCAPs), are provided in which the workfunction of a conductive electrode stack is changed by introducing metal impurities into a metal-containing material layer which, together with a conductive electrode, is present in the electrode stack. The choice of metal impurities depends on whether the electrode is to have an n-type workfunction or a p-type workfunction. The present invention also provides a method of fabricating such semiconductor structures.

Abstract: Methods of forming a resistive memory device include forming an insulation layer on a semiconductor substrate including a conductive pattern, forming a contact hole in the insulation layer to expose the conductive pattern, forming a lower electrode in the contact hole, forming a variable resistive oxide layer in the contact hole on the lower electrode, forming a middle electrode in the contact hole on the variable resistive oxide layer, forming a buffer oxide layer on the middle electrode and the insulation layer, and forming an upper electrode on the buffer oxide layer. Related resistive memory devices are also disclosed.

Abstract: A metal oxide semiconductor (MOS) transistor with a Y structure metal gate is provided. The MOS transistor includes a substrate, a Y structure metal gate positioned on the substrate, two doping regions disposed in the substrate on two sides of the Y structure metal structure, a spacer, an insulating layer positioned outside the spacer, a dielectric layer positioned outside the insulating layer and a bevel edge covering the spacer. The spacer has a vertical sidewall, and the vertical sidewall surrounds a recess. A part of the Y structure metal gate is disposed in the recess, and a part of the Y structure metal gate is positioned on the bevel edge.

Abstract: A method of manufacturing a semiconductor device includes forming a semiconductor layer containing a semiconductor material having a first oxide-generating Gibbs free energy required to become an oxide; forming a first material for a gate insulator on the semiconductor layer, said first material containing an element having a second oxide-generating Gibbs free energy required to become an oxide and becoming insulative when the element is oxidized or nitrided; and annealing the first material in an atmosphere containing hydrogen atoms, or heavy hydrogen atoms, and oxygen atoms in a temperature range where the first oxide-generating Gibbs free energy is equal to or higher than the second oxide-generating Gibbs free energy.

Abstract: A semiconductor device includes a semiconductor substrate, a gate insulating film formed on a semiconductor substrate and containing a first element and a second element, and a gate electrode formed on the gate insulating film. The gate insulating film has a higher content of the first element in a portion thereof closer to the semiconductor substrate than in a portion thereof closer to the gate electrode, and a higher content of the second element in a portion thereof closer to the gate electrode than in a portion thereof closer to the semiconductor substrate.

Abstract: During a replacement gate approach, the inverse tapering of the opening obtained after removal of the polysilicon material may be reduced by depositing a spacer layer and forming corresponding spacer elements on inner sidewalls of the opening. Consequently, the metal-containing gate electrode material and the high-k dielectric material may be deposited with enhanced reliability.

Abstract: A method is provided for additionally oxidizing a thin-film oxide. The method includes: providing a substrate; depositing an MyOx (M oxide) layer overlying the substrate, where M is a solid element having an oxidation state in a range of +2 to +5; treating the MyOx layer to a high density plasma (HDP) source; and, forming an MyOk layer in response to the HDP source, where k>x. In one aspect, the method further includes decreasing the concentration of oxide charge in response to forming the MyOk layer. In another aspect, the MyOx layer is deposited with an impurity N, and the method further includes creating volatile N oxides in response to forming the MyOk layer. For example, the impurity N may be carbon and the method creates a volatile carbon oxide.

Abstract: A method of preventing surface decomposition of a III-V compound semiconductor is provided. The method includes forming a silicon film having a thickness from 10 ? to 400 ? on a surface of an III-V compound semiconductor. After forming the silicon film onto the surface of the III-V compound semiconductor, a high performance semiconductor device including, for example, a MOSFET, can be formed on the capped/passivated III-V compound semiconductor. During the MOSFET fabrication, a high k dielectric can be formed on the capped/passivated III-V compound semiconductor and thereafter, activated source and drain regions can be formed into the III-V compound semiconductor.

Abstract: A ruthenium layer for a dielectric layer containing a lanthanide layer and a method of fabricating such a combination of ruthenium layer and dielectric layer produce a reliable structure for use in a variety of electronic devices. A ruthenium or a conductive ruthenium oxide layer may be formed on the lanthanide oxide dielectric layer.

Abstract: The present invention discloses a suspended nanochannel transistor structure and a method for fabricating the same. The transistor structure of the present invention comprises a substrate; a side gate formed on the substrate; a dielectric layer covering the substrate and the side gate; a suspended nanochannel formed beside the lateral of the side gate with an air gap existing between the suspended nanochannel and the dielectric layer; a source and a drain formed over the dielectric layer and respectively arranged at two ends of the suspended nanochannel. The electrostatic force of the side gate attracts or repels the suspended nanochannel and thus fast varies the equivalent thickness of the side-gate dielectric layer. Thereby, the on/off state of the element is rapidly switched, or the initial voltage of the channel is altered.

Abstract: The use of a conductive bidimensional perovskite as an interface between a silicon, metal, or amorphous oxide substrate and an insulating perovskite deposited by epitaxy, as well as an integrated circuit and its manufacturing process comprising a layer of an insulating perovskite deposited by epitaxy to form the dielectric of capacitive elements having at least an electrode formed of a conductive bidimensional perovskite forming an interface between said dielectric and an underlying silicon, metal, or amorphous oxide substrate.

Abstract: A method of manufacturing a semiconductor device, comprises: forming a high dielectric gate insulating film in an nMIS formation region and a pMIS formation region of a semiconductor substrate; forming a first metal film on the high dielectric gate insulating film, the first metal film; removing the first metal film in the nMIS formation region; forming a second metal film on the high dielectric gate insulating film of the nMIS formation region and on the first metal film of the pMIS formation region; and processing the first metal film and the second metal film. The high dielectric gate insulating film has a dielectric constant higher than a dielectric constant of silicon oxide. The first metal film does not contain silicon and germanium. The second metal film contains at least one of silicon and germanium.

Abstract: A transistor structure of an electronic device can include a gate dielectric layer and a gate electrode. The gate electrode can have a surface portion between the gate dielectric layer and the rest of the gate electrode. The surface portion can be formed such that another portion of the gate electrode primarily sets the effective work function in the finished transistor structure.

Abstract: The present disclosure provides a method of fabricating a semiconductor device that includes forming a high-k dielectric over a substrate, forming a first metal layer over the high-k dielectric, forming a second metal layer over the first metal layer, forming a first silicon layer over the second metal layer, implanting a plurality of ions into the first silicon layer and the second metal layer overlying a first region of the substrate, forming a second silicon layer over the first silicon layer, patterning a first gate structure over the first region and a second gate structure over a second region, performing an annealing process that causes the second metal layer to react with the first silicon layer to form a silicide layer in the first and second gate structures, respectively, and driving the ions toward an interface of the first metal layer and the high-k dielectric in the first gate structure.

Abstract: A semiconductor device and associated methods, the semiconductor device including a semiconductor substrate with a first well region, a first gate electrode disposed on the first well region, and a first N-type capping pattern, a first P-type capping pattern, and a first gate dielectric pattern disposed between the first well region and the first gate electrode.

Abstract: Provided are a semiconductor device and a method for fabricating the same. The semiconductor device can include a transistor structure, including a gate dielectric on a substrate, a gate electrode on the gate dielectric, a spacer at sidewalls of the gate electrode, and source/drain regions in the substrate; and an interlayer dielectric on the transistor structure where an air gap is provided in a region between the spacer, the interlayer dielectric, and the source/drain region of the substrate.

Abstract: A method for fabricating a TFT on a substrate includes forming a gate electrode; forming a semiconductor layer insulated from the gate electrode and partially overlapped with the gate electrode; forming a gate insulating layer between the gate electrode and the semiconductor layer, the gate insulating layer including a sol-gel compound; and forming source and drain electrodes at both sides of the semiconductor layer.

Abstract: A semiconductor device having a high-K gate dielectric layer includes a p-type well that is formed in an upper layer of a silicon substrate. Arsenic ions are implanted into an extreme surface layer of the p-type well and a heat treatment is performed to form a p-type low-concentration layer. A HfAlOx film and a polycrystalline silicon layer are laminated on the substrate. A gate electrode is formed by patterning the polycrystalline silicon layer. After a n-type extension region is formed by implanting arsenic ions by using the gate electrode as a mask, sidewall spacers are formed on sides of the gate electrode. Arsenic ions are implanted by using the sidewall spacers and the gate electrode as masks, whereby n-type source/drain regions are formed.

Abstract: The present disclosure provides a semiconductor device. The semiconductor device includes a semiconductor substrate having a source region and a drain region, defining a first dimension from the source to drain; and a gate stack disposed on the semiconductor substrate and partially interposed between the source region and the drain region. The gate stack includes a high k dielectric layer disposed on the semiconductor substrate; a first metal feature disposed on the high k dielectric layer, the first metal gate feature having a first work function and defining a second dimension parallel with the first dimension; and a second metal feature having a second work function different from the first work function and defining a third dimension parallel with the first dimension, the third dimension being less than the second dimension.

Abstract: A method is provided for fabricating a semiconductor device. The method includes providing a substrate including a dummy gate structure formed thereon, removing the dummy gate structure to form a trench, forming a first metal layer over the substrate to fill a portion of the trench, forming a protection layer in a remaining portion of the trench, removing a unprotected portion of the first metal layer, removing the protection layer from the trench, and forming a second metal layer over the substrate to fill the trench.

Abstract: The task of the present invention is to enable formation of a gate insulating film structure having a good-quality interface between a silicon oxide film and silicon in an interface between a high dielectric constant thin film and a silicon substrate to provide a semiconductor device and a semiconductor manufacturing method which are capable of improving interface electrical characteristics, which has been a longstanding task in practical use of a high dielectric constant insulating film. A metal layer deposition process and a heat treatment process which supply metal elements constituting a high dielectric constant film on a surface of a base silicon oxide film 103 allow the metal elements to be diffused into the base silicon oxide film 103 to thereby form an insulating film structure 105 as a gate insulating film, after forming the base silicon oxide film 103 on a surface of a silicon substrate 101.

Abstract: A method for fabricating a thin film transistor (TFT) on a substrate includes forming a gate electrode; forming a semiconductor layer being insulated from the gate electrode and partially overlapped with the gate electrode; sequentially forming first and second gate insulating layers between the gate electrode and the semiconductor layer, wherein the first gate insulating layer is formed of a material different from the second gate insulating layer and at least one of the first and second gate insulating layers includes a sol-compound; and forming source and drain electrodes at both sides of the semiconductor layer.

Abstract: A semiconductor device in which selectivity in epitaxial growth is improved. There is provided a semiconductor device comprising a gate electrode formed over an Si substrate, which is a semiconductor substrate, with a gate insulating film therebetween and an insulating layer formed over sides of the gate electrode and containing a halogen element. With this semiconductor device, a silicon nitride film which contains the halogen element is formed over the sides of the gate electrode when an SiGe layer is formed over the Si substrate. Therefore, the SiGe layer epitaxial-grows over the Si substrate with high selectivity. As a result, an OFF-state leakage current which flows between, for example, the gate electrode and source/drain regions is suppressed and a manufacturing process suitable for actual mass production is established.

Abstract: A method for fabricating metal gate transistor is disclosed. First, a substrate having a first transistor region and a second transistor region is provided. Next, a stacked film is formed on the substrate, in which the stacked film includes at least one high-k dielectric layer and a first metal layer. The stacked film is patterned to form a plurality of gates in the first transistor region and the second transistor region, a dielectric layer is formed on the gates, and a portion of the dielectric layer is planarized until reaching the top of each gates. The first metal layer is removed from the gate of the second transistor region, and a second metal layer is formed over the surface of the dielectric layer and each gate for forming a plurality of metal gates in the first transistor region and the second transistor region.

Abstract: An integrated electronic circuit has a thin layer portion based on hafnium oxide. This portion additionally contains magnesium atoms, so that the portion is in the form of a hafnium-and-magnesium mixed oxide. Such a portion has a high dielectric constant and a very low leakage current. It is particularly suitable for forming a part of a gate insulation layer of a MOS transistor or a part of a MIM capacitor dielectric.

Abstract: Embodiments relate to a method for forming a gate insulating layer, which may include forming a device isolation layer being divided into a device active region and a device isolation region, growing a first oxide layer at an entire surface of the semiconductor substrate as a gate insulating layer, performing a first annealing process to form a diffusion barrier layer an interface between the first oxide layer and the device active region, etching and removing a first oxide layer and a diffusion barrier layer of the core power source wiring region by masking the input/output power source wiring region, growing a second oxide layer on the core power source wiring region, and performing a second annealing process to form an NO gate oxide layer on which an N-rich oxide layer at an interface of the core power source wiring region.

Abstract: A semiconductor device is provided which includes a semiconductor substrate, a transistor formed on the substrate, the transistor having a gate stack including a metal gate and high-k gate dielectric and a dual first contact formed on the substrate. The dual first contact includes a first contact feature, a second contact feature overlying the first contact feature, and a metal barrier formed on sidewalls and bottom of the second contact feature, the metal barrier layer coupling the first contact feature to the second contact feature.

Abstract: A PMOS transistor is disclosed which includes a nitrogen containing barrier to oxygen diffusion between a gate dielectric layer and a metal gate in the PMOS transistor, in combination with a low oxygen region of the metal gate in direct contact with the nitrogen containing barrier and an oxygen rich region of the metal gate above the low oxygen content metal region. The nitrogen containing barrier may be formed by depositing nitrogen containing barrier material on the gate dielectric layer or by nitridating a top region of the gate dielectric layer. The oxygen rich region of the metal gate may be formed by depositing oxidized metal on the low oxygen region of the metal gate or by oxidizing a top region of the low oxygen region of the metal gate.

Abstract: In a MIS transistor of which gate length is 10 nm or less, a gate insulator comprising a silicon oxide film formed on a silicon substrate and a high-k film formed on the silicon oxide film has a nitrided region including more nitrogen at the lateral side than at the central side in the gate-length direction, and including more nitrogen at the upper side than at the lower side in the film thickness direction. The reliability and characteristics of a MIS transistor using a gate insulator including a high-k (high dielectric constant) film is enhanced.

Abstract: The present disclosure provides a semiconductor device that includes a semiconductor substrate, a transistor formed in the substrate, the transistor including a high-k gate dielectric formed over the substrate, the high-k gate dielectric having a first length measured from one sidewall to the other sidewall of the high-k gate dielectric, and a metal gate formed over the high-k gate dielectric, the metal gate having a second length measured from one sidewall to the other sidewall of the metal gate, the second length being smaller than the first length.

Abstract: A multilayered gate stack having improved reliability (i.e., low charge trapping and gate leakage degradation) is provided. The inventive multilayered gate stack includes, from bottom to top, a metal nitrogen-containing layer located on a surface of a high-k gate dielectric and Si-containing conductor located directly on a surface of the metal nitrogen-containing layer. The improved reliability is achieved by utilizing a metal nitrogen-containing layer having a compositional ratio of metal to nitrogen of less than 1.1. The inventive gate stack can be useful as an element of a complementary metal oxide semiconductor (CMOS). The present invention also provides a method of fabricating such a gate stack in which the process conditions of a sputtering process are varied to control the ratio of metal and nitrogen within the sputter deposited layer.

Abstract: Broadly speaking, methods and an apparatus are provided for removing an inorganic material from a substrate. More specifically, the methods provide for removing the inorganic material from the substrate through exposure to a high density plasma generated using an inductively coupled etching apparatus. The high density plasma is set and controlled to isotropically contact particular regions of the inorganic material to allow for trimming and control of a critical dimension associated with the inorganic material.

Abstract: Disclosed are embodiments of field effect transistors (FETs) having suppressed sub-threshold corner leakage, as a function of channel material band-edge modulation. Specifically, the FET channel region is formed with different materials at the edges as compared to the center. Different materials with different band structures and specific locations of those materials are selected in order to effectively raise the threshold voltage (Vt) at the edges of the channel region relative to the Vt at the center of the channel region and, thereby to suppress of sub-threshold corner leakage. Also disclosed are design structures for such FETs and method embodiments for forming such FETs.

Abstract: In a P-channel power MIS field effect transistor formed on a silicon surface having substantially a (110) plane, a gate insulation film is used which provides a gate-to-source breakdown voltage of 10 V or more, and planarizes the silicon surface, or contains Kr, Ar, or Xe.

Abstract: Disclosed herein is a device comprising a source region, a drain region and a gate layer; the source region, the drain region and the gate layer being disposed on a semiconductor host; the gate layer being disposed between source and drain regions; the gate layer comprising a first gate-insulator layer; a gate layer comprising carbon nanotubes and/or graphene. Disclosed herein too is a method comprising disposing a source region, a drain region and a gate layer on a semiconductor host; the gate layer being disposed between the source region and the drain region; the gate layer comprising carbon nanotubes and/or graphene.

Abstract: By providing a gate dielectric material of increased thickness for P-channel transistors compared to N-channel transistors, degradation mechanisms, such as negative bias threshold voltage instability, hot carrier injection and the like, may be reduced. Due to the enhanced reliability of the P-channel transistors, overall production yield for a specified quality category may be increased, due to the possibility of selecting narrower guard bands for the semiconductor device under consideration.

Abstract: In a process of forming MISFETs that have gate insulating films that are mutually different in thickness on the same substrate, the formation of an undesirable natural oxide film at the interface between the semiconductor substrate and the gate insulating film is suppressed. A gate insulating film of MISFETs constituting an internal circuit is comprised of a silicon oxynitride film. Another gate insulating film of MISFETs constituting an I/O circuit is comprised of a laminated silicon oxynitride film and a high dielectric film. A process of forming the two types of gate insulating films on the substrate is continuously carried out in a treatment apparatus of a multi-chamber system. Accordingly, the substrate will not be exposed to air. Therefore, it is possible to suppress the inclusion of undesirable foreign matter and the formation of a natural oxide film at the interface between the substrate and the gate insulating films.

Abstract: A semiconductor apparatus wherein a device formed on a semiconductor substrate comprises a gate insulating film including a high dielectric constant film formed on the substrate and an anti-reaction film formed on the high dielectric constant film, and a gate electrode formed on the anti-reaction film, the high dielectric constant film comprises a film containing at least one of Hf and Zr, and Si and O, or a film containing at least one of Hf and Zr, and Si, O and N, the anti-reaction film comprises an SiO2 film, a film containing SiO2 as a main component and at least one of Hf and Zr, a film containing SiO2 as a main component and N, a film containing SiO2 as a main component, Hf and N, a film containing SiO2 as a main component, Zr and N, or a film containing SiO2 as a main component, Hf, Zr and N.

Abstract: Disclosed are a semiconductor device with dual gate dielectric layers and a method for fabricating the same. The semiconductor device includes: a silicon substrate divided into a cell region where NMOS transistors are formed and a peripheral region where NMOS and PMOS transistors are formed; a targeted silicon oxide layer formed on the silicon substrate in the cell region; an oxynitride layer formed on the silicon substrate in the peripheral region; a first gate structure formed in the cell region; a second gate structure formed on the oxynitride layer in an NMOS region of the peripheral region; and a third gate structure formed on the oxynitride layer in a PMOS region of the peripheral region.

Abstract: A semiconductor device manufacturing method includes the steps of: successively forming, on a semiconductor substrate, a gate insulating film and first and second dummy sections stacked in this order; forming a notch section by processing the gate insulating film and the first and second dummy gate sections into a previously set pattern and making the first dummy gate section move back in the gate length direction relative to the second dummy gate section; forming a side wall of an insulating material in a side part of each of the gate insulating film and the first and second dummy gate sections and embedding the notch section therewith; removing the first and second dummy gate sections to leave the gate insulating film and the notch section in the bottom of a removed portion; and forming a gate electrode made of a conductive material by embedding the removed portion with the conductive material.