Abstract: A storage element includes a first ferromagnetic layer; a second ferromagnetic layer; a nonmagnetic layer interposed between the first ferromagnetic layer and the second ferromagnetic layer in a first direction; a first wiring that extends in a second direction different from the first direction and together with the nonmagnetic layer sandwiches the first ferromagnetic layer in the first direction; and an electrode that together with the nonmagnetic layer sandwiches the second ferromagnetic layer in at least a part in the first direction, wherein the electrode is in contact with at least a part of a lateral side surface of the second ferromagnetic layer.

Abstract: Disclosed are a synthetic antiferromagnetic material using the Ruderman-Kittel-Kasuya-Yosida (RKKY) interaction and a multibit memory using the synthetic antiferromagnetic material that is formed. The synthetic antiferromagnetic material has a non-magnetic metal layer as an RKKY inducing layer in the center, interaction between upper and lower ferromagnetic layers is imparted according to the thickness of the RKKY inducing layer, and the magnetization of an anti-parallel state is maximized therebetween. When such synthetic antiferromagnetic materials are cumulatively stacked and tunnel barrier layers are provided therebetween, multiple bits can be stored. Namely, data may be stored by supplying a program current in parallel to the surface of the RKKY inducing layer, and a resistance state may be checked by supplying current in a vertical direction to the surface of the RKKY inducing layer.

Abstract: A magnetoresistive random access memory (MRAM) structure includes a magnetic tunnel junction (MTJ), and a top electrode which contacts an end of the MTJ. The top electrode includes a top electrode upper portion and a top electrode lower portion. The width of the top electrode upper portion is larger than the width of the top electrode lower portion. A bottom electrode contacts another end of the MTJ. The top electrode, the MTJ and the bottom electrode form an MRAM.

Abstract: The present disclosure provides a semiconductor structure, including an Nth metal layer, a bottom electrode over the Nth metal layer, a magnetic tunneling junction (MTJ) over the bottom electrode, a top electrode over the MTJ, and an (N+M)th metal layer over the Nth metal layer. N and M are positive integers. The (N+M)th metal layer surrounds a portion of a sidewall of the top electrode. A manufacturing method of forming the semiconductor structure is also provided.

Abstract: Magnetic locators and uses of such locators for detection of buried utilities are disclosed. Outputs provided from two or more three three-axis magnetic sensors based on magnetic field signals sensed at single points in space in three axes may be used to determine information about the buried utilities including position and/or depth of the buried utilities relative to the locator.

Abstract: Some embodiments relate to a magnetoresistive random-access memory (MRAM) cell. The cell includes a bottom electrode having a central bottom electrode portion surrounded by a peripheral bottom electrode portion. Step regions of the conductive bottom electrode couple the central and peripheral bottom electrode portions to one another such that an upper surface of the central portion is recessed relative to an upper surface of the peripheral portion. A magnetic tunneling junction (MTJ) has MTJ outer sidewalls which are disposed over the bottom central electrode portion and which are arranged between the step regions. A top electrode is disposed over an upper surface of the MTJ. Other devices and methods are also disclosed.

Abstract: Example embodiments relate to methods and apparatuses for aligning a probe for scanning probe microscopy (SPM) to the tip of a pointed sample. One embodiments includes a method for aligning an SPM probe to an apex area of a free-standing tip of a pointed sample. The method includes providing an SPM apparatus that includes the SPM probe; a sample holder; a drive mechanism; and detection, control, and representation tools for acquiring and representing an image of a surface scanned by the SPM probe. The method also includes mounting the sample on the sample holder. Further, the method includes positioning the probe tip of the SPM, determining a 2-dimensional area that includes the pointed sample, performing an SPM acquisition scan, evaluating and acquired image, and placing the SPM probe in a position where it is aligned with an apex area of the free-standing tip of the pointed sample.

Abstract: A method for fabricating semiconductor device includes the steps of: forming a magnetic tunneling junction (MTJ) on a substrate and a top electrode on the MTJ; forming a first inter-metal dielectric (IMD) layer around the MTJ and the top electrode; forming a stop layer on the first IMD layer; forming a second IMD layer on the stop layer; performing a first etching process to remove the second IMD layer and the stop layer; performing a second etching process to remove part of the top electrode; and forming a metal interconnection to connect to the top electrode.

Abstract: A non-local spin valve (NLSV) sensor includes a bearing surface and a detector located proximate to the bearing surface. The NLSV sensor also includes a channel layer located behind the detector relative to the bearing surface, and in a substantially same plane as the detector. The channel layer has a front end that is proximate to the detector and a rear end that is distal to the detector. The NLSV sensor further includes first and second spin injectors, with the first spin injector located proximate to the rear end of the channel layer and positioned above the channel layer, and the second spin injector located proximate the rear end of the channel layer and positioned below the channel layer.

Abstract: An integrated circuit (IC) device includes a logic portion including logic circuits in multiple vertically stacked metal layers interconnected by one or more via layers, and a memory portion with a plurality of magnetoresistive devices. Each magnetoresistive device is provided in a single metal layer of the multiple vertically stacked metal layers of the IC device.

Abstract: A method for fabricating a semiconductor device may include: forming a gate dielectric material over a substrate; sequentially forming a carbon-undoped polysilicon layer and a carbon-doped polysilicon layer over the gate dielectric material; doping the carbon-doped polysilicon layer with a dopant; forming a columnar crystalline polysilicon layer over the carbon-doped polysilicon layer doped with the dopant; and performing annealing to activate the dopant.

Abstract: In some embodiments, the present application provides a memory device. The memory device includes a chip that includes a magnetic random access memory (MRAM) cell. A magnetic-field-shielding structure comprised of conductive or magnetic material at least partially surrounds the chip. The magnetic-field-shielding structure comprises a sidewall region that laterally surrounds the chip, an upper region extending upward from the sidewall region, and a lower region extending downward from the sidewall region. At least one of the upper region and/or lower region terminate at an opening over the chip.

Abstract: Structures and methods are disclosed for shielding magnetically sensitive components. One structure includes a substrate, a bottom shield deposited on the substrate, a magnetoresistive semiconductor device having a first surface and a second surface opposing the first surface, the first surface of the magnetoresistive semiconductor device deposited on the bottom shield, a top shield deposited on the second surface of the magnetoresistive semiconductor device, the top shield having a window for accessing the magnetoresistive semiconductor device, and a plurality of interconnects that connect the magnetoresistive semiconductor device to a plurality of conductive elements.

Abstract: A current sensor can indirectly measure a sensed current by directly measuring static perturbing AC magnetic fields with magnetoresistance elements, the perturbing magnetic fields generated by perturbing coils. The sensed current can be indirectly measured by modulating or changing sensitivities of the magnetoresistance elements in a way that is directly related to the sensed current.

Abstract: A magnetic sensor that ensures the height of the yoke and that guides magnetic flux in the direction in which the magnetic field sensing film detects a magnetic field includes a first magnetic field detection element that has a first magnetic field sensing film that detects a magnetic field in a first direction, and a first yoke that includes a first portion that is located on a side of the first magnetic field sensing film with respect to the first direction, and a second portion that is in contact with the first portion in a direction that is orthogonal to the first direction. The average dimension of the second portion in the first direction is larger than the average dimension of the first portion in the first direction.

Abstract: A semiconductor device preferably includes a metal-oxide semiconductor (MOS) transistor disposed on a substrate, an interlayer dielectric (ILD) layer disposed on the MOS transistor, and a magnetic tunneling junction (MTJ) disposed on the ILD layer. Preferably, a top surface of the MTJ includes a reverse V-shape while the top surface of the MTJ is also electrically connected to a source/drain region of the MOS transistor.

Abstract: A method of producing a multilayer device, such as a multilayer magnetoelectronic device, and a device with an improved magnetic pinning. The device includes a multilayer structure including an antiferromagnetic pinning layer and one or more ferromagnetic layers. Each of the ferromagnetic layers has a boundary surface with the antiferromagnetic layer. The antiferromagnetic layer is deposited at a nonzero angle of incidence with respect to a direction perpendicular to the plane of extension of the antiferromagnetic pinning layer. This oblique incidence deposition gives rise to a surface roughness of the antiferromagnetic pinning layer which is described by a plane wave function.

Abstract: Magnetic locators and uses of such locators for detection of buried objects, such as buried utilities, are disclosed. Outputs provided from two or more three three-axis magnetic sensors, as well as optionally from other sensors, such as accelerometers and gyroscopic sensors, may be used to determine information about the buried utilities including one or more of position and depth of the buried utilities relative to the locator.

Abstract: A semiconductor device includes a gate insulating film on a semiconductor substrate, and a gate electrode on the gate insulating film. The gate electrode includes a first layer containing polycrystalline silicon, a second layer between the first layer and the gate insulating film and containing polycrystalline silicon and carbon, a third layer on an upper surface of the first layer and containing polycrystalline silicon and carbon, a fourth layer on a first side surface of the first layer and containing polycrystalline silicon and carbon, and a fifth layer on a second side surface of the first layer and containing polycrystalline silicon and carbon.

Abstract: Magneto-electric spin orbital (MESO) structures having functional oxide vias, and method of fabricating magneto-electric spin orbital (MESO) structures having functional oxide vias, are described. In an example, a magneto-electric spin orbital (MESO) device includes a source region and a drain region in or above a substrate. A first via contact is on the source region. A second via contact is on the drain region, the second via contact laterally adjacent to the first via contact. A plurality of alternating ferromagnetic material lines and non-ferromagnetic conductive lines is above the first and second via contacts. A first of the ferromagnetic material lines is on the first via contact, and a second of the ferromagnetic material lines is on the second via contact. A spin orbit coupling (SOC) via is on the first of the ferromagnetic material lines. A functional oxide via is on the second of the ferromagnetic material lines.

Abstract: Aspects of the subject disclosure may include, for example, a method comprising: applying to a substrate a first two-dimensional layer; and applying to the first two-dimensional layer a second two-dimensional layer, wherein the first two-dimensional layer and the second two-dimensional layer form a bi-layer element, wherein the bi-layer element has an axis, wherein there is an initial electrical resistance across the bi-layer element along the axis, and wherein a first change to the substrate results in a second change to the bi-layer element such that the initial electrical resistance is replaced by a lower electrical resistance. Other embodiments are disclosed.

Abstract: Methods of forming a high sensitivity Hall effect sensor having a thin Hall plate and the resulting devices are provided. Embodiments include providing a SOI substrate having a sequentially formed Si substrate and BOX and Si layers; forming a first STI structure in a first portion of the Si layer above the BOX layer, the first STI structure having a cross-shaped pattern; forming a second STI structure in a frame-shaped pattern in a second portion of the Si layer; the second STI structure formed outside and adjacent to the first STI structure; removing a portion of the Si layer between the first and second STI structures down to the BOX layer; removing the first STI structure, a cross-shaped Si layer remaining; and implanting N+ dopant ions into each end of the cross-shaped Si layer to form N+ implantation regions.

Abstract: Some embodiments relate to an integrated circuit including a magnetoresistive random-access memory (MRAM) cell. The integrated circuit includes a lower metal layer and an upper metal layer disposed over the lower metal layer. A bottom electrode is disposed over and in electrical contact with the lower metal layer. A magnetic tunneling junction (MTJ) is disposed over an upper surface of bottom electrode. A top electrode is disposed over an upper surface of the MTJ and is in contact with the upper metal layer. A sidewall spacer surrounds an outer periphery of the top electrode. An etch stop layer is disposed on top of an outer periphery of the spacer top surface and surrounding an outer periphery of the bottom surface of the upper metal layer. The etch stop layer overhangs the outer periphery of the spacer top surface.

Abstract: This spin current magnetization rotational element includes a second ferromagnetic metal layer having a variable magnetization orientation, and spin-orbit torque wiring, which extends in a direction that intersects a direction perpendicular to the surface of the second ferromagnetic metal layer, and is connected to the second ferromagnetic metal layer, wherein the spin resistance of a connection portion of the spin-orbit torque wiring that is connected to the second ferromagnetic metal layer is larger than the spin resistance of the second ferromagnetic metal layer.

Abstract: A printed circuit board assembly includes a current sense trace to transmit an electrical signal through the assembly. The assembly includes a magnetic core including an opening for receiving the current sense trace and includes first stack layers and second stack layers that each define opposing sides of the opening, and elongate layers that extend from the first stack layers to the second stack layers and define additional opposing sides of the opening. The assembly further includes a Hall effect sensor located in the first stack layers or the second stack layers and configured to detect Hall effect data corresponding to a first Hall effect current of the electrical signal having a DC frequency. The assembly further includes a coil wrapped around the first stack layers or the second stack layers and configured to detect coil data corresponding to an AC component of the signal.

Abstract: One illustrative integrated circuit (IC) product disclosed herein includes an MRAM cell, the MRAM cell having an outer perimeter, wherein the MRAM cell comprises a bottom electrode, a top electrode and an MTJ (Magnetic Tunnel Junction) element positioned above the bottom electrode and below the top electrode. In this example, the IC product also includes an insulating material positioned around the outer perimeter of the MRAM cell and a conductive sidewall spacer comprised of a metal-containing shielding material positioned around the outer perimeter of the MRAM cell, wherein the insulating material is positioned between the conductive sidewall spacer and the MRAM cell.

Abstract: Shielded semiconductor devices and methods for fabricating shielded semiconductor devices are provided. An exemplary magnetically shielded semiconductor device includes a substrate having a top surface and a bottom surface. An electromagnetic-field-susceptible semiconductor component is located on and/or in the substrate. The magnetically shielded semiconductor device includes a top magnetic shield located over the top surface of the substrate. Further, the magnetically shielded semiconductor device includes a bottom magnetic shield located under the bottom surface of the substrate. Also, the magnetically shielded semiconductor device includes a sidewall magnetic shield located between the top magnetic shield and the bottom magnetic shield.

Abstract: The wiring substrate includes a cavity and a plurality of vertical connecting channels disposed around the cavity. The vertical connecting channels are bonded with a resin compound and electrically connected to a routing circuitry or a conducting layer under the cavity. The bottom of the cavity is covered by a dielectric layer of the routing circuitry or the resin compound, and an aperture is formed through the dielectric layer of the routing circuitry or the resin compound to be communicated with the cavity. As a result, a semiconductor device can be face-down disposed in the cavity and electrically connected to the routing circuitry or the conducting layer by bonding wires extending through the aperture.

Abstract: An electronic device includes a semiconductor memory, wherein the semiconductor memory may include: a cell mat disposed over a substrate, the cell mat including a plurality of memory cells; an insulating layer disposed over the cell mat; a conductive pattern disposed over the insulating layer, the conductive pattern overlapping a first portion of the cell mat without overlapping a second portion of the cell mat; and a shielding layer disposed in the insulating layer, the shielding layer overlapping at least the second portion of the cell mat, the shielding layer being capable of blocking plasma.

Abstract: A module includes a circuit package and a top external shield layer. The circuit package includes multiple electronic components on a substrate; at least one side shield structure located at a corresponding at least one side edge region of the circuit package and electrically connected to ground, the at least one side shield structure being positioned on the substrate or on a pad on the substrate; and a molded compound disposed over the substrate, the electronic components, and the at least one side shield structure. The top external shield layer is disposed on a top outer surface of the circuit package and is electrically connected to ground. The at least one side shield structure and the top external shield layer provide an external shield of the module configured to protect the circuit package from external electromagnetic radiation and environmental stress.

Abstract: A coil module includes a substrate layer, a coil electrode, and a sealing resin layer. The coil electrode includes metal pins that stand on a resin substrate of the substrate layer in such a way that lower end surfaces thereof are exposed on a lower surface of the substrate layer. The sealing resin layer is stacked on the substrate layer and covers the metal pins. Upper end surfaces of the metal pins are exposed on an upper surface of the sealing resin layer. Each of the metal pins and a corresponding one of the metal pins paired therewith are connected to each other on the lower surface of the substrate layer through a lower wiring pattern. Each of the pins and a corresponding one of the metal pins are connected to each other on the upper surface of the substrate layer through an upper wiring pattern.

Abstract: An integrated circuit can have a first substrate supporting a magnetic field sensing element and a second substrate supporting another magnetic field sensing element. The first and second substrates can be arranged in a variety of configurations. Another integrated circuit can have a first magnetic field sensing element and second different magnetic field sensing element disposed on surfaces thereof.

Abstract: According to one embodiment, a magnetic memory device includes a metal-containing layer including a metallic element, a first magnetic layer, a second magnetic layer, and a first intermediate layer. The second magnetic layer is provided between the first magnetic layer and a portion of the metal-containing layer. The first intermediate layer includes a portion provided between the first magnetic layer and the second magnetic layer. The first intermediate layer is nonmagnetic. The first intermediate layer is convex toward the metal-containing layer.

Abstract: A lateral spin valve reader includes a detector located proximate to a bearing surface of the reader, and a spin injector located away from the bearing surface. The lateral spin valve reader also includes a channel that extends from the detector to the spin injector. The channel includes a two-dimensional semiconducting layer that extends from the detector to the spin injector.

Abstract: An integrated circuit can have a first substrate supporting a magnetic field sensing element and a second substrate supporting another magnetic field sensing element. The first and second substrates can be arranged in a variety of configurations. Another integrated circuit can have a first magnetic field sensing element and second different magnetic field sensing element disposed on surfaces thereof.

Abstract: An absolute electromagnetic position encoder comprises a readhead and an absolute scale. The readhead comprises a spatially modulated signal coupling configuration and a readhead processor. The absolute scale comprises a passive signal pattern, an active signal pattern and a timing and activation circuit connected to the active signal pattern. During a first signal generating cycle, the readhead processor is configured to provide first cycle spatially periodic signals and the timing and activation circuit is configured to receive and store energy. During a second signal generating cycle, the timing and activation circuit is configured to drive the active signal pattern and the readhead processor is configured to provide at least one corresponding second cycle signal. The readhead processor is configured to determine an absolute position of the readhead relative to the absolute scale based on at least the second cycle signal and the first cycle spatially periodic signals.

Abstract: A method of magnetic tunnel junction patterning for magnetoresistive random access memory devices using low atomic weight ion sputtering. The method includes: providing a magnetoresistive random access memory device including a hard mask metal, a MTJ element, and a semiconductor substrate, wherein the hard mask metal is disposed on the MTJ element and, wherein the MTJ element is disposed on the semiconductor substrate; and etching back the MTJ element into a plurality of MTJ element pillars using a low atomic weight ion sputtering. A magnetoresistive random access memory device using low atomic weight ion sputtering. The device includes: a semiconductor substrate; a plurality of MTJ element pillars disposed on the semiconductor substrate, wherein the plurality of MTJ element pillars is etched from a MTJ element using a low atomic weight ion sputtering; and a hard mask metal disposed on the MTJ element pillars.

Abstract: Spin-transport elements using semiconductors have had the problem of higher element resistance than conventional GMR elements and TMR elements, making it difficult to obtain high magnetoresistance ratios. A magnetoresistive element including a semiconductor channel layer; a first ferromagnetic layer disposed on the semiconductor channel layer; a second ferromagnetic layer disposed away from the first ferromagnetic layer; and a non-magnetic first reference electrode disposed away from the first ferromagnetic layer and the second ferromagnetic layer, wherein current is input from the second ferromagnetic layer to the first ferromagnetic layer through the semiconductor channel layer, a voltage between the second ferromagnetic layer and the first reference electrode is output.

Abstract: This technology provides an electronic device. An electronic device in accordance with an implementation of this document may include a semiconductor memory, and the semiconductor memory may include: an under layer including a plurality of material layers having a different crystal structures; a first magnetic layer formed over the under layer and having a variable magnetization direction; a tunnel barrier layer formed over the first magnetic layer; and a second magnetic layer formed over the tunnel barrier layer and having a pinned magnetization direction.

Abstract: A Hall-Effect measure apparatus comprises a magnetic source, a wafer on a thermal chuck, a dc current source and a voltage meter. The magnetic source generates a magnetic field in a perpendicular position relative to the wafer. Furthermore, the magnetic field is targeted at a specific region of the wafer to be tested. By performing a Hall-Effect measurement and van der Pauw measurement, the carrier mobility of the specific region of the wafer can be calculated.

Abstract: According to the embodiments, a semiconductor device includes a substrate, a plurality of insulating layers, a lower shield plate, a semiconductor device, an upper shield plate, and a side shield member. A first contact portion is formed on the substrate. The lower shield plate includes a magnetic substance and is provided above the substrate so as to avoid the first contact portion. The semiconductor chip is provided above the lower shield plate and has a second contact portion electrically connected to the first contact portion. The upper shield plate includes a magnetic substance and is provided above the semiconductor chip so as to avoid the second contact portion and a connection member. The side shield member includes a magnetic substance and connects side portions of the lower shield plate and the upper shield plate on which the connection member is not disposed.

Abstract: A semiconductor device may include a first magnetic layer including a plurality of first regions configuring a plurality of memory cells and spaced apart from each other on a substrate, and a second region encompassing the plurality of first regions and electrically isolated from the first regions, a tunnel barrier layer disposed on the first magnetic layer, and a second magnetic layer disposed on the tunnel barrier layer.

Abstract: The generation of a Hall voltage within a semiconductor film of an integrated Hall effect sensor uses the flow of a current within the semiconductor film when subjected to a magnetic field. The film is disposed on top of an insulating layer, referred to as buried layer, which is itself disposed on top of a carrier substrate containing a buried electrode that is situated under the insulating layer. A biasing voltage is applied to the buried electrode.

Abstract: A memory having an array of perpendicular spin-transfer torque (STT) magnetic random access memory (MRAM) cells, wherein each cell has a magnetic layer stack. A magnetic shield disposed between the cells and having a minimum height of at least the height of the magnetic layer stacks.

Abstract: According to one embodiment, a semiconductor memory device includes a memory cell, a bit line connected to the memory cell, a sense circuit which senses data of the memory cell based on second current that flows through the memory cell and first current, a first transistor of a first conductivity type, which is connected to the bit line and through which the second current flows, and a second transistor of the first conductivity type, through which the first current flows.

Abstract: A memory device using a spin hall effect, and methods of manufacturing and operating the memory device, include applying a first operational current to a bit line of the memory device such that a spin current is applied to a magnetic tunnel junction (MTJ) cell coupled to the bit line due to a material in the bit line, wherein the bit line is electrically connected to a word line via the MTJ cell, and the word line intersects the bit line.

Abstract: The present invention provides vicinal surfaces of polycrystalline materials and a method for their preparation. The method includes the deposition of a polycrystalline material on a substrate followed by removing the material from the substrate so as to expose a vicinal surface having stepped terraces. The step of removing the material from the substrate may be preceded by annealing. The vicinal surfaces are useful for a variety of applications.

Abstract: The present invention relates to a mobile terminal and a corresponding case with a shield magnet for driving a Hall IC of the terminal, in which the case can be used to automatically operate the mobile terminal simultaneously with opening and closing the case by utilizing the magnetic force of the shield magnet which is composed of a yoke and a permanent magnet and attached to the case.

Abstract: A method and system for providing a magnetic junction usable in a magnetic device are described. The magnetic includes a pinned layer, a nonmagnetic spacer layer, a free layer, and package structure(s). The pinned layer has a pinned layer perimeter and a top surface. The nonmagnetic spacer layer is on at least part of the top surface and between the pinned and free layers. The free layer has a free layer perimeter. The package structure(s) are ferromagnetic and encircles at least one of the free layer and the pinned layer. The package structure(s) are ferromagnetically coupled with the pinned layer. The magnetic junction is configured such that the free layer is switchable between stable magnetic states when a write current is passed through the magnetic junction.

Abstract: A technique is provided for a thermally assisted magnetoresistive random access memory device. A magnetic tunnel junction is formed. Contact wiring having a top contact electrode and a bottom contact electrode is formed. The contact wiring provides write bias to heat the magnetic tunnel junction. A multilayer dielectric encapsulant is configured to retain the heat within the magnetic tunnel junction.