With Magnetic Field Directing Means (e.g., Shield, Pole Piece, Etc.) Patents (Class 257/422)
  • Patent number: 6559521
    Abstract: A method and apparatus which provide one or more electromagnetic shield layers for integrated circuit chips containing electromagnetic circuit elements are disclosed. The shield layers may be in contact with the integrated circuit chip, including magnetic memory structures such as MRAMs, or in a flip-chip carrier, or both. A printed circuit board which supports the chip may also have one or more shield layers.
    Type: Grant
    Filed: April 5, 2002
    Date of Patent: May 6, 2003
    Assignee: Micron Technology, Inc.
    Inventor: Mark Tuttle
  • Publication number: 20030075769
    Abstract: A galvanometer unit comprises a limited-rotation motor with a load element such as a mirror attached to a shaft extending from the motor. In a servo loop that controls the angular position of the mirror, a position-sensor attached to the shaft provides position feedback information. The sensor includes a rotor which is positioned at the null point of the fundamental torsional resonance mode of the rotating system, thereby essentially eliminating feedback components resulting from the resonance.
    Type: Application
    Filed: November 27, 2002
    Publication date: April 24, 2003
    Inventors: David C. Brown, Felix Stukalin
  • Patent number: 6552411
    Abstract: A method for forming a desired junction profile in a semiconductor device. At least one dopant is introduced into a semiconductor substrate. The at least one dopant is diffused in the semiconductor substrate through annealing the semiconductor substrate and the at least one dopant while simultaneously exposing the semiconductor substrate to an electric field.
    Type: Grant
    Filed: March 16, 2001
    Date of Patent: April 22, 2003
    Assignee: International Business Machines Corporation
    Inventors: Arne W. Ballantine, John J. Ellis-Monaghan, Toshihura Furukawa, Jeffrey D. Gilbert, Glenn R. Miller, James A. Slinkman
  • Patent number: 6538297
    Abstract: A magneto-resistive device and a magneto-resistive effect type storage device are provided, which have improved selectivity and output signals by controlling bias to be applied. Two resistive devices are connected in series, and a magneto-resistive device is used for at least one of the resistive devices. When both of the resistive devices are magneto-resistive devices, their magnetic resistance should be controlled independently from each other, and by allowing the first magneto-resistive device to include a nonmagnetic substance of an electrical insulator and the second magneto-resistive device to include a nonmagnetic substance of a conductive substance, the second magneto-resistive device is operated as a bias control device for controlling the characteristics of the first magneto-resistive device so as to control the voltage to be applied to the storage device.
    Type: Grant
    Filed: March 13, 2001
    Date of Patent: March 25, 2003
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Akihiro Odagawa, Hiroshi Sakakima, Kiyoyuki Morita
  • Patent number: 6528326
    Abstract: A magnetoresistive device including a high-resistivity layer (13), a first magnetic layer (12) and a second magnetic layer (14), the first magnetic layer (12) and the second magnetic layer (14) being arranged so as to sandwich the high-resistivity layer (13), wherein the high-resistivity layer (13) is a barrier for passing tunneling electrons between the first magnetic layer (12) and the second magnetic layer (14), and contains at least one element LONC selected from oxygen, nitrogen and carbon; at least one layer A selected from the first magnetic layer (12) and the second magnetic layer (14) contains at least one metal element M selected from Fe, Ni and Co, and an element RCP different from the metal element M; and the element RCP combines with the element LONC more easily in terms of energy than the metal element M. Accordingly, a novel magnetoresistive device having a low junction resistance and a high MR can be obtained.
    Type: Grant
    Filed: January 24, 2001
    Date of Patent: March 4, 2003
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Masayoshi Hiramoto, Nozomu Matsukawa, Hiroshi Sakakima, Hideaki Adachi, Akihiro Odagawa
  • Patent number: 6525385
    Abstract: A semiconductor device with an inductance element reduces eddy current in a conductive element and secures required inductance. The semiconductor device includes a semiconductor chip and the inductance element of flat structure formed on a surface of the semiconductor chip. The semiconductor chip is fixed to the conductive element, to form a package. The element has a magnetic material to face the semiconductor chip.
    Type: Grant
    Filed: June 27, 2001
    Date of Patent: February 25, 2003
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Tetsuo Inoue, Takao Ito
  • Patent number: 6509620
    Abstract: A microelectromechanical system (MEMS) device is disclosed for determining the position of a mover. The MEMS device has a bottom layer connected to a mover layer. The mover layer is connected to a mover by flexures. The mover moves relative to the mover layer and the bottom layer. The flexures urge the mover back to an initial position of mechanical equilibrium. The flexures include coupling blocks to control movement of the mover. The MEMS device determines the location of the mover by determining the capacitance between mover electrodes located on the coupling blocks of the flexures and counter electrodes located on an adjacent layer. The coupling block moves according to a determinable relationship with the mover. As the coupling block moves, the capacitance between the mover electrode and the counter electrode changes. A capacitance detector analyzes the capacitance between the electrodes and determines the position of the mover.
    Type: Grant
    Filed: May 31, 2001
    Date of Patent: January 21, 2003
    Assignee: Hewlett-Packard Company
    Inventors: Peter G. Hartwell, Donald J. Fasen
  • Patent number: 6504221
    Abstract: A magnetic memory device includes a data ferromagnetic layer having a magnetization that can be oriented in either of two directions, a reference layer, and a spacer layer between the data and reference layers. The reference layer includes a dielectric layer, first and second conductors separated by the dielectric layer, and a ferromagnetic cladding on the first and second conductors. The memory device may be read by temporarily setting the magnetization of the reference layer to a known orientation, and determining a resistance state of the device.
    Type: Grant
    Filed: September 25, 2001
    Date of Patent: January 7, 2003
    Assignee: Hewlett-Packard Company
    Inventors: Lung T. Tran, Manish Sharma, Manoj K. Bhattacharyya
  • Patent number: 6492708
    Abstract: A means for fabrication of solenoidal inductors integrated in a semiconductor chip is provided. The solenoidal coil is partially embedded in a deep well etched into the chip substrate. The non-embedded part of the coil is fabricated as part of the BEOL metallization layers. This allows for a large cross-sectional area of the solenoid turns, thus reducing the turn-to-turn capacitive coupling. Because the solenoidal coils of this invention have a large diameter cross-section, the coil can be made with a large inductance value and yet occupy a small area of the chip. The fabrication process includes etching of a deep cavity in the substrate after all the FEOL steps are completed; lining said cavity with a dielectric followed by fabrication of the part of the coil that will be embedded by deposition of a conductive material metal through a mask; deposition of dielectric and planarization of same by CMP.
    Type: Grant
    Filed: March 14, 2001
    Date of Patent: December 10, 2002
    Assignee: International Business Machines Corporation
    Inventors: Raul E. Acosta, Melanie L. Carasso, Steven A. Cordes, Robert A. Groves, Jennifer L. Lund, Joanna Rosner
  • Patent number: 6479353
    Abstract: A magnetic storage cell includes an active layer and a reference layer which is structured to minimize disruptions to magnetization in its active layer. The reference layer is structured so that a pair of its opposing edges overlap a pair of corresponding edges of the active layer. This may be used minimize the effects of demagnetization fields on the active layer. In addition, the reference layer may be thinned at its opposing edges to control the effects of coupling fields on the active layer and balance the demagnetization field.
    Type: Grant
    Filed: May 31, 2001
    Date of Patent: November 12, 2002
    Assignee: Hewlett-Packard Company
    Inventor: Manoj Bhattacharyya
  • Patent number: 6465856
    Abstract: A microstructure that may be used as an electrical connection in a microfabricated electro-mechanical system (MEMS) apparatus. The microstructure may have one or more isolatable electrical connections for signal transmission. The microstructure allows a MEMS apparatus to shield signal transmissions from the effects of electromagnetic interference or conductive fluids.
    Type: Grant
    Filed: March 19, 2001
    Date of Patent: October 15, 2002
    Assignee: Xerox Corporation
    Inventors: Peter M. Gulvin, Jingkuang Chen
  • Patent number: 6452240
    Abstract: In order to dampen magnetization changes in magnetic devices, such as tunnel junctions (MTJ) used in high speed Magnetic Random Access Memory (MRAM), a transition metal selected from the 4d transition metals and 5d transition metals is alloyed into the magnetic layer to be dampened. In a preferred form, a magnetic permalloy layer is alloyed with osmium (Os) in an atomic concentration of between 4% and 15% of the alloy.
    Type: Grant
    Filed: October 30, 2000
    Date of Patent: September 17, 2002
    Assignee: International Business Machines Corporation
    Inventors: Snorri T. Ingvarsson, Roger H. Koch, Stuart S. Parkin, Gang Xiao
  • Publication number: 20020084501
    Abstract: A magnetoresistive device including a high-resistivity layer (13), a first magnetic layer (12) and a second magnetic layer (14), the first magnetic layer (12) and the second magnetic layer (14) being arranged so as to sandwich the high-resistivity layer (13), wherein the high-resistivity layer (13) is a barrier for passing tunneling electrons between the first magnetic layer (12) and the second magnetic layer (14), and contains at least one element LONC selected from oxygen, nitrogen and carbon; at least one layer A selected from the first magnetic layer (12) and the second magnetic layer (14) contains at least one metal element M selected from Fe, Ni and Co, and an element RCP different from the metal element M; and the element RCP combines with the element LONC more easily in terms of energy than the metal element M. Accordingly, a novel magnetoresistive device having a low junction resistance and a high MR can be obtained.
    Type: Application
    Filed: January 3, 2002
    Publication date: July 4, 2002
    Applicant: Matsushita Electric Industrial Co., Ltd.
    Inventors: Masayoshi Hiramoto, Nozomu Matsukawa, Hiroshi Sakakima, Hideaki Adachi, Akihiro Odagawa
  • Patent number: 6387549
    Abstract: A high-sensitivity magnetic sensor capable of detecting a nonequilibrium spin, uses an almost-spin-polarized ferromagnetic oxide in a high-quality trilayer arrangement including an intermediate layer made of a conductive nonmagnetic oxide not reacting with a ferromagnetic metallic oxide and having a lattice matching between a spin injection layer and a spin detection layer.
    Type: Grant
    Filed: June 29, 1999
    Date of Patent: May 14, 2002
    Assignee: NEC Corporation
    Inventors: Takeshi Obata, Takashi Manako, Yuichi Shimakawa
  • Patent number: 6342713
    Abstract: A hybrid memory device combines a ferromagnetic layer and a Hall Effect device. The ferromagnetic layer is magnetically coupled to a portion of a Hall plate, and when such plate is appropriately biased, a Hall Effect signal can be generated whose value is directly related to the magnetization state of the ferromagnetic layer. The magnetization state of the ferromagnetic layer can be set to correspond to different values of a data item to be stored in the hybrid memory device. The magnetization state is non-volatile, and a write circuit can be coupled to the ferromagnetic layer to reset or change the magnetization state to a different value. The memory device can also be fabricated to include an associated transistor (or other suitable switch) that functions as an isolation element to reduce cross-talk and as a selector for the output of the device when such is used in a memory array.
    Type: Grant
    Filed: March 22, 2000
    Date of Patent: January 29, 2002
    Inventor: Mark B. Johnson
  • Publication number: 20010022373
    Abstract: A magnetic memory element has a first ferromagnetic layer, a second ferromagnetic layer, and a non-magnetic layer disposed between these ferromagnetic layers. The non-magnetic layer has an electrical characteristic that is changeable depending on an external magnetic field applied to the non-magnetic layer.
    Type: Application
    Filed: March 16, 2001
    Publication date: September 20, 2001
    Inventors: Ryoji Minakata, Masashi Michijima, Hidekazu Hayashi
  • Patent number: 6278271
    Abstract: A magnetic field sensor for measurement of the three components (Bx, By, Bz) of a magnetic field comprises a Hall-effect element (1) and an electronic circuit (22). The Hall-effect element (1) comprises an active area (18) of a first conductivity type which is contacted with voltage and current contacts (2-5 or 6-9). Four voltage contacts (2-5) are present which are connected to inputs of the electronic circuit (22). By means of summation or differential formation of the electrical potentials (V2, V3, V4, V5) present at the voltage contacts (2-5), the electronic circuit (22) derives three signals (Vx, Vy, Vz) which are proportional to the three components (Bx, By, Bz) of the magnetic field.
    Type: Grant
    Filed: March 29, 1999
    Date of Patent: August 21, 2001
    Assignee: Sentron AG
    Inventor: Christian Schott
  • Patent number: 6208000
    Abstract: A semiconductor device according to the invention is constructed as below. A charge accumulating layer which contains a magnetic substance is formed directly on a semiconductor substrate, and a gate insulating film is formed on the charge accumulating layer. Further, a gate electrode is formed on the gate insulating film, and source and drain regions formed in surface portions of the semiconductor substrate such that the gate electrode is interposed therebetween. Another semiconductor device according to the invention is constructed as below. A first gate insulating film formed on a semiconductor substrate, and a charge accumulating layer which contains a magnetic substance is formed on the first gate insulating film. Further, a second gate insulating film is formed on the charge accumulating layer, and a gate electrode is formed on the second gate insulating film. Source and drain regions formed in surface portions of the semiconductor substrate such that the gate electrode is interposed therebetween.
    Type: Grant
    Filed: May 4, 1999
    Date of Patent: March 27, 2001
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Tetsufumi Tanamoto, Shinobu Fujita, Koichiro Inomata
  • Patent number: 6195229
    Abstract: A method of manufacturing a thin film merged magnetic head including an inductive write structure and a magnetoresistive sensor uses a patterned protection layer to protect a second shield/bottom pole layer in regions spaced from the pole tip of the inductive write structure. A window is provided in the protection layer. During manufacture, the configuration comprises a first shield layer, a magnetoresistive element, a second shield layer serving as a bottom pole, a protection layer, a protection window, a write gap, a top pole, and a pole tip structure. The use of a protection layer and window results in the formation of channels in the second shield layer adjacent to a pedestal that supports the inductive write structure. The channels prevent magnetic flux from extending toward the second shield layer beyond the width of the pole tip structure. This structure reduces side writing with a consequent improvement in off-track performance.
    Type: Grant
    Filed: August 30, 1999
    Date of Patent: February 27, 2001
    Assignee: Read-Rite Corporation
    Inventors: Yong Shen, Bertha Higa-Baral, Lien-Chang Wang
  • Patent number: 6114719
    Abstract: A magnetic tunnel junction (MTJ) memory cell uses a biasing ferromagnetic layer in the MTJ stack of layers that is magnetostatically coupled with the free ferromagnetic layer in the MTJ stack to provide transverse and/or longitudinal bias fields to the free ferromagnetic layer. The MTJ is formed on an electrical lead on a substrate and is made up of a stack of layers.
    Type: Grant
    Filed: May 29, 1998
    Date of Patent: September 5, 2000
    Assignee: International Business Machines Corporation
    Inventors: Frederick Hayes Dill, Robert Edward Fontana, Jr., Tsann Linn, Stuart Stephen Papworth Parkin, Ching Hwa Tsang
  • Patent number: 6084281
    Abstract: Planar magnetic motor (100), characterized by the fact that it comprises a plurality of magnetic poles (111, 121) made of a ferromagnetic material placed at the center of planar coils (110, 120) constituted by at least one layer of turns produced on the surface of a substrate (150) made of a ferromagnetic material, the turns being wound and connected to each other so as to combine the magnetic fluxes generated by the magnetic poles (111, 121). The invention can be used to produced magnetic motors and microactuators.
    Type: Grant
    Filed: April 1, 1998
    Date of Patent: July 4, 2000
    Assignee: CSEM Centre Suisse d'Electronique et de Microtechnique S.A.
    Inventors: Enzo Fullin, Raymond Vuilleumier
  • Patent number: 6064083
    Abstract: A hybrid memory device combines a ferromagnetic layer and a Hall Effect device. The ferromagnetic layer is magnetically coupled to a portion of a Hall plate, and when such plate is appropriately biased, a Hall Effect signal can be generated whose value is directly related to the magnetization state of the ferromagnetic layer. The magnetization state of the ferromagnetic layer can be set to correspond to different values of a data item to be stored in the hybrid memory device. The magnetization state is non-volatile, and a write circuit can be coupled to the ferromagnetic layer to reset or change the magnetization state to a different value. The memory device can also be fabricated to include an associated transistor (or other suitable switch) that functions as an isolation element to reduce cross-talk and as a selector for the output of the device when such is used in a memory array.
    Type: Grant
    Filed: February 24, 1997
    Date of Patent: May 16, 2000
    Inventor: Mark B. Johnson
  • Patent number: 5990533
    Abstract: Disclosed is a semiconductor device with a current detector, in which a semiconductor element for current-driving a load and a current-detecting element for detecting a driving current flowing through the semiconductor element are integrated on a common semiconductor pellet, and which has: a magnetoresistance effect element which has a two layer film composed of a magnetic film and a conductive film and means for supplying the two-layer film with a constant current and which has a resistivity depending on a magnetic field generated by the driving current; wherein the magnetoresistance effect element is vertically deposited above the semiconductor element to function as the current-detecting element.
    Type: Grant
    Filed: March 31, 1997
    Date of Patent: November 23, 1999
    Assignee: NEC Corporation
    Inventor: Yuji Hasegawa
  • Patent number: 5962905
    Abstract: A magnetoresistive element comprises an n-type emitter layer, a p-type base layer, and an n-type collector layer, the three layers being so arranged as to form a pn-junction with each other, an emitter ferromagnetic layer formed in contact with the n-type emitter layer, a base ferromagnetic layer formed in contact with the p-type base layer, a power source for applying, by way of the emitter ferromagnetic layer, a forward bias voltage between the n-type emitter layer and the p-type base layer, a power source for applying a backward bias voltage to the n-type collector layer and the p-type base layer and a power source for applying, by way of the base ferromagnetic layer, a bias voltage so as to inject minority carriers into the p-type base layer.
    Type: Grant
    Filed: September 16, 1997
    Date of Patent: October 5, 1999
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yuzo Kamiguchi, Masashi Sahashi
  • Patent number: 5936299
    Abstract: An inductor structure includes an inductor spiral coil formed on a substrate; and a substrate contact connected to the substrate and disposed within a predetermined distance to the inductor spiral coil to increase the quality-factor (Q) characteristics associated with the inductor structure, and also does not increase eddy currents in the substrate. The substrate contact provides for implementation of the inductor structure as a spiral inductor which is integrated on a silicon substrate. The substrate contact determines the energy potential substantially adjacent to the inductor for reducing the noise level. In an implementation of an inductor in an RF circuit, the substrate contact contributes to providing an increased Q.
    Type: Grant
    Filed: March 13, 1997
    Date of Patent: August 10, 1999
    Assignee: International Business Machines Corporation
    Inventors: Joachim Norbert Burghartz, Keith Aelwyn Jenkins, Mehmet Soyuer
  • Patent number: 5936293
    Abstract: A magnetic tunnel junction (MTJ) of the type using soft (low magnetic coercivity) and hard (high magnetic coercivity) ferromagnetic layers separated by an insulating tunnel barrier (a hard/soft MTJ device) is stable without loss of magnetization after repeated cycling of its magnetic state. The MTJ device is based on the discovery that the mechanism of demagnetization in a hard/soft MTJ device is via coupling of the hard ferromagnetic layer to the soft ferromagnetic layer via the formation and motion of domain walls in the soft ferromagnetic layer. The MTJ device includes adjacent ferromagnetic structures that provide a transverse biasing magnetic field to the soft ferromagnetic layer. The transverse biasing field permits coherent rotation of the magnetic moment of the soft ferromagnetic layer without the formation of magnetic domains when suitable switching fields are applied.
    Type: Grant
    Filed: January 23, 1998
    Date of Patent: August 10, 1999
    Assignee: International Business Machines Corporation
    Inventor: Stuart Stephen Papworth Parkin
  • Patent number: 5811832
    Abstract: A memory device consists of an array of resonant tunnel diodes in the form of pillars which are formed by selective etching. Each pillar includes first and second barriers (B1, B2) disposed between terminal regions (T1, T2) and a conductive region (CR1) between the barriers. The diameter of the pillars is typically of the order of 20-50 nm and is sufficiently small that the device exhibits first and second relatively high and low stable resistive states in the absence of an applied voltage between the terminal regions. The device can be used as a non-volatile memory at room temperature.
    Type: Grant
    Filed: October 18, 1995
    Date of Patent: September 22, 1998
    Assignee: Hitachi, Ltd.
    Inventors: Bruce Alphenaar, Zahid Ali Khan Durrani
  • Patent number: 5808349
    Abstract: A strong magnetic field is applied to a photoconductive semiconductor switch to make the opening time of the switch independent of the recombination time of the photoionized semiconductor. As a result, the switch is capable of shaping current pulses with the fidelity of an illuminating optical pulse used to activate the switch. The strong magnetic field applied to the photoconductive semiconductor switch has a strength satisfying the relationship .mu.B>1, where .mu. is the mobility of the semiconductor (in m.sup.2 /Volt Sec) and B the magnetic field (in Tesla). Such a switch acts as an insulator (magnetic insulation) to an applied electric field except during the time that the light incident thereon generates electron-hole pairs. During that time, a polarization current, proportional to the externally induced pair production rate, flows and the magnetic insulation is broken. The minimal system response time is controlled by the gyrofrequency of the carriers.
    Type: Grant
    Filed: December 5, 1995
    Date of Patent: September 15, 1998
    Assignee: APTI Inc.
    Inventor: Konstantinos Papadopoulos
  • Patent number: 5767673
    Abstract: Magnetoresistive elements according to this invention comprise magnetically soft material in close proximity to the magnetoresistive material, exemplarily a perovskite manganite. The combination results in magnetic field "amplification", with large resistance changes attainable at relatively low applied fields. The invention exemplarily is embodied in magnetic sensors, e.g., magnetoresistive read/write heads.
    Type: Grant
    Filed: June 27, 1996
    Date of Patent: June 16, 1998
    Assignee: Lucent Technologies Inc.
    Inventors: Bertram Josef Batlogg, Sang-Wook Cheong, Harold Yoonsung Hwang
  • Patent number: 5757055
    Abstract: A triple drain magnetic field effect transistor (MagFET) for measuring magnetic field. The disclosed MagFET has a gate, a source, a center drain and two lateral drains and generates an increased Hall voltage between the two lateral drains. The MagFET provides a high conductivity channel disposed between the center drain and the source to allow a high sense current to flow. The relationship between the sense current and the background carrier concentration of the lateral drains of the transistor are effectively reduced or decoupled in order to provide the increased Hall voltage between the lateral drains in response to a magnetic field.
    Type: Grant
    Filed: September 17, 1996
    Date of Patent: May 26, 1998
    Assignee: Intel Corporation
    Inventor: Jeffrey C. Kalb, Jr.
  • Patent number: 5654566
    Abstract: A new hybrid magnetic spin injected-FET structure can be used as a memory element for the nonvolatile storage of digital information, as well as in other environments, including for example logic applications for performing digital combinational tasks, or a magnetic field sensor. The hybrid FET uses ferromagnetic materials for the source and drain, and like a conventional FET, has two operating states determined by a gate voltage, "off" and "on". The ferromagnetic layers of the hybrid FET are fabricated to permit the device to have two stable magnetization states, parallel and antiparallel. In the "on" state the spin injected FET has two settable, stable resistance states determined by the relative orientation of the magnetizations of the ferromagnetic source and drain.
    Type: Grant
    Filed: May 6, 1996
    Date of Patent: August 5, 1997
    Inventor: Mark B. Johnson
  • Patent number: 5652445
    Abstract: A modified Hall Effect device can be used as a memory element for the nonvolatile storage of digital information. The novel device includes a ferromagnetic layer that covers a portion of a Hall plate and is electrically isolated from the Hall plate. The ferromagnetic layer on the Hall plate can be changed by an externally applied field, and permits the device to have two stable magnetization states (positive and negative) along an anisotropy axis, which can correspond to two different data values (0 or 1) when the device is used as a memory element. In another embodiment of the invention, the Hall plate is integrated with a conduction channel of a FET, and the ferromagnetic layer is incorporated in proximity to, or as part of the gate over the conducting channel. This device can be described as a "ferromagnetic gated FET.
    Type: Grant
    Filed: May 6, 1996
    Date of Patent: July 29, 1997
    Inventor: Mark B. Johnson
  • Patent number: 5629549
    Abstract: A new magnetic spin transistor is provided. This spin transistor can be used as a memory element or logic gate, such as an OR, AND, NOT, NOR and NAND gate. The state of the magnetic spin transistor logic gate is set inductively. This new magnetic spin transistor/gate can be operated with current gain. Furthermore, inductive coupling permits the linking of multiple spin transistors and spin transistor gates to perform combinational tasks. A half adder embodiment is specifically described, and other logic gates and combinations of half adders can be constructed to perform arithmetic functions as part of a microprocessor.
    Type: Grant
    Filed: April 21, 1995
    Date of Patent: May 13, 1997
    Inventor: Mark B. Johnson
  • Patent number: 5591996
    Abstract: A device for producing an output voltage which is proportional to an applied magnetic field. The device includes a plurality charge injection regions, a corresponding plurality of charge exit regions, and a charge transfer region. The charge transfer region includes gate electrodes which serve to propagate at least one isolated charge packet across the charge transfer region in a predetermined direction from the charge input region to the charge output region. The charge packet is subject to the applied magnetic field which is perpendicular to the charge transfer region so as to induce a resultant potential that is orthogonal to both the applied magnetic field and the predetermined direction. Furthermore, the resultant potential effects a lateral redistribution of charge carriers in the packet. A recirculation configuration allows for a recycling of the packet from the output region back to the input region in order to accommodate a continuation of the redistribution of charge carriers.
    Type: Grant
    Filed: March 24, 1995
    Date of Patent: January 7, 1997
    Assignee: Analog Devices, Inc.
    Inventors: Geoffrey T. Haigh, Scott C. Munroe
  • Patent number: 5557132
    Abstract: A silicon substrate is partially removed for forming a movable center portion connected through torsional portions to a stationary portion, and current flows through a coil formed in the movable center portion so that a moving contact formed in the torsional portion comes into contact with a fixed point.
    Type: Grant
    Filed: December 6, 1994
    Date of Patent: September 17, 1996
    Assignee: NEC Corporation
    Inventor: Masazi Takahashi
  • Patent number: 5502325
    Abstract: A magnetoresistor is monolithically integrated with an active circuit by growing a thin film magnetoresistor on a semiconductor substrate after the substrate has been doped and annealed for the active devices. The magnetoresistor is grown through a window in a mask, with the mask and magnetoresistor materials selected such that the magnetoresistor is substantially non-adherent to the mask. InSb is preferred for the magnetoresistor, Si.sub.3 N.sub.4 for the mask and GaAs for the substrate. The non-adherence allows the mask to be substantially thinner than the magnetoresistor without impairing the removal of the mask after the magnetoresistor has been established.
    Type: Grant
    Filed: May 30, 1995
    Date of Patent: March 26, 1996
    Assignee: Hughes Aircraft Company
    Inventors: Marko Sokolich, Hiroyuki Yamasaki, Huai-Tung Yang
  • Patent number: 5488250
    Abstract: A semiconductor structure is disclosed in which two regions of semiconductor material positioned adjacent to each other have different electron mobilities. By application of a magnetic field to the device, a Hall voltage is created across the boundary region between the regions of semiconductor material to modify their resistance. By detecting the change in resistance, the device can function as a memory cell, a programmable logic device, a head for hard disk drives, a measurement tool for measuring magnetic fields, or other apparatus.
    Type: Grant
    Filed: June 1, 1994
    Date of Patent: January 30, 1996
    Assignee: Falke Hennig
    Inventor: Falke Hennig
  • Patent number: 5324977
    Abstract: A hybrid integrated circuit device has a magnetic sensor formed directly on a substrate by photolithography. Alternatively, a flip chip type magnetic sensor is mounted on a substrate by fusion. The magnetic sensor can be mounted on the substrate with high positional precision.
    Type: Grant
    Filed: November 18, 1992
    Date of Patent: June 28, 1994
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Ziro Honda, Masato Imanaka
  • Patent number: 5322818
    Abstract: A method for forming an oxide superconducting material by preparing first a shaped magnetic shield comprising an oxide superconductor as a matrix, and then effecting CVD and further EVD to fill in the pores of the matrix with an oxide superconductor; more specifically, it comprises introducing an oxidizing gas to said shaped magnetic shield from either inside or outside the shaped magnetic shield while introducing a material gas of said oxide superconductor from the other side thereof, and then maintaining said shaped magnetic shield at this state under a high temperature.
    Type: Grant
    Filed: March 8, 1993
    Date of Patent: June 21, 1994
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Hisashi Ohtani
  • Patent number: 5189504
    Abstract: A semiconductor device of a MOS structure having a p-type gate electrode has a gate electrode including at least two layers consisting of a boron-doped polysilicon layer and a polysilicon layer doped with boron and an inert material. This inert material is nitrogen or carbon.
    Type: Grant
    Filed: January 30, 1992
    Date of Patent: February 23, 1993
    Assignee: Nippon Telegraph and Telephone Corporation
    Inventors: Satoshi Nakayama, Tetsushi Sakai
  • Patent number: 5179429
    Abstract: A magnetic field sensor is provided by a lateral bipolar transistor having a base region formed of a first conductivity type, an emitter region formed of a second conductivity type disposed in the base region for emitting charge carriers, and a collector region of the second conductivity type disposed in the base region for receiving charge carriers from the emitter region. A first and second metallic contact are connected to the collector region for splitting the collector current into first and second collector contact currents. In the presence of a magnetic field, a number of the charge carriers are deflected toward the first or the second metallic contact, depending on the orientation of the magnetic field, causing an imbalance in the first and second collector contact currents. The noise at the metallic contacts is the same as the noise of a single collector transistor which effectively correlates the noise with itself and cancels any distortion associated with the noise.
    Type: Grant
    Filed: March 30, 1992
    Date of Patent: January 12, 1993
    Assignee: Motorola, Inc.
    Inventor: Ljubisa Ristic