With Magnetic Field Directing Means (e.g., Shield, Pole Piece, Etc.) Patents (Class 257/422)
  • Patent number: 7545013
    Abstract: A nonvolatilely reconfigurable logical circuit is built. It is a reconfigurable logical circuit based on the CMOS configuration using the spin MOSFET. By changing the transmission characteristic of each transistor in accordance with the magnetization states of Tr1, Tr2, Tr5, and Tr8 which are spin MOSFETs, it is possible to reconfigure all the two-input symmetric functions AND/OR/XOR/NAND/NOR/XNOR/“1”/“0”. Since it is possible to constitute the logical function by a small number of non-volatile elements, it is possible to reduce the chip area, thereby increasing the speed and reducing the power consumption.
    Type: Grant
    Filed: March 26, 2004
    Date of Patent: June 9, 2009
    Assignee: Japan Science and Technology Agency
    Inventors: Satoshi Sugahara, Tomohiro Matsuno, Masaaki Tanaka
  • Patent number: 7545025
    Abstract: Disclosed is a semiconductor device which includes a semiconductor chip and a base substrate. The semiconductor chip includes a semiconductor substrate, an interconnect layer and a high-frequency interconnect. The interconnect layer is provided on the substrate. The high-frequency interconnect is formed within the interconnect layer. The semiconductor chip is mounted onto the base substrate. An electromagnetic shield layer is provided between the high-frequency interconnect and the interconnect.
    Type: Grant
    Filed: March 3, 2008
    Date of Patent: June 9, 2009
    Assignee: NEC Electronics Corporation
    Inventor: Yasutaka Nakashiba
  • Patent number: 7539045
    Abstract: Magnetic or magnetoresistive random access memories (MRAMs) are implemented in a variety of arrangements and methods. Using one such arrangement, a matrix is implemented with magnetoresistive memory cells logically organized in rows and columns, each memory cell including a magnetoresistive element. The matrix has a set of column lines, a column line being a continuous conductive strip which is magnetically coupled to the magnetoresistive element of each of the memory cells of a column, wherein each column line has a forward column line and a return column line arranged on opposite sides of the magnetoresistive element and offset from one another for forming a return path for current in that column line.
    Type: Grant
    Filed: November 6, 2003
    Date of Patent: May 26, 2009
    Assignee: NXP B.V.
    Inventor: Hans Marc Bert Boeve
  • Patent number: 7531882
    Abstract: A method and system for providing a magnetic element that can be used in a magnetic memory is disclosed. The magnetic element includes pinned, nonmagnetic spacer, and free layers. The spacer layer resides between the pinned and free layers. The free layer can be switched using spin transfer when a write current is passed through the magnetic element. The magnetic element may also include a barrier layer, a second pinned layer. Alternatively, second pinned and second spacer layers and a second free layer magnetostatically coupled to the free layer are included. At least one free layer has a high perpendicular anisotropy. The high perpendicular anisotropy has a perpendicular anisotropy energy that is at least twenty and less than one hundred percent of the out-of-plane demagnetization energy.
    Type: Grant
    Filed: September 30, 2005
    Date of Patent: May 12, 2009
    Assignee: Grandis, Inc.
    Inventors: Paul P. Nguyen, Yiming Huai
  • Patent number: 7521264
    Abstract: Devices such as transistors, amplifiers, frequency multipliers, and square-law detectors use injection of spin-polarized electrons from one magnetic region, into another through a control region and spin precession of injected electrons in a magnetic field induced by current in a nanowire. In one configuration, the nanowire is also one of the magnetic regions and the control region is a semiconductor region between the magnetic nanowire and the other magnetic region. Alternatively, the nanowire is insulated from the control region and the two separate magnetic regions. The relative magnetizations of the magnetic regions can be selected to achieve desired device properties. A first voltage applied between one magnetic region and the other magnetic nanowire or region causes injection of spin-polarized electrons through the control region, and a second voltage applied between the ends of the nanowire causes a current and a magnetic field that rotates electron spins to control device conductivity.
    Type: Grant
    Filed: January 5, 2007
    Date of Patent: April 21, 2009
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Viatcheslav V. Osipov, Alexandre M. Bratkovski
  • Patent number: 7511351
    Abstract: In a semiconductor device having a WCSP type construction package, to increase inductance without increasing further an area conventionally occupied by a coil. A pseudo-post part 27 comprising a magnetic body is extended in a direction perpendicular to a main surface 12a of a semiconductor chip 12, on a second insulating layer 21 of a WCSP 10. A first conductive part 15a and a second conductive part 15b constructed as square frames are respectively provided so as to surround the pseudo-post part, on respective top surfaces of a second insulation layer and a third insulating layer 22 which are separated parallel to each other, in an extension direction of the pseudo-post part. A coil 100 being a substantially spiral shape conductive path is formed from, the first conductive part, the second conductive part, and a connection part 26 which electrically connects the one ends of the first and second conductive parts.
    Type: Grant
    Filed: July 27, 2005
    Date of Patent: March 31, 2009
    Assignee: Oki Electric Industry Co., Ltd.
    Inventors: Noritaka Anzai, Makoto Terui
  • Patent number: 7508041
    Abstract: A magnetic memory device includes a magnetic tunneling junction (MTJ) structure having a cylindrical shape. Elements of the MTJ structure are co-axial. The MTJ structure includes a conductive layer, an insulating layer co-axially formed around the conductive layer and a material layer formed around the insulating layer, the material layer being co-axial with the conductive layer and having a plurality of magnetic layers. The material layer includes a lower magnetic layer, a tunneling layer, and an upper magnetic layer that are sequentially stacked around and along the conductive layer.
    Type: Grant
    Filed: August 23, 2005
    Date of Patent: March 24, 2009
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jin-seo Noh, Tae-wan Kim, Hong-seog Kim, Eun-sik Kim
  • Patent number: 7501688
    Abstract: A spin injection magnetization reversal element includes a ferromagnetic fixed layer, an isolation layer and a ferromagnetic free layer. The area of contact between the ferromagnetic fixed layer and the isolation layer is larger than an area of contact between the ferromagnetic free layer and the isolation layer. The ferromagnetic fixed layer may be divided into ferromagnetic first fixed layer and ferromagnetic second fixed layer, and the isolation layer may be divided into first isolation layer and second isolation layer. The ferromagnetic first fixed layer may be arranged on one of opposed principal surfaces of the ferromagnetic free layer with the first isolation layer in between, and the ferromagnetic second fixed layer may be arranged on the other of the opposed principal surfaces of the ferromagnetic free layer with the second isolation layer in between. The element holds recorded magnetization and can reverse magnetization with a small current density.
    Type: Grant
    Filed: June 27, 2006
    Date of Patent: March 10, 2009
    Assignee: Fuji Electric Holdings Co., Ltd.
    Inventor: Akira Saito
  • Patent number: 7498656
    Abstract: An improved electromagnetic shielding structure has been discovered. In one embodiment of the invention, an apparatus includes an inductor and an electrically conductive enclosure that electromagnetically shields the inductor. The electrically conductive enclosure has an aperture at least as large as the inductor. The aperture is substantially centered around a projected surface of the inductor. The apparatus may include one or more electrically conductive links extending across the aperture and electrically coupled to the electrically conductive enclosure. The electrically conductive links reduce an effect of electromagnetic signals external to the electrically conductive enclosure on the inductor.
    Type: Grant
    Filed: March 31, 2004
    Date of Patent: March 3, 2009
    Assignee: Silicon Laboratories Inc.
    Inventors: Ligang Zhang, David Pietruszynski, Axel Thomsen, Kevin G. Smith
  • Publication number: 20090050992
    Abstract: An amorphous soft magnetic thin film material for forming shielding and keeper applications in MRAM devices. The amorphous soft magnetic material may be deposited using Physical Vapor Deposition (PVD) in the presence of a magnetic field, in order to form shielding layers and keepers in a multi-layer metallization process. The soft magnetic material may be an amorphous metallic alloy, such as CoZrX, where X may be Ta, Nb, Pd and/or Rh.
    Type: Application
    Filed: July 16, 2008
    Publication date: February 26, 2009
    Inventors: Jacques Constant Stefan KOOLS, Ming MAO, Thomas SCHNEIDER, Jinsong WANG, Michael GUTKIN
  • Publication number: 20090046502
    Abstract: A magnetic memory cell is provided. The memory cell includes a metal device, a first word line, and a second word line. The metal device includes a first magnetic layer having a first dipole; a second magnetic layer having a second dipole; and an conductive layer located between the first and second magnetic layers. The first word line is positioned near the first magnetic layer to change the direction of the first dipole. The second word line is positioned near the second magnetic layer to change the direction of the second dipole. A method of reading/writing a bit in the magnetic memory cell is also provided.
    Type: Application
    Filed: August 16, 2007
    Publication date: February 19, 2009
    Applicant: NORTHERN LIGHTS SEMICONDUCTOR CORP.
    Inventors: Tom Allen Agan, James Chyi Lai
  • Patent number: 7492021
    Abstract: A magnetic transistor includes a magnetic section, a thin semiconductor layer, a first metal terminal, a second metal terminal, and a third metal terminal. The thin semiconductor layer is disposed on the magnetic section. The first metal terminal is disposed on one end of the magnetic section, acting as a gate of the magnetic transistor and capable of providing a conductive channel in the thin semiconductor layer. The second metal terminal and the third metal terminal are disposed respectively on one end and the other end of the thin semiconductor layer, capable of creating a conductive region. While the magnetic transistor is turned on, a current path is formed between the second metal terminal and the third metal terminal via the thin semiconductor layer.
    Type: Grant
    Filed: October 16, 2006
    Date of Patent: February 17, 2009
    Assignee: Northern Lights Semiconductor Corp.
    Inventors: James Chyi Lai, Tom Allen Agan
  • Patent number: 7485937
    Abstract: A tunnel junction device capable of controlling its spin retention is provided. The tunnel junction device includes a La0.6Sr0.4MnO3-? electrode (12), a La0.6Sr0.4Mn1-yRuyO3-? electrode (14), both as ferromagnetic (including ferrimagnetic) metal materials, and a LaAlO3-? (electrically insulating layer) (13) arranged between the two electrodes (12) and (14).
    Type: Grant
    Filed: February 25, 2005
    Date of Patent: February 3, 2009
    Assignees: National Institute of Advanced Industrial Science and Technology, Japan Science and Technology Agency
    Inventors: Yoshinori Tokura, Masashi Kawasaki, Hiroshi Akoh, Hiroyuki Yamada, Yuji Ishii, Hiroshi Sato, Yoshio Kaneko
  • Patent number: 7485938
    Abstract: It is possible to perform a writing operation with low power consumption and a low current, and enhance reliability without causing element breakdown. There are provided a first magnetization-pinned layer including at least one magnetic film in which a magnetization direction is pinned; a second magnetization-pinned layer including at least one magnetic film in which a magnetization direction is pinned; a magnetic recording layer formed between the first magnetization-pinned layer and the second magnetization-pinned layer and including at least one magnetic film in which a magnetization direction is changeable by injecting spin-polarized electrons; a tunnel barrier layer formed between the first magnetization-pinned layer and the magnetic recording layer; and a nonmagnetic intermediate layer formed between the magnetic recording layer and the second magnetization-pinned layer.
    Type: Grant
    Filed: September 15, 2006
    Date of Patent: February 3, 2009
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yoshiaki Saito, Hideyuki Sugiyama
  • Patent number: 7479690
    Abstract: Strip metallic thin films each having a width of 180 ?m or so are disposed in parallel at intervals of 10 ?m to 50 ?m on the surface of a protection layer formed on the silicon substrate and at their corresponding spots located on the upper side of an analog circuit formed in a silicon substrate. These strip metallic thin films are connected to one another at their ends or centers to form a comb-like shield section and one end thereof is connected to its corresponding external connecting post. Incidentally, the shield section is formed by copper plating in the same process as redistribution wirings that connect electrode pads at an outer peripheral portion of the silicon substrate to their corresponding external connecting posts.
    Type: Grant
    Filed: July 18, 2006
    Date of Patent: January 20, 2009
    Assignee: Oki Electric Industry Co., Ltd.
    Inventor: Yasushi Shiraishi
  • Patent number: 7476953
    Abstract: An integrated sensor has a magnetic field sensing element and first and second relatively high magnetically permeable members forming a gap, wherein the magnetic field element is disposed within the gap. The magnetically permeable members provide an increase in the flux experienced by the magnetic field sensing element in response to a magnetic field. The integrated sensor can be used as a current sensor, a proximity detector, or a magnetic field sensor.
    Type: Grant
    Filed: February 4, 2005
    Date of Patent: January 13, 2009
    Assignee: Allegro Microsystems, Inc.
    Inventors: William P. Taylor, Richard Dickinson, Michael C. Doogue, Sandra R. Pinelle
  • Patent number: 7471492
    Abstract: A magnetoresistive element has a first magnetic layer and a second magnetic layer separate from each other, the first magnetic layer and the second magnetic layer each having a magnetization whose direction is substantially pinned, and a non-magnetic conductive layer formed in contact with the first magnetic layer and the second magnetic layer and electrically connecting the first and second magnetic layers, the non-magnetic conductive layer forming a path of spin-polarized electrons from one of the magnetic layer to the other magnetic layer, the non-magnetic conductive layer comprising a portion located between the first magnetic layer and the second magnetic layer, the portion being a sensing area.
    Type: Grant
    Filed: July 22, 2004
    Date of Patent: December 30, 2008
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hideaki Fukuzawa, Hiromi Yuasa, Susumu Hashimoto, Hitoshi Iwasaki
  • Patent number: 7468542
    Abstract: A fast and very low-power-consuming nonvolatile memory. A nonvolatile magnetic memory includes a high-output tunnel magnetoresistive device, in which spin-transfer torque is used for writing. A tunnel magnetoresistive device has a structure such that a ferromagnetic film of a body-centered cubic structure containing Co, Fe, and B, a MgO insulator film of a rock-salt structure oriented in (100), and a ferromagnetic film are stacked.
    Type: Grant
    Filed: July 27, 2006
    Date of Patent: December 23, 2008
    Assignee: Hitachi, Ltd.
    Inventors: Jun Hayakawa, Hideo Ohno, Shoji Ikeda
  • Patent number: 7459769
    Abstract: It is an object of the invention to relax magnetic saturation and realize a high-performance magnetic shield effect that is suitable for magnetic devices such as an MRAM. A magnetic shield member of the invention is suitable for a magnetic memory device in which a magnetic random access memory (MRAM) consisting of a TMR element formed by stacking a magnetization fixed layer with a direction of magnetization fixed and a magnetic layer, in which a direction of magnetization can be changed, via a tunnel barrier layer is sealed by a sealing material such as resin.
    Type: Grant
    Filed: February 8, 2005
    Date of Patent: December 2, 2008
    Assignee: Sony Corporation
    Inventors: Yoshihiro Kato, Yoshinori Ito, Tatsushiro Hirata, Katsumi Okayama, Kaoru Kobayashi
  • Patent number: 7449760
    Abstract: The present invention provides a magnetic memory device capable of performing stable information writing operation by efficiently using a magnetic field generated by current flowing in a conductor and stably holding written information. A magnetic memory device includes: magnetic yoke disposed in correspondence with a region in which a write bit line and a write word line cross each other and constructed so as to surround partially or entirely the periphery of the lines; and a stacked body including a second magnetic layer of which magnetization direction changes according to an external magnetic field, and magnetically coupled to the magnetic yoke. The second magnetic layer has coercive force larger than that of the magnetic yoke, and coercive force of the magnetic yoke increases toward the second magnetic layer. Thus, the influence by remanent magnetization of the magnetic yoke can be suppressed, and the magnetization direction of the second magnetic layer can be stably held.
    Type: Grant
    Filed: September 7, 2004
    Date of Patent: November 11, 2008
    Assignee: TDK Corporation
    Inventor: Hitoshi Hatate
  • Patent number: 7432573
    Abstract: A surface-spintronic device operating on a novel principles of operations may be implemented as a spin conducting, a spin switching or a spin memory device. It includes a magnetic atom thin film (13) layered on a surface of a solid crystal (12) and a drain and a source electrodes (14)and (15) disposed at two locations on the magnetic atom thin film, respectively, whereby a spin splitting surface electronic state band formed in a system comprising said solid crystal(12) surface and said magnetic atom thin film (13) is utilized to obtain a spin polarized current flow. With electrons spin-polarized in a particular direction injected from the source electrode (15), controlling the direction of magnetization of the magnetic atom thin film (13) allows switching on and off the conduction of such injected electrons therethrough.
    Type: Grant
    Filed: June 23, 2004
    Date of Patent: October 7, 2008
    Assignee: Japan Science and Technology Agency
    Inventors: Hideaki Kasai, Hiroshi Nakanishi, Tomoya Kishi
  • Patent number: 7423328
    Abstract: The method for reducing word line currents in magnetoresistive random access memory (MRAM) includes disposing the MRAM bit between a pair of word lines according to a magnetic field strength is increased when a distance between a magnetic section and its corresponding word line is decreased.
    Type: Grant
    Filed: October 6, 2006
    Date of Patent: September 9, 2008
    Assignee: Northern Lights Semiconductor Corp.
    Inventors: James Chyi Lai, Tom Allen Agan
  • Patent number: 7411816
    Abstract: An MRAM circuit includes an MRAM array having a plurality of operational MRAM elements and a reference cell made up of one or more reference MRAM elements. A plurality of program lines within a first region are cladded with a flux-concentrating layer configured to focus a generated magnetic field while the portions of the program lines within a second region are uncladded so that the generated magnetic field is unfocused. Generally, the first region is associated with the operational MRAM elements and the second region is associated with the reference cell.
    Type: Grant
    Filed: January 19, 2006
    Date of Patent: August 12, 2008
    Assignee: Honeywell International Inc.
    Inventor: Eric T. Leung
  • Patent number: 7411263
    Abstract: A magnetic memory device includes a magnetoresistive element and a first wiring layer. The magnetoresistive element includes a fixed layer, a recording layer, and a non-magnetic layer interposed therebetween. The first wiring layer extends in a first direction and generates a magnetic field for recording data in the magnetoresistive element. The recording layer includes a base portion extending in a second direction rotated from the first direction by an angle falling within a range of more than 0° to not more than 20°, and first and second projections projecting from the first and second sides of the base portion in a third direction perpendicular to the second direction. The third and fourth sides of the base portion are inclined with respect to the third direction in the same rotational direction as a rotational direction in which the second direction is rotated.
    Type: Grant
    Filed: March 27, 2006
    Date of Patent: August 12, 2008
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Masahiko Nakayama, Tadashi Kai, Sumio Ikegawa, Yoshiaki Fukuzumi, Tatsuya Kishi
  • Patent number: 7411262
    Abstract: The present invention seeks to reduce the amount of current required for a write operation by using a process for forming the read conductor within a recessed write conductor, the write conductor itself formed within a trench of an insulating layer. The present invention protects the MTJ from the voltages created by the write conductor by isolating the write conductor and enabling the reduction of current necessary to write a bit of information.
    Type: Grant
    Filed: August 29, 2005
    Date of Patent: August 12, 2008
    Assignee: Micron Technology, Inc.
    Inventor: James G. Deak
  • Patent number: 7411264
    Abstract: The present invention provides a thin-film structure that includes an etch-stop layer having a first side and a second side, a patterned compensation layer for dissipating thermal energy, and an etch-vulnerable layer, where the etch-stop layer substantially impedes etching. The patterned compensation layer is adjacent the first side of the etch-stop layer, and the etch-vulnerable layer is adjacent the second side of the etch-stop layer.
    Type: Grant
    Filed: November 18, 2004
    Date of Patent: August 12, 2008
    Assignee: Seagate Technology LLC
    Inventors: Mallika Kamarajugadda, Michael C. Kautzky, Stacy C. Wakham, David C. Seets, Arun Natarajun
  • Patent number: 7405085
    Abstract: An amorphous soft magnetic thin film material for forming shielding and keeper applications in MRAM devices. The amorphous soft magnetic material may be deposited using Physical Vapor Deposition (PVD) in the presence of a magnetic field, in order to form shielding layers and keepers in a multi-layer metallization process. The soft magnetic material may be an amorphous metallic alloy, such as CoZrX, where X may be Ta, Nb, Pd and/or Rh.
    Type: Grant
    Filed: September 15, 2004
    Date of Patent: July 29, 2008
    Assignee: Veeco Instruments, Inc.
    Inventors: Jacques Constant Stefan Kools, Ming Mao, Thomas Schneider, Jinsong Wang, Michael Gutkin
  • Patent number: 7397694
    Abstract: A magnetic memory array. A first bit line provides a first writing magnetic field to a magnetic memory cell. A second bit line provides a second writing magnetic field to a reference magnetic memory cell. A word line provides a third writing magnetic field to the magnetic memory cell and a fourth writing magnetic field to the reference magnetic memory cell. The third writing magnetic field exceeds the fourth writing magnetic field.
    Type: Grant
    Filed: January 26, 2006
    Date of Patent: July 8, 2008
    Assignee: Industrial Technology Research Institute
    Inventors: Chi-Ming Chen, Chien-Chung Hung, Young-Shying Chen, Lien-Chang Wang
  • Publication number: 20080157240
    Abstract: A seek-scan probe (SSP) memory including a recess cavity to self-align magnets includes a frame, a movable platform movably coupled to the frame, a coil coupled to the movable platform, and a cap wafer having coupled to the frame. The cap wafer includes a recess cavity to receive a magnet that produces a magnetic field. By energizing the coil while in the magnetic field a physical force is produced that is translated into movement of the movable platform.
    Type: Application
    Filed: December 29, 2006
    Publication date: July 3, 2008
    Inventor: Deguang Zhu
  • Patent number: 7378716
    Abstract: A magnetic tunneling junction (MTJ) cell includes a free magnetic layer having a low magnetic moment, and a magnetic random access memory (MRAM) includes the MTJ cell. The MTJ cell of the MRAM includes a lower electrode, a lower magnetic layer, a tunneling layer, an upper magnetic layer and an upper electrode, which are sequentially stacked on the lower electrode. The upper magnetic layer includes a free magnetic layer having a thickness of about 5 nm or less. The MTJ cell may have an aspect ratio of about 2 or less, and the free magnetic layer may have a magnetic moment of about 800 emu/cm3 or less.
    Type: Grant
    Filed: November 15, 2004
    Date of Patent: May 27, 2008
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Tae-wan Kim, Sang-jin Park, In-jun Hwang
  • Publication number: 20080116535
    Abstract: A shield structure for shielding an electromagnetic-field-susceptible region of a semiconductor component (e.g., a magnetoresistive random access memory, or “MRAM”) includes a stress-relief layer (e.g., electroplated Ni) formed over the semiconductor device in a shield region substantially corresponding to the electromagnetic-field-susceptible region, and a magnetic shield layer (e.g., an electroplated PERMALLOY or MUMETAL layer) mechanically coupled to the stress-relief layer within the shield region, wherein the magnetic shield layer has a stress condition that is substantially opposite of that of the stress-relief layer.
    Type: Application
    Filed: November 21, 2006
    Publication date: May 22, 2008
    Inventors: Jaynal A. Molla, Gregory W. Grynkewich, Eric J. Salter
  • Patent number: 7375388
    Abstract: The present invention provides a method of fabricating a portion of a memory cell, the method comprising providing a first conductor in a trench which is provided in an insulating layer and flattening an upper surface of the insulating layer and the first conductor, forming a material layer over the flattened upper surface of the insulating layer and the first conductor and flattening an upper portion of the material layer while leaving intact a lower portion of the material layer over the insulating layer and the first conductor.
    Type: Grant
    Filed: December 15, 2003
    Date of Patent: May 20, 2008
    Assignee: Micron Technology, Inc.
    Inventors: Donald L. Yates, Joel A. Drewes
  • Patent number: 7375405
    Abstract: A magnetoresistance effect (MR) device incorporating a spin valve film, and a magnetic head, a magnetic head assembly and a magnetic recording/reproducing system incorporating the MR device, wherein the magnetization direction of a free layer is at a certain angle to the magnetization direction of a second ferromagnetic layer therein when the applied magnetic field is zero. A pinned magnetic layer includes a pair of ferromagnetic films antiferromagnetically coupled to each other via a coupling film existing therebetween. The magnetization direction of either one of the pair of ferromagnetic films constituting the pinned magnetic layer is maintained, and a nonmagnetic high-conductivity layer is disposed adjacent to a first ferromagnetic layer on the side opposite to the side on which the first ferromagnetic layer is contacted with a nonmagnetic spacer layer. With that constitution, the device has extremely high sensitivity, and the bias point in the device is well controlled.
    Type: Grant
    Filed: March 15, 2005
    Date of Patent: May 20, 2008
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hideaki Fukuzawa, Yuzo Kamiguchi, Katsuhiko Koui, Shin-ichi Nakamura, Hitoshi Iwasaki, Kazuhiro Saito, Hiromi Fuke, Masatoshi Yoshikawa, Susumu Hashimoto, Masashi Sahashi
  • Patent number: 7367111
    Abstract: A method and structure for a spin valve transistor (SVT) comprises a magnetic field sensor, an insulating layer adjacent the magnetic field sensor, a bias layer adjacent the insulating layer, a non-magnetic layer adjacent the bias layer, and a ferromagnetic layer over the non-magnetic layer, wherein the insulating layer and the non-magnetic layer comprise antiferromagnetic materials. The magnetic field sensor comprises a base region, a collector region adjacent the base region, an emitter region adjacent the base region, and a barrier region located between the base region and the emitter region. The bias layer is between the insulating layer and the non-magnetic layer. The bias layer is magnetic and is at least three times the thickness of the magnetic materials in the base region.
    Type: Grant
    Filed: January 25, 2006
    Date of Patent: May 6, 2008
    Assignee: Hitachi Global Storage Technologies Netherland BV
    Inventors: Robert E. Fontana, Jr., Jeffrey S. Lille
  • Patent number: 7339245
    Abstract: A Hall sensor on a semiconductor substrate includes a Hall plate in the semiconductor substrate, where the Hall plate includes a first zone having a first conduction type. The semiconductor substrate also include a second zone having a second conduction type. A space-charge zone in the semiconductor substrate separates the first zone and the second zone, first contacts supply a control current to the first zone, and second contacts supply a compensation current to the second zone.
    Type: Grant
    Filed: August 14, 2003
    Date of Patent: March 4, 2008
    Assignee: Austriamicrosystems AG
    Inventor: Thomas Mueller
  • Patent number: 7335961
    Abstract: An MTJ element is formed between orthogonal word and bit lines. The bit line is a composite line which includes a high conductivity layer and a soft magnetic layer under the high conductivity layer. During operation, the soft magnetic layer concentrates the magnetic field of the current and, due to its proximity to the free layer, it magnetically couples with the free layer in the MTJ. This coupling provides thermal stability to the free layer magnetization and ease of switching and the coupling may be further enhanced by inducing a shape or crystalline anisotropy into the free layer during formation.
    Type: Grant
    Filed: August 25, 2005
    Date of Patent: February 26, 2008
    Assignees: Headway Technologies, Inc., Applied Spintronics, Inc.
    Inventors: Yimin Guo, Tai Min, Pokang Wang, Xi Zeng Shi
  • Patent number: 7332781
    Abstract: The invention concerns a magnetic memory, whereof each memory point consists of a magnetic tunnel junction (60), comprising: a magnetic layer, called trapped layer (61), whereof the magnetization is rigid; a magnetic layer, called free layer (63), whereof the magnetization may be inverse; and insulating layer (62), interposed between the free layer (73) and the trapped layer (71) and respectively in contact with said two layers. The free layer (63) is made with an amorphous or nanocrytallized alloy based on rare earth or a transition metal, the magnetic order of said alloy being of the ferromagnetic type, said free layer having a substantially planar magnetization.
    Type: Grant
    Filed: September 19, 2002
    Date of Patent: February 19, 2008
    Assignee: Centre National de la Recherche Scientifique
    Inventors: Jean-Pierre Nozieres, Laurent Ranno, Yann Conraux
  • Patent number: 7329935
    Abstract: Low power magnetoresistive random access memory elements and methods for fabricating the same are provided. In one embodiment, a magnetoresistive random access device has an array of memory elements. Each element comprises a fixed magnetic portion, a tunnel barrier portion, and a free SAF structure. The array has a finite magnetic field programming window Hwin represented by the equation Hwin?(Hsat??sat)?(Hsw+?sw), where Hsw is a mean switching field for the array, Hsat is a mean saturation field for the array, and Hsw for each memory element is represented by the equation HSW??{square root over (HkHSAT)}, where Hk represents a total anisotropy and HSAT represents an anti-ferromagnetic coupling saturation field for the free SAF structure of each memory element. N is an integer greater than or equal to 1. Hk, HSAT, and N for each memory element are selected such that the array requires current to operate that is below a predetermined current value.
    Type: Grant
    Filed: October 16, 2006
    Date of Patent: February 12, 2008
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Nicholas D. Rizzo, Renu W. Dave, Bradley N. Engel, Jason A. Janesky, JiJun Sun
  • Patent number: 7323732
    Abstract: An MRAM array having enhanced magnetoresistance includes a spin filtering element connected by a spin hold element to the MRAM cell structures. A spin filtering element may serve several MRAM cell structures, by connecting the spin filtering element to a series of MRAM cell structures by a spin hold wire, or a spin filtering element and a spin hold element may be formed as adjacent layers in each MRAM cell stack.
    Type: Grant
    Filed: March 3, 2004
    Date of Patent: January 29, 2008
    Assignee: Macronix International Co., Ltd.
    Inventors: ChiaHua Ho, Hsiang-Lan Lung
  • Patent number: 7312506
    Abstract: A memory cell structure. A first conductive line is cladded by at least two first ferromagnetic layers respectively having a first easy axis and a second easy axis, a nano oxide layer located between the first ferromagnetic layers, and a first pinned ferromagnetic layer. The first and second easy axes are 90 degree twisted-coupled with the first easy axis parallel to the length of the first conductive line and the second easy axis perpendicular to the length of the first conductive line. A storage device is adjacent to the first conductive line, receiving a magnetic field generated from a current flowing through the first conductive line.
    Type: Grant
    Filed: March 30, 2005
    Date of Patent: December 25, 2007
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yu-Jen Wang, Chih-Huang Lai, Denny Tang, Wen Chin Lin
  • Patent number: 7309888
    Abstract: A thin film sensing device operates based on a spin polarized current. The spin device includes ferromagnetic layers characterized by different coercivities and/or magnetization states, and one or more low transmission barriers in between. The device is further configured so that the spin polarized current flows at least in part in a direction perpendicular to the aforementioned layers.
    Type: Grant
    Filed: March 14, 2006
    Date of Patent: December 18, 2007
    Assignee: Seagate Technology LLC
    Inventor: Mark B. Johnson
  • Patent number: 7307302
    Abstract: It is possible to obtain excellent heat stability even though the element is miniaturized and keep stable magnetic domains even though switching is repeated any number of times. A magneto-resistive effect element includes: a magnetization-pinned layer including a magnetic film having a spin moment oriented in a direction perpendicular to a film surface thereof and pinned in the direction; a magnetic recording layer having a spin moment oriented in a direction perpendicular to a film surface thereof; a nonmagnetic layer formed between the magnetization-pinned layer and the magnetic recording layer; and an anti-ferromagnetic film formed on at least side surfaces of the magnetization-pinned layer.
    Type: Grant
    Filed: July 9, 2004
    Date of Patent: December 11, 2007
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Yoshiaki Saito
  • Patent number: 7304360
    Abstract: A super-paramagnetic cladding layer formed on from 1 to 3 sides of a conductive line in a magnetic device is disclosed. The cladding layer is made of “x” ML/SL stacks in which x is between 5 and 50, SL is an amorphous AlOx seed layer, and ML is a composite with a soft magnetic layer comprised of discontinuous particles less than 2 nm in size on the seed layer and a capping layer of Ru, Ta, or Cu on the soft magnetic layer. Fringing fields and hysteresis effects from continuous ferromagnetic cladding layers associated with switching the magnetic state of an adjacent MTJ are totally eliminated because of the super-paramagnetic character of the soft magnetic layer at room temperature. The soft magnetic layer has near zero magnetostriction, very high susceptibility, and may be made of Ni˜80Fe˜20, Ni˜30Fe˜70, Co˜90Fe˜10, or CoNiFe.
    Type: Grant
    Filed: July 12, 2005
    Date of Patent: December 4, 2007
    Assignee: MagIC Technologies, Inc.
    Inventors: Yimin Guo, Po-Kang Wang
  • Patent number: 7285811
    Abstract: The present invention provides an MRAM cell which minimizes the occurrence of electrical shorts during fabrication. A first conductor is provided in a trench in an insulating layer and an upper surface of the insulating layer and the first conductor is planarized. A first dielectric layer is deposited over the first conductor and insulating layer to a thickness at least greater than the thickness of a desired MRAM cell. The first dielectric layer is patterned and etched to form an opening over the first conductor for the cell shapes. The magnetic layers comprising the MRAM cell are consecutively formed within the cell shapes and the first dielectric layer.
    Type: Grant
    Filed: August 31, 2006
    Date of Patent: October 23, 2007
    Assignee: Micron Technology, Inc.
    Inventors: Donald L. Yates, Garry A. Mercaldi
  • Patent number: 7279762
    Abstract: The invention includes a construction comprising an MRAM device between a pair of conductive lines. Each of the conductive lines can generate a magnetic field encompassing at least a portion of the MRAM device. Each of the conductive lines is surrounded on three sides by magnetic material to concentrate the magnetic fields generated by the conductive lines at the MRAM device. The invention also includes a method of forming an assembly containing MRAM devices. A plurality of MRAM devices are formed over a substrate. An electrically conductive material is formed over the MRAM devices, and patterned into a plurality of lines. The lines are in a one-to-one correspondence with the MRAM devices and are spaced from one another. After the conductive material is patterned into lines, a magnetic material is formed to extend over the lines and within spaces between the lines.
    Type: Grant
    Filed: December 5, 2005
    Date of Patent: October 9, 2007
    Assignee: Micron Technology, Inc.
    Inventors: Hasan Nejad, James G. Deak
  • Patent number: 7262474
    Abstract: In a magnetic memory device, and a method of manufacturing the same, the magnetic memory device includes a switching device, and a magnetic tunneling junction (MTJ) cell connected to the switching device, the MTJ cell including a lower electrode connected to the switching device and a lower magnetic layer, a tunneling film containing fluorine, an upper magnetic layer, and a capping layer, sequentially stacked on the lower electrode.
    Type: Grant
    Filed: January 31, 2005
    Date of Patent: August 28, 2007
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Tae-wan Kim, Kook-rin Char, Dae-sik Kim
  • Patent number: 7262449
    Abstract: A magnetic random access memory according to an aspect of the present invention comprises a first magnetic layer in which a magnetization state is fixed, a second magnetic layer which has a shape different from that of the first magnetic layer and in which a magnetization state varies in accordance with write data, a non-magnetic layer which is arranged between the first magnetic layer and the second magnetic layer, and a third magnetic layer which surrounds the second magnetic layer.
    Type: Grant
    Filed: May 18, 2004
    Date of Patent: August 28, 2007
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Takeshi Kajiyama
  • Patent number: 7256098
    Abstract: A method of making a memory device and a memory device is described. In one embodiment, a method of manufacturing a memory device is described. The method includes providing a substrate having a tunneling layer deposited on a main surface and having a first conductive lines arranged on the tunneling layer running in a first direction. A layer of dielectric material is deposited on the first conductive lines. A control gate layer is deposited. The first conductive lines are patterned to produce gate stacks. Dielectric material is deposited in between the gate stacks. The gate stacks are partially removed to uncover floating gate electrodes in region of selection transistor lines to be prepared creating selection transistor line recesses running in the second direction. The selection transistor line recesses are filled with a conductive material to create the selection transistor lines.
    Type: Grant
    Filed: April 11, 2005
    Date of Patent: August 14, 2007
    Assignee: Infineon Technologies AG
    Inventor: Josef Willer
  • Patent number: 7250662
    Abstract: A conductor with improved magnetic field per current ratio is disclosed. The conductor includes a magnetic liner lining a second surface and sides thereof. The magnetic liner is preferably a super-paramagnet with high susceptibility or a ferromagnet with a microstructure where the size of the non-exchanged coupled micro domains is so small that their energy content is close to or small compared to kT that such films have super-paramagnetic properties and essentially behave like a paramagnet with high susceptibility.
    Type: Grant
    Filed: July 31, 2003
    Date of Patent: July 31, 2007
    Assignees: International Business Machines Corporation, Infineon Technologies North America Corporation
    Inventors: Snorri T. Ingvarsson, Rainer E. R. Leuschner, Yu Lu
  • Patent number: 7211874
    Abstract: An MTJ MRAM cell element, whose free layer has a shape induced magnetic anisotropy, is formed between orthogonal word and bit lines. The bit line is a composite line which includes a high conductivity current carrying layer and a soft adjacent magnetic layer (SAL). During operation, the soft magnetic layer concentrates the magnetic field of the current and, due to its proximity to the free layer, it magnetically couples with the free layer to produce two magnetization states of greater and lesser stability. During switching, the layer is first placed in the less stable state by a word line current, so that a small bit line current can switch its magnetization direction. After switching, the state reverts to its more stable form as a result of magnetostatic interaction with the SAL, which prevents it from being accidentally rewritten when it is not actually selected and also provides stability against thermal agitation.
    Type: Grant
    Filed: April 6, 2004
    Date of Patent: May 1, 2007
    Assignees: Headway Technologies, Inc., Applied Spintronics, Inc.
    Inventors: Yimin Guo, Po-Kang Wang, Xizeng Shi, Tai Min