Abstract: A magnetic random access memory with lower switching field is provided. The memory includes a first antiferromagnetic layer, a pinned layer formed on the first antiferromagnetic layer, a tunnel barrier layer formed on the pinned layer, a ferromagnetic free layer formed on the tunnel barrier layer, and a multi-layered metal layer. The multi-layered metal layer is formed by at least one metal layer, where the direction of the anisotropy axis of the antiferromagnetic layer and the ferromagnetic layer and that of the ferromagnetic free layer are arranged orthogonally. The provided memory has the advantage of lowering the switching field of the ferromagnetic layer, and further lowering the writing current.

Abstract: A vertical Hall effect apparatus, including methods thereof. A substrate layer can be provided upon which an epitaxial layer is formed. The epitaxial layer is surrounded vertically by one or more isolation layers. Additionally, an oxide layer can be formed above the epitaxial layer. A plurality of Hall effect elements can be formed within the epitaxial layer(s) and below the oxide layer, wherein the Hall effect elements sense the components of an arbitrary magnetic field in the plane of the wafer and perpendicular to the current flow in the hall element. A plurality of field plates can be formed above the oxide layer to control the inherited offset due to geometry control and processing of the vertical Hall effect apparatus, while preventing the formation of an output voltage of the vertical Hall effect apparatus at zero magnetic fields thereof.

Abstract: A method of fabricating a flash memory cell having a split gate structure. A sacrificial layer is formed on a floating gate layer formed on a semiconductor substrate. The sacrificial layer is etched to form an opening exposing a portion of the floating gate layer. A gate interlayer insulating layer pattern is formed inside the opening. After removing the sacrificial layer pattern and etching the floating gate layer (using the gate interlayer insulating layer pattern as an etch mask), a floating gate is formed under the gate interlayer insulating layer pattern. A control gate is formed overlapping a portion of the floating gate.

Abstract: A magnetoresistive memory element includes a stacked structure with a ferromagnetic reference region including a fixed magnetization; a ferromagnetic free region including a free magnetization that is free to be switched between oppositely aligned directions with respect to an easy axis thereof; and a tunneling barrier made of a non-magnetic material. The ferromagnetic reference and free regions and the tunneling barrier together form a magnetoresistive tunneling junction. The ferromagnetic free region includes a plurality of N ferromagnetic free layers being magnetically coupled such that magnetizations of adjacent ferromagnetic free layers are in antiparallel alignment, where N is an integer greater than or equal to two. The ferromagnetic free region further includes at least one ferromagnetic decoupling layer including frustrated magnetization in orthogonal alignment to ferromagnetic free layer magnetizations and being arranged in between adjacent ferromagnetic free layers.

Abstract: This invention proposes a stable magnetic memory device that is equipped with a storage cell having a MTJ, wherein variation in the coercive force (Hc) of a ferromagnetic free layer is suppressed, and a switching characteristic of a bit of a MRAM is improved, and there is no write error. Namely in a magnetic memory device equipped with a first wiring, a second wiring (bit line) intersecting with the first wiring, and a storage cell for writing/reading information of a magnetic spin at an intersecting area of the first wiring and the second wiring, a partial sidewall portion electrically connecting to the storage cell of the second wiring (bit line) has a forward tapered form having a contact angle relative to a top surface of the storage cell being 45 degrees or more.

Abstract: A ultrathin magnetoelectric transducer and its manufacturing method are provided which enable the quality of mounting to be inspected nondestructively, and can reduce a footprint. The magnetoelectric transducer has a substrate composed of a nonmagnetic substrate, and includes bottom surface connecting electrodes whose leads have a first thickness, and side electrodes which are exposed by dicing and have the first thickness. A more sensitive Hall element has a high-permeability magnetic substrate as the substrate, and includes the bottom surface connecting electrodes whose leads have the first thickness, and the side electrodes exposed by the dicing and having the first thickness. The bottom surface connecting electrodes of the leads with the first thickness are formed across the internal electrodes of adjacent magnetoelectric transducers with maintaining the first thickness. The side electrodes with the first thickness are formed by cutting the center between the adjacent magnetoelectric transducers.

Abstract: A magnetic element for a high-density memory array includes a resettable layer and a storage layer. The resettable layer has a magnetization that is set in a selected direction by at least one externally generated magnetic field. The storage layer has at least one magnetic easy axis and a magnetization that changes direction based on the spin-transfer effect when a write current passes through the magnetic element. An alternative embodiment of the magnetic element includes an additional multilayer structure formed from a tunneling barrier layer, a pinned magnetic layer and an antiferromagnetic layer that pins the magnetization of the pinned layer in a predetermined direction. Another alternative embodiment of the magnetic element includes an additional multilayer structure that is formed from a tunneling barrier layer and a second resettable layer having a magnetic moment that is different from the magnetic moment of the resettable layer of the basic embodiment.

Abstract: Devices such as transistors, amplifiers, frequency multipliers, and square-law detectors use injection of spin-polarized electrons from one magnetic region, into another through a control region and spin precession of injected electrons in a magnetic field induced by current in a nanowire. In one configuration, the nanowire is also one of the magnetic regions and the control region is a semiconductor region between the magnetic nanowire and the other magnetic region. Alternatively, the nanowire is insulated from the control region and the two separate magnetic regions. The relative magnetizations of the magnetic regions can be selected to achieve desired device properties. A first voltage applied between one magnetic region and the other magnetic nanowire or region causes injection of spin-polarized electrons through the control region, and a second voltage applied between the ends of the nanowire causes a current and a magnetic field that rotates electron spins to control device conductivity.

Abstract: Embodiments of the invention provide a polarization rotator. The polarization rotator may be integrated with a waveguide on a substrate, and may include a ferromagnetic semiconductor layer on the substrate, a first doped layer on the ferromagnetic semiconductor layer, and a second doped layer on the first doped layer.

Abstract: A method of forming a magneto-resistive memory element includes forming a groove in a layer of insulating material. A liner is formed conformably within the groove and the groove is filled with copper and then planarized. The electrically conductive material is provided an upper surface that is recessed relative to the upper surface of the layer of insulating material. A cap, which can be conductive (e.g., Ta) or resistive (e.g., TiAIN), is disposed over the electrically conductive material and within the groove. A surface of the cap that faces away from the electrically conductive material, is formed with an elevation substantially equal to that of the edge of the liner, or the cap can extend over the liner edge. At least one layer of magneto-resistive material is disposed over a portion of the cap. Advantageously, the cap can protect the copper line from harmful etch processes required for etching a MRAM stack, while keeping the structure planar after CMP.

Abstract: It is possible to perform a writing operation with low power consumption and a low current, and enhance reliability without causing element breakdown. There are provided a first magnetization-pinned layer including at least one magnetic film in which a magnetization direction is pinned; a second magnetization-pinned layer including at least one magnetic film in which a magnetization direction is pinned; a magnetic recording layer formed between the first magnetization-pinned layer and the second magnetization-pinned layer and including at least one magnetic film in which a magnetization direction is changeable by injecting spin-polarized electrons; a tunnel barrier layer formed between the first magnetization-pinned layer and the magnetic recording layer; and a nonmagnetic intermediate layer formed between the magnetic recording layer and the second magnetization-pinned layer.

Abstract: A method of forming an MTJ memory cell and/or an array of such cells is provided wherein each such cell has a small circular horizontal cross-section of 1.0 microns or less in diameter and wherein the ferromagnetic free layer of each such cell has a magnetic anisotropy produced by a magnetic coupling with a thin antiferromagnetic layer that is formed on the free layer. The MTJ memory cell so provided is far less sensitive to shape irregularities and edge defects than cells of the prior art.

Abstract: A semiconductor apparatus includes lower conductive film strips, an inter-layer insulating layer, implanted conductive members, and upper conductive film strips. The lower conductive film strips are formed in a pattern closely adjacent in a line width orientation, electrically separated from each other. The inter-layer insulating layer is formed the lower conductive film strips. The implanted conductive members are implanted in connection holes formed in the inter-layer insulating layer at positions corresponding to both edge sides of the lower conductive film strips. The upper conductive film strips are formed on the implanted conductive members and the inter-layer insulating layer to connect the lower conductive film strips in series so that the lower conductive film strips, the implanted conductive members, and the upper conductive film strips form an electric coil.

Abstract: A shielding arrangement for protecting a circuit containing magnetically sensitive materials from external stray magnetic fields. A shield of a material having a relatively high permeability is formed over the magnetically sensitive materials using thin film deposition techniques. Alternatively, a planar shield is affixed directly to a surface of semiconductor die containing an integrated circuit structure.

Abstract: A magnetoresistive or magnetic memory element and a magnetic random access memory having one or more magnetic memory elements. The memory element includes a magnetic tunnel junction including first and a second magnetic layers. The first magnetic layer having a free magnetization. The free magnetization of the first magnetic layer is magnetically coupled to a first current line and a second current line for switching the free magnetization, and a mechanism for applying a static magnetic offset field in the direction of at least one of the first and second current lines.

Abstract: In the method of making a thin-film magnetic head in accordance with the present invention, an alignment mark is electrically connected to a multilayer film which will later become a TMR film. Therefore, when the alignment mark is irradiated with a position correcting electron beam in order to correct a drawing position in the subsequent step of electron beam lithography, electric charges of the electron beam flow into the multilayer film without staying in the alignment mark. As a consequence, the position correcting electron beam does not lose its straightforwardness, whereby the drawing position in electron beam lithography can be corrected accurately.

Abstract: The semiconductor device includes a multilevel interconnection formed on a semiconductor substrate. The multilevel interconnection includes a plurality of wiring layers each of which is insulated by an insulating layer. A metal member is formed as a shielding film in a same plane as a wiring layer. As a result, the shielding layer can be formed without increasing the number of process steps.

Abstract: In a semiconductor device having a WCSP type construction package, to increase inductance without increasing further an area conventionally occupied by a coil. A pseudo-post part 27 comprising a magnetic body is extended in a direction perpendicular to a main surface 12a of a semiconductor chip 12, on a second insulating layer 21 of a WCSP 10. A first conductive part 15a and a second conductive part 15b constructed as square frames are respectively provided so as to surround the pseudo-post part, on respective top surfaces of a second insulation layer and a third insulating layer 22 which are separated parallel to each other, in an extension direction of the pseudo-post part. A coil 100 being a substantially spiral shape conductive path is formed from, the first conductive part, the second conductive part, and a connection part 26 which electrically connects the one ends of the first and second conductive parts.

Abstract: A current-in-plane magnetic sensor comprises a sensor stack including first and second layers of ferromagnetic material, a first nano-oxide layer positioned adjacent to the first layer of ferromagnetic material, and a layer of non-magnetic material positioned between the first and second layers of ferromagnetic material, wherein the thickness of the non-magnetic layer is selected to provide antiferromagnetic coupling between the first and second ferromagnetic layers, a magnetic field source for biasing the directions of magnetization of the first and second layers of ferromagnetic material in directions approximately 90° with respect to each other, a first lead connected to a first end of the sensor stack, and a second lead connected to a second end of the sensor stack. Disc drives that use the current-in-plane magnetic sensor are also included.

Abstract: A Hall element is provided with a segmented field plate. Dynamic bias control is applied to the segments of the field plate. In one embodiment, a feedback signal is derived from an amplified output of the Hall element. The feedback signal is applied to the segments of the field plate in order to control sheet conductivity in specific localized areas. In one embodiment, a metal field plate is split into four segments along lines between bias and sense contacts of the Hall element. Opposing diagonal segments are electrically connected.

Abstract: Systems, devices and methods are provided for magnetic memory elements with low remanence flux concentrators. Improved bit yield is attributable to reduced remanence in the flux concentrator. Remanence provides the memory element with a biasing magnetic field. The flux concentrator includes anisotropy aligned with an appropriate conductor. One aspect of the present subject matter is a memory cell. One memory cell embodiment includes a magnetic memory element and a flux concentrator operably positioned with respect to a conductor. The conductor is adapted to provide a current-induced magnetic flux to the magnetic memory element. The flux concentrator includes an easy axis of magnetization aligned with the conductor and a hard axis of magnetization orthogonal to the easy axis of magnetization. Other aspects are provided herein.

Abstract: A magnetoresistance element, wherein a first electric conductor is so formed as to contact almost the center of the surface opposite to a non-magnetic layer of a first ferromagnetic layer so formed as to sandwich, along with a second ferromagnetic layer, the non-magnetic layer, and an insulator so formed as to cover at least the side surface of the first ferromagnetic layer and the non-magnetic layer is formed so as to cover the peripheral edge of the surface of the first ferromagnetic layer, whereby it is possible to prevent a leakage current from flowing from the first electric conductor to a second electric conductor along the side surfaces of the first ferromagnetic layer, the non-magnetic layer and the second ferromagnetic layer, and to make uniform a bias current running from the first electric conductor to the second electric conductor to thereby restrict variations in magnetoresistance characteristics such as MR value and junction resistance.

Abstract: Depletion-mode ferroelectric transistors are adapted for use as non-volatile memory cells. Various embodiments are described having a diode interposed between the bit line and a source/drain region of the transistor for added margin against read disturb. Various additional embodiments are described having an array architecture such that two memory cells sharing the same bit line also share the same program line. Using this configuration, non-selected cells are readily supplied with gate/source voltages sufficient to maintain the cells in a deactivated state during read and write operations on selected cells.

Abstract: Arrays of microelectronic elements such as magnetorestive memory elements and FET's, including dual-gate FET's, are fabricated by methods involving a host wafer and a first wafer on which part of the microelectronic elements are separately formed. Conductive elements such as metal-filled vias are formed in the host wafer and extend to its surface. Hydrogen ions are implanted at a selected depth in the first wafer. After formation of selected portions of the microelectronic elements above the hyrogen ion implantation depth of the first wafer, the latter is bonded to the surface of the host wafer so that complementary parts of the two wafers can join to form the microelectronic elements. The first wafer is fractured at the hydrogen ion implantation depth and its lower portion is removed to allow for polishing and affixing of electrodes thereon.

Abstract: A magneto resistive memory device is fabricated by etching a blanket metal stack comprised of a buffer layer, pinned magnetic layer, a tunnel barrier layer and a free magnetic layer. The problem of junction shorting from resputtered metal during the etching process is eliminated by formation of a protective spacer covering the side of the freelayer and tunnel barrier interface. The spacer is formed following the first etch through the free layer which stops on the barrier layer. After spacer formation a second etch is made to isolate the device. The patterning of the device tunnel junction is made using a disposable mandrel method that enables a self-aligned contact to be made following the completion of the device patterning process.

Abstract: A method and system for providing and using a magnetic memory are disclosed. The method and system include providing a plurality of magnetic memory cells, at least a first write line, and at least a second write line. Each of the magnetic memory cells includes a magnetic element having a top and a bottom. The first write line(s) are connected to the bottom of magnetic element of the first portion of the plurality of magnetic memory cells. The second write line(s) reside above the top of the magnetic element of each of a second portion of the magnetic memory cells. The second write line(s) are electrically insulated from the magnetic element of each of the second portion of the plurality of magnetic memory cells.

Abstract: The invention includes a magnetoresistive memory device having a conductive core, and a first magnetic layer extending at least partially around the conductive core. A non-magnetic material is over at least a portion of the first magnetic layer and separated from the conductive core by at least the first magnetic layer. A second magnetic layer is over the non-magnetic material, and separated from the first magnetic layer by at least the non-magnetic material. The invention also includes methods of forming magnetoresistive memory devices.

Abstract: An MTJ element is formed between orthogonal word and bit lines. The bit line is a composite line which includes a high conductivity layer and a soft magnetic layer under the high conductivity layer. During operation, the soft magnetic layer concentrates the magnetic field of the current and, due to its proximity to the free layer, it magnetically couples with the free layer in the MTJ. This coupling provides thermal stability to the free layer magnetization and ease of switching and the coupling may be further enhanced by inducing a shape or crystalline anisotropy into the free layer during formation.

Abstract: A semiconductor apparatus includes lower conductive film strips, an inter-layer insulating layer, implanted conductive members, and upper conductive film strips. The lower conductive film strips are formed in a pattern closely adjacent in a line width orientation, electrically separated from each other. The inter-layer insulating layer is formed the lower conductive film strips. The implanted conductive members are implanted in connection holes formed in the inter-layer insulating layer at positions corresponding to both edge sides of the lower conductive film strips. The upper conductive film strips are formed on the implanted conductive members and the inter-layer insulating layer to connect the lower conductive film strips in series so that the lower conductive film strips, the implanted conductive members, and the upper conductive film strips form an electric coil.

Abstract: A magnetic memory device can information with a low power consumption by inhibiting the coercive force from being increased by a demagnetizing field in a free layer, regardless of the thickness, moment, and the like of the free layer, even when the size of a magnetoresistive element is reduced.

Abstract: An emitter for an electron-beam projection lithography (EPL) system and a manufacturing method therefor are provided. The electron-beam emitter includes a substrate, an insulating layer overlying the substrate, and a gate electrode including a base layer formed on top of the insulating layer to a uniform thickness and an electron-beam blocking layer formed on the base layer in a predetermined pattern. The manufacturing method includes steps of: preparing a substrate; forming an insulating layer on the substrate; forming a base layer of a gate electrode by depositing a conductive metal on the insulating layer to a predetermined thickness; forming an electron-beam blocking layer of the gate electrode by depositing a metal capable of anodizing on the base layer to a predetermined thickness; and patterning the electron-beam blocking layer in a predetermined pattern by anodizing. The emitter provides a uniform electric field within the insulating layer and simplify the manufacturing method therefor.

Abstract: Micromachine systems are provided. An embodiment of such a micromachine system includes a substrate that defines a trench. First and second microelectromechanical devices are arranged at least partially within the trench. Each of the microelectromechanical devices incorporates a first portion that is configured to move relative to the substrate. Methods also are provided.

Abstract: MRAM devices include an MRAM substrate having a face, elongated main magnetic resistors that extend along the face and elongated reference magnetic resistors that extend along the face nonparallel to the elongated main magnetic resistors. The elongated reference magnetic resistors may extend along the face orthogonal to the elongated main magnetic resistors. The elongated main magnetic resistors may be configured to have a maximum resistance or a minimum resistance, and the elongated reference magnetic transistors may be configured to have resistance midway between the maximum resistance and the minimum resistance.

Abstract: A memory card includes at least one magnetic random access memory supported by a substrate, and a memory card cover disposed over the magnetic random access memory and the substrate to form a memory card, wherein at least one of the substrate and the memory card cover includes magnetic shielding to at least partially shield the magnetic random access memory from external magnetic fields, the memory card cover forming an external portion of the memory card.

Abstract: An exemplary magnetic memory cell comprises a data layer, a soft reference layer having a lower magnetic energy than the data layer, and spacer layer between the data layer and the soft reference layer.

Abstract: A memory includes an array of magnetic memory cells, each magnetic memory cell being adapted to store a bit of information, interconnects in communication with the magnetic memory cells, and conductors in communication with the magnetic memory cells and the interconnects, the conductors filling spaces between adjacent magnetic memory cells of the array.

Abstract: A write line is covered with a yoke material. The recording layer of an MTJ element is exchange-coupled to the yoke material. The total magnetic volume ?Msi×ti of the recording layer of the MTJ element and a portion of the yoke material that is exchange-coupled to the recording layer is smaller than the magnetic volume ?Msi?×ti? of the remaining portion of the yoke material that covers the write line.

Abstract: Embodiments of the invention include magnetoresistive memory cells having magnetic focusing spacers are formed on sidewalls thereof. Therefore, magnetic fields generated by a bit line and a digit line are focused by the magnetic focusing spacers and efficiently transferred to the magnetoresistive memory cell. In addition, an interlayer dielectric layer surrounding the magnetoresistive memory cell may be formed of high permeability material, thereby efficiently transferring magnetic field.

Abstract: In an MRAM and method for fabricating the same, the MRAM includes a semiconductor substrate, a transistor formed on the semiconductor substrate, an interlayer dielectric formed on the semiconductor substrate to cover the transistor, and first and second MTJ cells formed in the interlayer dielectric to be coupled in parallel with a drain region of the transistor, wherein the first MTJ cell is coupled to a first bit line formed in the interlayer dielectric and the second MTJ cell is coupled to a second bit line formed in the interlayer dielectric, and wherein a data line is formed between the first MTJ cell and a gate electrode of the transistor to be perpendicular to the first bit line and the second bit line. The MRAM provides high integration density, sufficient sensing margin, high-speed operation and reduced noise, requires reduced current for recording data and eliminates a voltage offset.

Abstract: An exemplary nonvolatile memory array comprises a substrate and a plurality of memory cells formed on the substrate, each of the memory cells being addressable via at least first and second conductors during operations. An exemplary memory cell in the exemplary memory array includes a ferromagnetic annular data layer having an opening, the opening enabling the second conductor to electrically contact the first conductor, an intermediate layer on at least a portion of the annular data layer, and a soft reference layer on at least a portion of the intermediate layer.

Abstract: A method and apparatus which provide one or more electromagnetic shield layers for integrated circuit chips containing electromagnetic circuit elements are disclosed. The shield layers may be in contact with the integrated circuit chip, including magnetic memory structures such as MRAMs, or in a flip-chip carrier, or both. A printed circuit board which supports the chip may also have one or more shield layers.

Abstract: The present invention seeks to reduce the amount of current required for a write operation by using a process for forming the read conductor within a recessed write conductor, the write conductor itself formed within a trench of an insulating layer. The present invention protects the MTJ from the voltages created by the write conductor by isolating the write conductor and enabling the reduction of current necessary to write a bit of information.

Abstract: An array of conductive lines for MRAM circuits wherein at least one set of mutually parallel conductive traces is tilted with respect to being perpendicular with a corresponding set of mutually parallel conductive traces wherein individual conductive traces within the sets intersect adjacent individual MRAM cells and wherein the tilting of the at least one set of conductive traces acts to induce both a vertical and horizontal component of a magnetic field such that the net vector addition of magnetic fields induced by the sets of conductive traces is greater than the untilted or perpendicular configuration so as to induce a greater net magnetic field to effect more reliable switching of the underlying MRAM cells. The tilted array also enables reducing the current supplied by the conductive traces while maintaining a comparable net magnetic field to the untilted configuration.

Abstract: A magneto-resistive device has a high reproducing output and is suitable for use as a CPP-GMR device. The magneto-resistive device has a first magnetic layer, a second magnetic layer, and a non-magnetic spacer formed between the first and second magnetic layers. The first magnetic layer contains a magnetic material whose conduction electrons belong to a first energy band, and the second magnetic layer contains a magnetic material whose conduction electrons belong to a second energy band. The first and second energy bands are attributable to orbitals of the same kind, thereby increasing the ratio of change in magnetoresistance and adjusting the electric resistance.

Abstract: A magnetic sensor device formed using SOI CMOS techniques includes a substrate, a silicon oxide layer and in some cases a plurality of gated regions. A first terminal is located between two innermost gated regions and supplies a supply voltage. A second and a third terminal, each of which is located between two adjacent gated regions other than the two innermost gated regions, output positive and negative Hall voltages. By appropriately controlling a bias voltage to the gated regions, small changes in a magnetic field induces larger currents in channel regions under the gated regions, which, in turn, results in detectable Hall voltages.

Abstract: A digital magnetic memory cell device for read and/or write operations has a soft-magnetic read and/or write layer system formed of at least one soft-magnetic read and/or write layer, and a hard-magnetic reference layer system. The two systems are separated by a barrier layer. The soft-magnetic read and/or write layer is an amorphous layer with an induced or inducible uniaxial anisotropy.

Abstract: Ultrafast square-law detectors amplify electric currents and electromagnetic waves with frequencies on the order of 100 GHz or more. The detectors use injection of spin-polarized electrons from a magnetic film or region into another magnetic film or region through a thin semiconductor control region. A signal current flowing through a conductive nanowire induces a magnetic field causing precession of electron spin injected inside the semiconductor layer and thereby changing the conductivity of the detector. With the magnetizations of the magnetic regions being parallel or antiparallel to each other, the resulting spin injection current includes a term proportional to the square of the signal current so that the detector behaves as a square-law detector. Such square-law detectors are magnetic-semiconductor heterostructures and can operate as a frequency doubler for millimeter electromagnetic waves.

Abstract: A method for fabricating a cladded conductor (42) for use in a magnetoelectronics device is provided. The method includes providing a substrate (10) and forming a conductive barrier layer (12) overlying the substrate (10). A dielectric layer (16) is formed overlying the conductive barrier layer (12) and a conducting line (20) is formed within a portion of the dielectric layer (16). The dielectric layer (16) is removed and a flux concentrator (30) is formed overlying the conducting line (20).

Abstract: A spin switch that can be driven with voltage. This spin switch includes the following: a ferromagnetic material; a magnetic semiconductor magnetically coupled to the ferromagnetic material; an antiferromagnetic material magnetically coupled to the magnetic semiconductor; and an electrode connected to the magnetic semiconductor via an insulator. A change in the electric potential of the electrode causes the magnetic semiconductor to make a reversible transition between a ferromagnetic state and a paramagnetic state. When the magnetic semiconductor is changed to the ferromagnetic state, the ferromagnetic material is magnetized in a predetermined direction due to the magnetic coupling with the magnetic semiconductor.

Abstract: A method of shielding an integrated circuit from electromagnetic interference. The integrated circuit is at least partially encapsulated within an electromagnetic interference resistant molding compound, and then the integrated circuit is completely encapsulated within a second molding compound. In this manner, the electromagnetic interference resistant molding compound protects the integrated circuit from electromagnetic interference, while the second molding compound can be selected for properties traditionally desired in a molding compound, such as thermal, electrical insulating, and structural properties. Thus, the integrated circuit according to the present invention can be placed closer to structures, such as power supplies, which produce electromagnetic interference, without experiencing an unacceptable degradation of performance due to the electromagnetic interference caused by the structures.