With Magnetic Field Directing Means (e.g., Shield, Pole Piece, Etc.) Patents (Class 257/422)
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Publication number: 20110090732Abstract: A particular magnetic tunnel junction (MTJ) cell includes a side wall defining a first magnetic domain adapted to store a first digital value. The MTJ cell also includes a bottom wall coupled to the side wall and defining a second magnetic domain adapted to store a second digital value.Type: ApplicationFiled: December 21, 2010Publication date: April 21, 2011Applicant: QUALCOMM INCORPORATEDInventors: Xia Li, Seung H. Kang, Xiaochun Zhu
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Publication number: 20110089511Abstract: A method of making a magnetic random access memory cell includes forming a magnetic tunnel junction (MTJ) on top of a wafer, depositing oxide on top of the MTJ, depositing a photo-resist layer on top of the oxide layer, forming a trench in the photo-resist layer and oxide layer where the trench has a width that is substantially the same as that of the MTJ. Then, the photo-resist layer is removed and a hard mask layer is deposited on top of the oxide layer in the trench and the wafer is planarized to remove the portion of the hard mask layer that is not in the trench to substantially level the top of oxide layer and the hard layer on the wafer. The remaining oxide layer is etched and the the MTJ is etched to remove the portion of the MTJ which is not covered by the hard mask layer.Type: ApplicationFiled: December 21, 2010Publication date: April 21, 2011Applicant: AVALANCHE TECHNOLOGY, INC.Inventors: Parviz KESHTBOD, Roger Klas MALMHALL, Rajiv Yadav RANJAN
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Patent number: 7919836Abstract: Disclosed is a semiconductor device which includes a semiconductor chip and a base substrate. The semiconductor chip includes a semiconductor substrate, an interconnect layer and a high-frequency interconnect. The interconnect layer is provided on the substrate. The high-frequency interconnect is formed within the interconnect layer. The semiconductor chip is mounted onto the base substrate. An electromagnetic shield layer is provided between the high-frequency interconnect and the interconnect.Type: GrantFiled: April 24, 2009Date of Patent: April 5, 2011Assignee: Renesas Electronics CorporationInventor: Yasutaka Nakashiba
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Publication number: 20110062539Abstract: To provide a semiconductor device in which the deterioration of the rewrite property is suppressed. In a memory cell region, magnetoresistive elements in a semiconductor magnetic-storage device are formed in an array shape in a mode that the magnetoresistive elements are arranged at portions where digit lines extending in one direction intersect bit lines extending in the direction approximately orthogonal to the digit lines. The digit line and the bit line have such a wiring structure constituted by covering a copper film to be a wiring main body with a cladding layer. One end side of the magnetoresistive element is electrically coupled to the bit line via a top via formed from a non-magnetic material.Type: ApplicationFiled: September 17, 2010Publication date: March 17, 2011Inventors: Ryoji MATSUDA, Motoi Ashida, Shuichi Ueno, Shoichi Fukui, Shinya Hirano, Seiji Muranaka, Kazuyuki Omori
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Publication number: 20110057275Abstract: To provide a semiconductor device capable of write operation to a selected magnetoresistive element without causing a malfunction of a non-selected magnetoresistive element and a manufacturing method of this semiconductor device. The semiconductor device includes a magnetic storage element having a magnetization free layer whose magnetization direction is made variable and formed over a lead interconnect and a digit line located below the magnetic storage element, extending in a first direction, and capable of changing the magnetization state of the magnetization free layer by the magnetic field generated. The digit line includes an interconnect body portion and a cladding layer covering therewith the bottom surface and the side surface of the interconnect body portion and opened upward. The cladding layer includes a sidewall portion covering therewith the side surface of the interconnect body portion and a bottom wall portion covering therewith the bottom surface of the interconnect body portion.Type: ApplicationFiled: September 2, 2010Publication date: March 10, 2011Inventors: Mikio TSUJIUCHI, Yosuke Takeuchi, Kazuyuki Omori, Kenichi Mori
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Patent number: 7898066Abstract: A semiconductor device has a substrate having a plurality of metal layers. A die is coupled to the substrate. A plurality of metal wires is provided. At least one end of each of the metal wires is electrically coupled to at least one metal layer. A mold compound is used to encapsulate the die, a first surface of the substrate, and the plurality of metal wires. A portion of at least one metal wire remains exposed. A conductive coating is applied to the mold compound and to the portion of the at least one metal wire exposed.Type: GrantFiled: May 25, 2007Date of Patent: March 1, 2011Assignee: Amkor Technology, Inc.Inventors: Christopher M. Scanlan, Christopher J. Berry, Timothy L. Olson
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Patent number: 7888756Abstract: A magnetic tunnel junction (MTJ) structure is of the type having a tunnel barrier positioned between a fixed ferromagnetic layer and a free ferromagnetic layer, the tunnel barrier includes a first barrier layer contacting either the fixed ferromagnetic layer or the free ferromagnetic layer. The first barrier layer transmits a high spin polarization and is selected from the group consisting of metal oxides, metal nitrides, and metal oxynitrides. The second barrier layer, which contacts the first barrier layer, has a low barrier height and is selected from the group consisting of metal oxides, metal nitrides, and metal oxynitrides.Type: GrantFiled: March 22, 2007Date of Patent: February 15, 2011Assignee: Everspin Technologies, Inc.Inventors: Phillip Glenn Mather, Renu W. Dave, Frederick B. Mancoff
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Patent number: 7872321Abstract: A hybrid semiconductor-ferromagnet device is a device which has micromagnets (Co) deposited on semiconductor (InAs) two-dimensional electrons, and which has a junction structure of positive and negative magnetic field regions using a stray field resulting from the micromagnets. The magnetoresistance measured in the hybrid semiconductor-ferromagnet device has an asymmetrical hall resistance profile, and a change in magnetoresistance thereof is very large. The measured data is well consistent with the calculated results using a diffusive mode and a ballistic model.Type: GrantFiled: November 7, 2006Date of Patent: January 18, 2011Assignee: Korea Institute of Science and TechnologyInventors: Kyung-Ho Shin, Jim-Ki Hong, Sung-Jung Joo, Kung-Won Rhie
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Patent number: 7834410Abstract: The present disclosure provides a semiconductor memory device. The device includes a bottom electrode over a semiconductor substrate; an anti-ferromagnetic layer disposed over the bottom electrode; a pinned layer disposed over the anti-ferromagnetic layer; a barrier layer disposed over the pinned layer; a first ferromagnetic layer disposed over the barrier layer; a buffer layer disposed over the first ferromagnetic layer, the buffer layer including tantalum; a second ferromagnetic layer disposed over the buffer layer; and a top electrode disposed over the second ferromagnetic layer.Type: GrantFiled: April 13, 2009Date of Patent: November 16, 2010Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yu-Jen Wang, Ya-Chen Kao, Chun-Jung Lin
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Patent number: 7825000Abstract: A magnetic memory device including a Magnetic Tunnel Junction (MTJ) device comprises a substrate and Front End of Line (FEOL) circuitry. A Via level (VA) InterLayer Dielectric (ILD) layer, a bottom conductor layer, and an MTJ device formed over the top surface of the VA ILD layer are formed over a portion of the substrate. An alignment region including alignment marks extends through the bottom conductor layer and extends down into the device below the top surface of the VA ILD layers is juxtaposed with the MJT device.Type: GrantFiled: September 5, 2007Date of Patent: November 2, 2010Assignee: International Business Machines CorporationInventors: Sivananda K. Kanakasabapathy, Solomon Assefa
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Patent number: 7821110Abstract: Back end of line (BEOL) circuit structures and methods are provided for blocking externally-originating or internally-originating electromagnetic interference. One such BEOL circuit structure includes one or more semiconductor substrates supporting one or more integrated circuits, and one or more BEOL layers disposed over the semiconductor substrate(s). At least one BEOL layer includes a conductive pattern defined at least partially by a plurality of elements arrayed in a first direction and a second direction throughout at least a portion thereof. The plurality of elements are sized and positioned in at least one of the first and second directions to block electromagnetic interference of a particular wavelength from passing therethrough. In one implementation, a first conductive pattern of a first BEOL layer polarizes electromagnetic interference, and a second conductive pattern of a second BEOL layer blocks the polarized electromagnetic interference.Type: GrantFiled: May 11, 2007Date of Patent: October 26, 2010Assignee: International Business Machines CorporationInventors: Dae Ik Kim, Jonghae Kim, Moon Ju Kim, Choongyeun Cho
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Patent number: 7821087Abstract: A method and system for providing a magnetic element that can be used in a magnetic memory is disclosed. The magnetic element includes pinned, nonmagnetic spacer, and free layers. The spacer layer resides between the pinned and free layers. The free layer can be switched using spin transfer when a write current is passed through the magnetic element. The magnetic element may also include a barrier layer, a second pinned layer. Alternatively, second pinned and second spacer layers and a second free layer magnetostatically coupled to the free layer are included. In one aspect, the free layer(s) include ferromagnetic material(s) diluted with nonmagnetic material(s) and/or ferrimagnetically doped to provide low saturation magnetization(s).Type: GrantFiled: March 13, 2007Date of Patent: October 26, 2010Assignee: Grandis, Inc.Inventors: Paul Nguyen, Yiming Huai, Zhitao Diao, Frank Albert
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Patent number: 7821088Abstract: A method and system for providing a magnetic element that can be used in a magnetic memory is disclosed. The magnetic element includes pinned, nonmagnetic spacer, and free layers. The spacer layer resides between the pinned and free layers. The free layer can be switched using spin transfer when a write current is passed through the magnetic element. The free layer includes a first ferromagnetic layer and a second ferromagnetic layer. The second ferromagnetic layer has a very high perpendicular anisotropy and an out-of-plane demagnetization energy. The very high perpendicular anisotropy energy is greater than the out-of-plane demagnetization energy of the second layer.Type: GrantFiled: June 5, 2008Date of Patent: October 26, 2010Assignee: Grandis, Inc.Inventors: Paul P. Nguyen, Yiming Huai
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Publication number: 20100254182Abstract: A magnetic storage device which enables stable operation at the time of recording information into MRAM and the stable retention of recorded information. The die of the magnetic storage device has a substrate, first and second wirings, a magnetic storage element and a first magnetic shielding structure. The first magnetic shielding structure is formed to cover the magnetic storage element in a plan view. Second and third magnetic shielding structures sandwich the die in a thickness direction. A lead frame member has the die mounted thereon and contains a ferromagnetic material. The lead frame member overlaps with only part of the die in a plan view.Type: ApplicationFiled: March 22, 2010Publication date: October 7, 2010Inventors: Takeharu KUROIWA, Masayoshi Tarutani, Takashi Takenaga, Hiroshi Takada
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Publication number: 20100244164Abstract: Two opposing substrate layers each having one or more recesses filled with magnetic material guide the flow of flux through a coil in a MEMS device layer to provide for closed-loop operation. Flux flows from one pole piece through the coil to a second pole piece. A method of making using lithographic etching techniques is also provided.Type: ApplicationFiled: March 26, 2009Publication date: September 30, 2010Applicant: Honeywell International Inc.Inventor: Ryan Roehnelt
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Patent number: 7795696Abstract: A magnetoresistive memory element has a read module with a first pinned layer that has a magnetoresistance that is readable by a read current received from an external circuit. The element has a write module that receives a write current from the external circuit. A coupling module adjacent both the write module and the read module has a free layer that functions as a shared storage layer for both the read module and the write module. The shared storage layer receives spin torque from both the read module and the write module and has a magnetization that is rotatable by the write current.Type: GrantFiled: January 4, 2008Date of Patent: September 14, 2010Assignee: Seagate Technology LLCInventors: Oleg N. Mryasov, Thomas F. Ambrose, Werner Scholz
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Method and apparatus for bitline and contact via integration in magnetic random access memory arrays
Patent number: 7772663Abstract: In one embodiment, the invention is a method and apparatus for bitline and contact via integration in magnetic random access memory arrays. One embodiment of a magnetic random access memory according to the present invention includes a magnetic tunnel junction and a top wire that surrounds the magnetic tunnel junction on at least three sides.Type: GrantFiled: February 21, 2007Date of Patent: August 10, 2010Assignee: International Business Machines CorporationInventors: Sivananda Kanakasabapathy, Michael C. Gaidis -
Patent number: 7772660Abstract: A magnetic random access memory includes a transistor having a gate electrode formed above a surface of a substrate, and first and second impurity diffusion regions which sandwich a channel region below the gate electrode, a first plug formed on the first impurity diffusion region, a recording element formed on the first plug, including a plurality of stacked layers, and configured to hold information in accordance with an internal magnetization state, a first signal line formed on the recording element, a second plug formed on the second impurity diffusion region, an electrical conductor formed on the second plug, an area of a shape of the electrical conductor, which is projected onto the surface of the substrate, being larger than that of a shape of the recording element, which is projected onto the surface of the substrate, and a second signal line formed on the electrical conductor.Type: GrantFiled: May 13, 2008Date of Patent: August 10, 2010Assignee: Kabushiki Kaisha ToshibaInventor: Yoshihiro Ueda
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Patent number: 7772659Abstract: The magnetic device comprises a least two layers made of a magnetic material that are separated by at least one interlayer made of a non-magnetic material. The layers made of a magnetic material each have magnetization oriented substantially perpendicular to the plane of the layers. The layer of non-magnetic material induces an antiferromagnetic coupling field between the layers made of a magnetic material, the direction and amplitude of this field attenuating the effects of the ferromagnetic coupling field of magnetostatic origin that occurs between the magnetic layers.Type: GrantFiled: October 22, 2007Date of Patent: August 10, 2010Assignees: Commissariat a l'Energie Atomique, Centre National de la Recherche ScientifiqueInventors: Bernard Rodmacq, Vincent Baltz, Alberto Bollero, Bernard Dieny
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Patent number: 7768083Abstract: An integrated circuit can have a first substrate supporting a magnetic field sensing element and a second substrate supporting another magnetic field sensing element. The first and second substrates can be arranged in a variety of configurations. Another integrated circuit can have a first magnetic field sensing element and second different magnetic field sensing element disposed on surfaces thereof.Type: GrantFiled: January 20, 2006Date of Patent: August 3, 2010Assignee: Allegro Microsystems, Inc.Inventors: Michael C. Doogue, William P. Taylor, Vijay Mangtani
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Patent number: 7759750Abstract: To provide a highly-reliable, low-power-consumption nonvolatile memory. A magnetization reversal of a ferromagnetic free layer is accomplished with a spin transfer torque in a state where an appropriate magnetic field is applied in a direction orthogonal to the direction of the magnetic easy axis of the ferromagnetic free layer of the tunnel magnetoresistance device that the magnetic memory cell includes. Preferably, the magnetic field is applied in a direction forming an angle of 45° with the direction perpendicular to the film plane.Type: GrantFiled: April 24, 2007Date of Patent: July 20, 2010Assignees: Hitachi, Ltd., Tohoku UniversityInventors: Jun Hayakawa, Hideo Ohno, Shoji Ikeda
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Patent number: 7745893Abstract: A magnetic transistor includes a first magnetic section, a second magnetic section, a conductive section, a first metal terminal, and a second metal terminal. The conductive section is disposed between and is in direct contact with both the first and second magnetic section. The first metal terminal is disposed on one end of an opposite surface to the conductive section of the first magnetic section. The second metal terminal is disposed on one end approximately diagonal to the first metal terminal on an opposite surface to the conductive section of the second magnetic section. While the magnetic transistor structure is turned on, a current flows through the first magnetic section and the second magnetic section via the conductive section.Type: GrantFiled: October 6, 2006Date of Patent: June 29, 2010Assignee: Northern Lights Semiconductor Corp.Inventors: James Chyi Lai, Tom Allen Agan
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Patent number: 7741707Abstract: A stackable integrated circuit package system is provided placing a first integrated circuit die having an interconnect provided thereon in a substrate having a cavity, encapsulating the first integrated circuit die, having the interconnect exposed, in the cavity and along a first side of the substrate, mounting a second integrated circuit die to the first integrated circuit die, and encapsulating the second integrated circuit die along a second side of the substrate.Type: GrantFiled: February 27, 2006Date of Patent: June 22, 2010Assignee: Stats Chippac Ltd.Inventors: Seng Guan Chow, Heap Hoe Kuan, Dioscoro A. Merilo, Antonio B. Dimaano, Jr.
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Patent number: 7737515Abstract: Systems and methods for assembling a structure onto a substrate include an array of programmable magnets disposed beneath a substrate, wherein a magnetic field is applied to the structure to levitate the structure above the substrate while the structure is moved relative to the substrate to align the structure with a corresponding recess formed in the substrate. A magnetic field may be applied to translate and rotate the structure relative to the substrate. Differences between or among the programmable magnets regarding magnetic polarity, energized versus de-energized status, and magnetic field strength may be used to move the structure relative to the substrate in conjunction with a closed-loop control system. A bonded substrate assembly and a method of bonding a first wafer to a second wafer include wherein the first wafer includes a projection and the second wafer includes a matching depression.Type: GrantFiled: June 20, 2008Date of Patent: June 15, 2010Assignee: New Jersey Institute of TechnologyInventors: Nuggehalli M. Ravindra, Vijay Kasisomayajula, Sudhakar Shet, Anthony T. Fiory
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Patent number: 7719069Abstract: In one illustrative example, a three terminal magnetic sensor includes a collector region made of a semiconductor material, a base region, and an emitter region. An insulator layer is formed between the collector region and a carrier substrate body which carries the three terminal magnetic sensor. The insulator layer serves to reduce a capacitance otherwise present between the collector region and magnetic media at a magnetic field sensing plane of the three terminal magnetic sensor. Thus, the insulator layer electrically isolates the collector region from the carrier substrate body. The structure may be formed through use of a separation by implanting oxygen (SIMOX) technique or a wafer-bonding technique, as examples.Type: GrantFiled: May 10, 2005Date of Patent: May 18, 2010Assignee: Hitachi Global Storage Technologies Netherlands B.V.Inventor: Jeffrey S. Lille
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Publication number: 20100118585Abstract: One embodiment of the present invention includes a three dimensional memory array having a plurality of memory elements coupled to form the array through a single top lead and a single bottom lead, each memory element including a magnetic free layer in which non-volatile data can be stored, wherein each memory element possesses unique resonant frequencies associated with each digital memory state, thereby enabling frequency addressing during parallel write and read operations, each memory element further including a fixed layer and a spacer formed between the free layer and the fixed layer.Type: ApplicationFiled: December 8, 2009Publication date: May 13, 2010Applicant: HITACHI GLOBAL STORAGE TECHNOLOGIES NETHERLANDS B.V.Inventors: Liesl Folks, Bruce David Terris
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Patent number: 7692310Abstract: In one embodiment, the present invention includes a hybrid device having a first die including a semiconductor device and a second die coupled to the first die, where the second die includes a magnetic structure. The first die may be a semiconductor substrate, while the second die may be a magnetic substrate, and the first die may be stacked on the second die, in one embodiment. Other embodiments are described and claimed.Type: GrantFiled: March 27, 2006Date of Patent: April 6, 2010Assignee: Intel CorporationInventors: Chang-Min Park, Shriram Ramanathan
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Publication number: 20100072566Abstract: Exemplary embodiments of the invention are directed to magnetic elements including a passivation layer for isolation from other on-chip elements. One embodiment is directed to an apparatus comprising a magnetic tunnel junction (MTJ) element. The MTJ element comprises: a first ferromagnetic layer; a second ferromagnetic layer; an insulating layer disposed between the first and second ferromagnetic layers; and an MTJ passivation layer forming protective sidewalls disposed adjacent to the first ferromagnetic layer, the second ferromagnetic layer, and the insulating layer.Type: ApplicationFiled: September 24, 2008Publication date: March 25, 2010Applicant: QUALCOMM INCORPORATEDInventors: Seung H. Kang, Sei Seung Yoon
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Patent number: 7683447Abstract: A method for fabricating a magnetoresistive random access memory (MRAM) device having a plurality of memory cells includes: forming a fixed magnetic layer having magnetic moments fixed in a predetermined direction; forming a tunnel layer over the fixed magnetic layer; forming a free magnetic layer, having magnetic moments aligned in a direction that is adjustable by applying an electromagnetic field, over the tunnel layer; forming a hard mask on the free magnetic layer partially covering the free magnetic layer; and unmagnetizing portions of the free magnetic layer uncovered by the hard mask for defining one or more magnetic tunnel junction (MTJ) units.Type: GrantFiled: September 12, 2007Date of Patent: March 23, 2010Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Yu-Jen Wang, Young-Shying Chen, Ya-Chen Kao, Chun-Jung Lin
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Patent number: 7684147Abstract: The present invention is directed to the use of perovskite manganite thin films and other magnetic films that exhibit both planar Hall effect and biaxial magnetic anisotropy to form the active area in magnetic sensor devices and in magnetic bit cells used in magnetoresistive random access memory (MRAM) devices. The manganite thin films of the invention are ferromagnetic manganites of the formula R1-xAxMnO3, wherein R is a rare-earth metal, A is an alkaline earth metal, and x is generally between about 0.15 and about 0.5.Type: GrantFiled: December 15, 2004Date of Patent: March 23, 2010Inventors: Charles Ahn, Lior Klein, Yosef Basson, Xia Hong, Jeng-Bang Yau
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Patent number: 7683446Abstract: A magnetization direction in a magnetosensing layer (5b) is perturbed near the magnetic connection between a magnetic yoke (5) and the magnetosensing layer (5b). If the magnetization direction of a region in the magnetosensing layer (5b) facing a fixed layer which functions during read is not perturbed, reliability is improved. In this magnetometric sensor, a surface area S1 of fixed layers (43, 44) is made smaller than a surface area S2 of the magnetosensing layer (5b) so that, in the region of the magnetosensing layer (5b) facing the fixed layer, the magnetization direction is perturbed less than in the surrounding region and reliability during data read is improved.Type: GrantFiled: May 31, 2006Date of Patent: March 23, 2010Assignee: TDK CorporationInventor: Keiji Koga
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Patent number: 7682840Abstract: A method and magnetic device for improving the desirable properties of a magnetic device, e.g., magnetization uniformity and reproducibility. Moreover the invention provides magnetic cells that are more magnetically homogeneous, with smaller amount of end domain magnetization canting from the average cell magnetization direction. The invention may provide a magnetic memory cell with less variation in switching fields, more spatially coherent dynamical magnetic properties for high speed and processional or coherent magnetic switching, and higher signal due to the increased uniformity. It may provide a magnetic sensor with more spatially coherent magnetic properties for high speed and processional or coherent magnetic switching, and increased signal. It may provide a read head element with more spatially coherent magnetic properties for high speed and processional or coherent magnetic sensing, and increased signal.Type: GrantFiled: April 4, 2006Date of Patent: March 23, 2010Assignee: IMECInventors: Wayne Hiebert, Jo De Boeck, Liesbet Lagae, Roel Wirix-Speetjens
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Patent number: 7676914Abstract: In an exemplary embodiment, a method for a magnetic sensor includes forming a first conductive layer over a substrate containing circuitry, forming a dielectric layer over the first conductive layer, forming a second conductive layer over the dielectric layer such that the first conductive layer, the dielectric layer, and the second conductive layer form a first capacitor, and providing first and second terminals, wherein the first terminal is coupled to the first conductive layer and the second terminal is coupled to the second conductive layer.Type: GrantFiled: October 23, 2007Date of Patent: March 16, 2010Assignee: Allegro Microsystems, Inc.Inventor: William P. Taylor
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Patent number: 7663197Abstract: A magnetoresistive element which records information by supplying spin-polarized electrons to a magnetic material, includes a first pinned layer which is made of a magnetic material and has a first magnetization directed in a direction perpendicular to a film surface, a free layer which is made of a magnetic material and has a second magnetization directed in the direction perpendicular to the film surface, the direction of the second magnetization reversing by the spin-polarized electrons, and a first nonmagnetic layer which is provided between the first pinned layer and the free layer. A saturation magnetization Ms of the free layer satisfies a relationship 0?Ms<?{square root over ( )}{Jw/(6?At)}. Jw is a write current density, t is a thickness of the free layer, A is a constant.Type: GrantFiled: September 22, 2006Date of Patent: February 16, 2010Assignee: Kabushiki Kaisha ToshibaInventors: Toshihiko Nagase, Masatoshi Yoshikawa, Eiji Kitagawa, Masahiko Nakayama, Tadashi Kai, Tatsuya Kishi, Hiroaki Yoda
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Patent number: 7663131Abstract: A MTJ that minimizes error count (EC) while achieving high MR value, low magnetostriction, and a RA of about 1100 ?-?m2 for 1 Mbit MRAM devices is disclosed. The MTJ has a composite AP1 pinned layer made of a lower amorphous Co60Fe20B20 layer and an upper crystalline Co75Fe25 layer to promote a smoother and more uniform AlOx tunnel barrier. A “stronger oxidation” state is realized in the AlOx layer by depositing a thicker than normal Al layer or extending the ROX cycle time for Al oxidation and thereby reduces tunneling hot spots. The NiFe free layer has a low Fe content of about 8 to 21 atomic % and the Hf content in the NiFeHf capping layer is from 10 to 25 atomic %. A Ta hard mask is formed on the capping layer. EC (best) is reduced from >100 ppm to <10 ppm by using the preferred MTJ configuration.Type: GrantFiled: March 8, 2007Date of Patent: February 16, 2010Assignee: MagIC Technologies, Inc.Inventors: Cheng T. Horng, Ru-Ying Tong, Chyu-Jiuh Torng, Guangli Liu
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Patent number: 7659562Abstract: An electric field read/write head, a method of manufacturing the same, and a data read/write device including the electric field read/write head are provided. The data read/write device includes an electric field read/write head which reads and writes data to and from a recording medium. The electric field read/write head includes a semiconductor substrate, a resistance region, source and drain regions, and a write electrode. The semiconductor substrate includes a first surface and a second surface with adjoining edges. The resistance region is formed to extend from a central portion at one end of the first surface to the second surface. The source region and the drain region are formed at either side of the resistance region and are separated from the first surface. The write electrode is formed on the resistance region with an insulating layer interposed between the write electrode and the resistance region.Type: GrantFiled: March 21, 2007Date of Patent: February 9, 2010Assignee: Samsung Electronics Co., Ltd.Inventors: Hyoung-soo Ko, Ju-hwan Jung, Yong-su Kim, Seung-bum Hong, Hong-sik Park
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Patent number: 7648858Abstract: Methods and structures provide a shielded multi-layer package for use with multi-chip modules and the like. A substrate (102) (e.g., chip carrier) has an adhesive layer (104), where electronic components (106, 108) are attached. An insulating layer (110) is formed over the plurality of electronic components, and a conductive encapsulant structure (115) is formed over the insulating layer. The adhesive layer is detached from the electronic components, and multi-layer circuitry (140) is formed over, and in electrical communication with, the plurality of electronic components. A shielding via (150) is formed through the multilayer circuitry such that it contacts the conductive encapsulant.Type: GrantFiled: June 19, 2007Date of Patent: January 19, 2010Assignee: Freescale Semiconductor, Inc.Inventors: Jinbang Tang, Jong-Kai Lin
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Patent number: 7635903Abstract: An oscillator includes at least one of: (i) a parallel array of resistors (420, 421, 422, 701, 801, 901, 902) or magnetoresistive contacts to a magnetoresistive film (120, 320); and (ii) a series array of resistors (620, 621, 702, 902) or magnetoresistive contacts to individualized areas of at least one magnetoresistive film.Type: GrantFiled: September 13, 2005Date of Patent: December 22, 2009Assignee: Everspin Technologies, Inc.Inventors: Frederick B. Mancoff, Bradley N. Engel, Nicholas D. Rizzo
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Patent number: 7633132Abstract: A magnetic sensor comprises a substrate, magnetoresistive element of a spin-valve type, a bias magnetic layer (or a permanent magnet film), and a protective film, wherein the bias magnetic layer is connected with both ends of the magnetoresistive element and the upper surface thereof is entirely covered with the lower surface of the magnetoresistive element at both ends. Herein, distances between the side surfaces of the both ends of the magnetoresistive element and the side surfaces of the bias magnetic layer viewed from the protective film do not exceed 3 ?m. In addition, a part of the bias magnetic layer can be covered with both ends of the magnetoresistive element, and an intermediate layer is arranged in relation to the magnetoresistive element, bias magnetic layer, and protective film so as to entirely cover the upper surface of the bias magnetic layer.Type: GrantFiled: February 9, 2007Date of Patent: December 15, 2009Assignee: Yamaha CorporationInventors: Yukio Wakui, Susumu Yoshida, Kokichi Aiso
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Publication number: 20090261437Abstract: A method for forming a magnetic tunnel junction (MTJ) for magnetic random access memory (MRAM) using two masks includes depositing over an interlevel dielectric layer containing an exposed first interconnect metallization, a first electrode, a fixed magnetization layer, a tunneling barrier layer, a free magnetization layer and a second electrode. An MTJ structure including the tunnel barrier layer, free layer and second electrode is defined above the first interconnect metallization by a first mask. A first passivation layer encapsulates the MTJ structure, leaving the second electrode exposed. A third electrode is deposited in contact with the second electrode. A second mask is used to pattern a larger structure including the third electrode, the first passivation layer, the fixed magnetization layer and the first electrode. A second dielectric passivation layer covers the etched plurality of layers, the first interlevel dielectric layer and the first interconnect metallization.Type: ApplicationFiled: March 17, 2009Publication date: October 22, 2009Applicant: QUALCOMM INCORPORATEDInventors: Seung H. Kang, Xia Li, Shiqun Gu, Matthew Nowak
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Patent number: 7602032Abstract: A memory and method of making a memory is disclosed. In one embodiment, the memory includes a cap structure for a magnetoresistive random access memory device including an etch stop layer formed over an upper magnetic layer of a magnetoresistive junction (MTJ/MCJ) layered structure and a hardmask layer formed over said etch stop layer, wherein said etch stop layer is selected from a material such that an etch chemistry used for removing said hardmask layer has selectivity against etching said etch stop layer material. In a method of opening the hardmask layer, an etch process to remove exposed portions of the hardmask layer is implemented, where the etch process terminates on the etch stop layer.Type: GrantFiled: April 29, 2005Date of Patent: October 13, 2009Assignees: Altis Semiconductor SNC, Infineone Technologies AGInventors: Ulrich Klostermann, Chanro Park, Wolfgang Raberg
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Patent number: 7598597Abstract: A second shield layer, under the master shielding layer, is added to a segmented MRAM array. This additional shielding is patterned so as to provide one shield per bit slice. The placement of longitudinal biasing tabs at the ends of these segmented shields ensures that each segmented shield is a single magnetic domain, making it highly effective as a shield against very small stray fields.Type: GrantFiled: November 3, 2008Date of Patent: October 6, 2009Assignee: MagIC Technologies, Inc.Inventors: Yimin Guo, Po-Kang Wang
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Publication number: 20090243009Abstract: Magnetic tunnel junction cell including multiple vertical domains. In an embodiment, a magnetic tunnel junction (MTJ) structure is disclosed. The MTJ structure includes an MTJ cell. The MTJ cell includes multiple vertical side walls. Each of the multiple vertical side walls defines a unique vertical magnetic domain. Each of the unique vertical magnetic domains is adapted to store a digital value.Type: ApplicationFiled: March 25, 2008Publication date: October 1, 2009Applicant: QUALCOMM INCORPORATEDInventors: Xia Li, Seung H. Kang, Xiaochun Zhu
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Patent number: 7595520Abstract: An MTJ in an MRAM array or TMR read head is disclosed in which a low magnetization capping layer is a composite having a NiFeHf inner layer formed on a NiFe or CoFeB/NiFe free layer, a Ta middle layer, and a Ru outer layer on the Ta layer. For example, a low magnetization NiFeHf layer is achieved by co-sputtering NiFe and Hf targets with a forward power of 400 W and 200 W, respectively. A higher Hf content increases the oxygen gettering power of the NiFeHf layer and the thickness is modified to change dR/R, RA, and magnetostriction values. A so-called dead layer between the free layer and capping layer is restored by incorporating a NiFeHf layer on the free layer to improve lattice matching. The Fe content in the NiFe target used to make the NiFeHf layer is preferably the same as in the NiFe free layer.Type: GrantFiled: July 31, 2006Date of Patent: September 29, 2009Assignee: MagIC Technologies, Inc.Inventors: Cheng T. Horng, Ru-Ying Tong
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Patent number: 7582942Abstract: The present invention provides an MRAM that includes a conductive line for generating a magnetic field. The latter is enhanced by the addition of a flux concentrator made from a single plane of soft ferromagnetic material, magnetically stabilized by means of an antiferromagnetic layer. This structure, in addition to being very easy to fabricate, facilitates close control over its magnetic properties, including uniformity and domain structure.Type: GrantFiled: October 30, 2008Date of Patent: September 1, 2009Assignee: MagIC Technologies, Inc.Inventors: Yimin Guo, Po-Kang Wang
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Patent number: 7579672Abstract: A semiconductor package with electromagnetic shielding capabilities is disclosed. The semiconductor package includes a substrate (101), a plurality of semiconductor dies (102), a plurality of shielding metal elements (103), a plurality of grounding metal elements (104) and a plurality of conductive metal elements (110). The semiconductor dies are disposed on an upper surface (105) of the substrate along a horizontal direction. The shielding metal elements are provided on the upper surface of the substrate, and are arranged between and around the semiconductor dies so that each semiconductor die is surrounded by the shielding metal elements and thus electromagnetic interference in the horizontal direction can be effectively shielded from each semiconductor die.Type: GrantFiled: January 25, 2008Date of Patent: August 25, 2009Assignee: Advanced Semiconductor Engineering, Inc.Inventor: Chia-fu Wu
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Patent number: 7569877Abstract: A system and method for selecting nanometer-scaled devices. The method includes a plurality of semiconductor wires. Two adjacent semiconductor wires of the plurality of semiconductor wires are associated with a separation smaller than or equal to 100 nm. Additionally, the system includes a plurality of address lines. Each of the plurality of address lines includes a gate region and an inactive region and intersects the plurality of semiconductor wires at a plurality of intersections. The plurality of intersections includes a first intersection and second intersection. The first intersection is associated with the gate region, and the second intersection is associated with the inactive region.Type: GrantFiled: February 24, 2006Date of Patent: August 4, 2009Assignee: California Institute of TechnologyInventors: James R. Heath, Yi Luo, Rob Beckman
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Patent number: 7569915Abstract: A shielding arrangement for protecting a circuit containing magnetically sensitive materials from external stray magnetic fields. A shield of a material having a relatively high permeability is formed over the magnetically sensitive materials using thin film deposition techniques. Alternatively, a planar shield is affixed directly to a surface of semiconductor die containing an integrated circuit structure.Type: GrantFiled: June 26, 2006Date of Patent: August 4, 2009Assignee: Micron Technology, Inc.Inventors: Richard K. Spielberger, Romney R. Katti
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Patent number: 7554145Abstract: An improved magnetoresistive memory device has a reduced distance between the magnetic memory element and a conductive memory line used for writing to the magnetic memory element. The reduced distance is facilitated by forming the improved magnetoresistive memory device according to a method that includes forming a mask over the magnetoresistive memory element and forming an insulating layer over the mask layer, then removing portions of the insulating layer using a planarization process. A conductive via can then be formed in the mask layer, for example using a damascene process. The conductive memory line can then be formed over the mask layer and conductive via.Type: GrantFiled: December 14, 2006Date of Patent: June 30, 2009Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Yuan-Hung Liu, Chih-Ta Wu, Lan-Lin Chao, Yeur-Luen Tu, Wen-Chin Lin, Chia-Shiung Tsai
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Patent number: 7547934Abstract: It is possible to obtain excellent heat stability even though the element is miniaturized and keep stable magnetic domains even though switching is repeated any number of times. A magneto-resistive effect element includes: a magnetization-pinned layer including a magnetic film having a spin moment oriented in a direction perpendicular to a film surface thereof and pinned in the direction; a magnetic recording layer having a spin moment oriented in a direction perpendicular to a film surface thereof; a nonmagnetic layer formed between the magnetization-pinned layer and the magnetic recording layer; and an anti-ferromagnetic film formed on at least side surfaces of the magnetization-pinned layer.Type: GrantFiled: September 27, 2007Date of Patent: June 16, 2009Assignee: Kabushiki Kaisha ToshibaInventor: Yoshiaki Saito