Magnetic Field Sensor In Integrated Circuit (e.g., In Bipolar Transistor Integrated Circuit) Patents (Class 257/427)
  • Patent number: 11515474
    Abstract: A memory device includes a semiconductor substrate, a first dielectric layer, a metal contact, an aluminum nitride layer, an aluminum oxide layer, a second dielectric layer, a metal via, and a memory stack. The first dielectric layer is over the semiconductor substrate. The metal contact passes through the first dielectric layer. The aluminum nitride layer extends along a top surface of the first dielectric layer and a top surface of the metal contact. The aluminum oxide layer extends along a top surface of the aluminum nitride layer. The second dielectric layer is over the aluminum oxide layer. The metal via passes through the second dielectric layer, the aluminum oxide layer, and the aluminum nitride layer and lands on the metal contact. The memory stack lands on the metal via.
    Type: Grant
    Filed: December 4, 2020
    Date of Patent: November 29, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Jung-Tang Wu, Szu-Ping Tung, Szu-Hua Wu, Shing-Chyang Pan, Meng-Yu Wu
  • Patent number: 11489107
    Abstract: The present disclosure relates to a method of forming an integrated chip. The method includes forming an ILD layer over a memory device over a substrate. A hard mask structure is formed over the ILD layer and a patterning structure is formed over the hard mask structure. The hard mask structure has sidewalls defining a first opening directly over the memory device and centered along a first line perpendicular to an upper surface of the substrate. The patterning structure has sidewalls defining a second opening directly over the memory device and centered along a second line parallel to the first line. The second line is laterally offset from the first line by a non-zero distance. The ILD layer is etched below an overlap of the first and second openings to define a top electrode via hole. The top electrode via hole is with a conductive material.
    Type: Grant
    Filed: September 2, 2020
    Date of Patent: November 1, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ming-Che Ku, Harry-Hak-Lay Chuang, Hung Cho Wang, Tsun Chung Tu, Jiunyu Tsai, Sheng-Huang Huang
  • Patent number: 11469372
    Abstract: The present disclosure relates to an integrated chip. The integrated chip includes a memory device surrounded by a dielectric structure disposed over a substrate. The memory device includes a data storage structure disposed between a bottom electrode and a top electrode. A top electrode via couples the top electrode to an upper interconnect wire. A first line is tangent to a first outermost sidewall of the top electrode via and a second line is tangent to an opposing second outermost sidewall of the top electrode via. The first line is oriented at a first angle with respect to a horizontal plane that is parallel to an upper surface of the substrate and the second line is oriented at a second angle with respect to the horizontal plane. The second angle is less than the first angle.
    Type: Grant
    Filed: September 2, 2020
    Date of Patent: October 11, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ming-Che Ku, Harry-Hak-Lay Chuang, Hung Cho Wang, Tsun Chung Tu, Jiunyu Tsai, Sheng-Huang Huang
  • Patent number: 11469269
    Abstract: Some embodiments relate to an integrated chip. The integrated chip includes a first memory cell overlying a substrate and a second memory cell overlying the substrate. A dielectric structure overlies the substrate. A trench extends into the dielectric structure and is spaced laterally between the first memory cell and the second memory cell. A dielectric layer is disposed within the trench.
    Type: Grant
    Filed: July 16, 2020
    Date of Patent: October 11, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Sheng-Chang Chen, Harry-Hak-Lay Chuang, Hung Cho Wang, Sheng-Huang Huang
  • Patent number: 11437433
    Abstract: Some embodiments relate to a method for forming a memory device. The method includes forming a first memory cell over a substrate and forming a second memory cell over the substrate. Further, an inter-level dielectric (ILD) layer is formed over the substrate such that the ILD layer comprises sidewalls defining a first trough between the first memory cell and the second memory cell. In addition, a first dielectric layer is formed over the ILD layer and within the first trough.
    Type: Grant
    Filed: July 16, 2020
    Date of Patent: September 6, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Sheng-Chang Chen, Harry-Hak-Lay Chuang, Hung Cho Wang, Sheng-Huang Huang
  • Patent number: 11404477
    Abstract: A memory array and a method for forming the memory array are disclosed. The memory array includes memory elements, selectors and conductive vias. Each selector includes two pairs of fin structures and a gate structure. The gate structure crosses the two pairs of fin structures. The conductive vias are electrically coupled to the two pairs of fin structures of the selectors.
    Type: Grant
    Filed: August 31, 2020
    Date of Patent: August 2, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: I-Che Lee, Huai-Ying Huang
  • Patent number: 11404413
    Abstract: A semiconductor device includes a semiconductor substrate having a first region and a second region, insulators, gate stacks, and first and second S/Ds. The first and second regions respectively includes at least one first semiconductor fin and at least one second semiconductor fin. A width of a middle portion of the first semiconductor fin is equal to widths of end portions of the first semiconductor fin. A width of a middle portion of the second semiconductor fin is smaller than widths of end portions of the second semiconductor fin. The insulators are disposed on the semiconductor substrate. The first and second semiconductor fins are sandwiched by the insulators. The gate stacks are over a portion of the first semiconductor fin and a portion of the second semiconductor fin. The first and second S/Ds respectively covers another portion of the first semiconductor fin and another portion of the second semiconductor fin.
    Type: Grant
    Filed: October 3, 2018
    Date of Patent: August 2, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kuan-Jung Chen, I-Chih Chen, Chih-Mu Huang, Kai-Di Wu, Ming-Feng Lee, Ting-Chun Kuan
  • Patent number: 11355551
    Abstract: A magnetic tunnel junction memory device includes a vertical stack of magnetic tunnel junction NOR strings located over a substrate. Each magnetic tunnel junction NOR string includes a respective semiconductor material layer that contains a semiconductor source region, a plurality of semiconductor channels, and a plurality of semiconductor drain regions, a plurality of magnetic tunnel junction memory cells having a respective first electrode that is located on a respective one of the plurality of semiconductor drain regions, and a metallic bit line contacting each second electrode of the plurality of magnetic tunnel junction memory cells. The vertical stack of magnetic tunnel junction NOR strings may be repeated along a channel direction to provide a three-dimensional magnetic tunnel junction memory device.
    Type: Grant
    Filed: June 23, 2020
    Date of Patent: June 7, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Han-Jong Chia, Bo-Feng Young, Sai-Hooi Yeong, Chenchen Jacob Wang, Meng-Han Lin, Yu-Ming Lin
  • Patent number: 11348626
    Abstract: A magnetic memory device includes a first magnetic layer extending in a first direction, a second magnetic layer that extends on and parallel to the first magnetic layer, and a conductive layer extending between the first magnetic layer and the second magnetic layer. The first magnetic layer includes a first region having magnetic moments oriented in a first rotational direction along the first direction. The second magnetic layer includes a second region having magnetic moments oriented in a second rotational direction along the first direction. The second rotational direction is different from the first rotational direction.
    Type: Grant
    Filed: March 24, 2020
    Date of Patent: May 31, 2022
    Inventors: Sung Chul Lee, Ung Hwan Pi
  • Patent number: 11342015
    Abstract: A memory device and a memory circuit is provided. The memory device includes a spin-orbit torque (SOT) layer, a magnetic tunnel junction (MTJ), a read word line, a selector and a write word line. The MTJ stands on the SOT layer. The read word line is electrically connected to the MTJ. The write word line is connected to the SOT layer through the selector. The write word line is electrically connected to the SOT layer when the selector is turned on, and the write word line is electrically isolated from the SOT layer when the selector is in an off state.
    Type: Grant
    Filed: November 24, 2020
    Date of Patent: May 24, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hung-Li Chiang, Chung-Te Lin, Shy-Jay Lin, Tzu-Chiang Chen, Ming-Yuan Song, Hon-Sum Philip Wong
  • Patent number: 11328951
    Abstract: A transistor cell including a deep via that is at least partially lined with a dielectric material. The deep via may extend down to a substrate over which the transistor is disposed. The deep via may be directly connected to a terminal of the transistor, such as the source or drain, to interconnect the transistor with an interconnect metallization level disposed in the substrate under the transistor, or on at opposite side of the substrate as the transistor. Parasitic capacitance associated with the close proximity of the deep via metallization to one or more terminals of the transistor may be reduced by lining at least a portion of the deep via sidewall with dielectric material, partially necking the deep via metallization in a region adjacent to the transistor.
    Type: Grant
    Filed: April 1, 2016
    Date of Patent: May 10, 2022
    Assignee: Intel Corporation
    Inventors: Patrick Morrow, Mauro J. Kobrinsky, Rishabh Mehandru
  • Patent number: 11322543
    Abstract: Various embodiments of the present disclosure are directed towards a memory device including a protective sidewall spacer layer that laterally encloses a memory cell. An upper inter-level dielectric (ILD) layer overlying a substrate. The memory cell is disposed with the upper ILD layer. The memory cell includes a top electrode, a bottom electrode, and a magnetic tunnel junction (MTJ) structure disposed between the top and bottom electrodes. A sidewall spacer structure laterally surrounds the memory cell. The sidewall spacer structure includes a first sidewall spacer layer, a second sidewall spacer layer, and the protective sidewall spacer layer. The first and second sidewall spacer layers comprise a first material and the protective sidewall spacer layer comprises a second material different from the first material. A conductive wire overlying the first memory cell. The conductive wire contacts the top electrode and the protective sidewall spacer layer.
    Type: Grant
    Filed: May 27, 2020
    Date of Patent: May 3, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Harry-Hak-Lay Chuang, Hung Cho Wang, Sheng-Chang Chen, Sheng-Huang Huang
  • Patent number: 11289538
    Abstract: A memory device including bit lines, auxiliary lines, selectors, and memory cells is provided. The word lines are intersected with the bit lines. The auxiliary lines are disposed between the word lines and the of bit lines. The selectors are inserted between the bit lines and the auxiliary lines. The memory cells are inserted between the word lines and the auxiliary lines.
    Type: Grant
    Filed: January 9, 2020
    Date of Patent: March 29, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ji-Feng Ying, Jhong-Sheng Wang, Tsann Lin
  • Patent number: 11283005
    Abstract: An MRAM cell has a bottom electrode, a metal tunneling junction, and a top electrode. The metal tunneling junction has a side surface between the bottom electrode and the top electrode. A thin layer on the side surface includes one or more compounds of a metal found in one of the electrodes. The thin layer has a lower conductance than the MTJ. The electrode metal may have been deposited on the side during MTJ patterning and subsequently been reacted to form a compound having a lower conductance than a nitride of the electrode metal. The thin layer may include an oxide deposited over the redeposited electrode metal. The thin layer may include a compound of the electrode metal deposited over the redeposited electrode metal. A silicon nitride spacer may be formed over the thin layer without forming nitrides of the electrode metal.
    Type: Grant
    Filed: March 26, 2020
    Date of Patent: March 22, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Joung-Wei Liou, Chin Kun Lan
  • Patent number: 11257867
    Abstract: A semiconductor device, the device including: a plurality of transistors, where at least one of the plurality of transistors includes a first single crystal channel, where at least one of the plurality of transistors includes a second single crystal channel, where the second single crystal channel is disposed above the first single crystal channel, where at least one of the plurality of transistors includes a third single crystal channel, where the third single crystal channel is disposed above the second single crystal channel, where at least one of the plurality of transistors includes a fourth single crystal channel, and where the fourth single crystal channel is disposed above the third single crystal channel; and at least one region of oxide to oxide bonds.
    Type: Grant
    Filed: December 5, 2021
    Date of Patent: February 22, 2022
    Assignee: MONOLITHIC 3D INC.
    Inventors: Deepak C. Sekar, Zvi Or-Bach
  • Patent number: 11222919
    Abstract: A spin current magnetization rotational element includes: a spin-orbit torque wiring extending in a first direction; and a first ferromagnetic layer laminated in a second direction intersecting with the spin-orbit torque wiring, wherein the first ferromagnetic layer comprises a plurality of ferromagnetic constituent layers and at least one inserted layer sandwiched between adjacent ferromagnetic constituent layers, and polarities of spin Hall angles of two layers, which sandwich at least one of the ferromagnetic constituent layers among the plurality of the ferromagnetic constituent layers, differ.
    Type: Grant
    Filed: December 13, 2017
    Date of Patent: January 11, 2022
    Assignee: TDK CORPORATION
    Inventors: Yohei Shiokawa, Tomoyuki Sasaki
  • Patent number: 11211549
    Abstract: An integrated circuit includes a substrate, a dielectric layer over the substrate, a plurality of cells, a plurality of spacers and a plurality of conductive particles. Each of the cells includes a bottom portion in the dielectric layer and an upper portion protruding from the dielectric layer. The spacers are disposed over the dielectric layer and partially cover the upper portions of the cells, respectively. The spacers are disconnected from each other, and cover a first area of the dielectric layer and expose a second area of the dielectric layer. The conductive particles are disposed between the first area of the dielectric layer and the spacers.
    Type: Grant
    Filed: July 17, 2020
    Date of Patent: December 28, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Chang-Lin Yang, Chung-Te Lin, Han-Ting Tsai, Chien-Hua Huang
  • Patent number: 11211552
    Abstract: This spin-orbit torque magnetoresistance effect element includes: a first ferromagnetic layer; a second ferromagnetic layer; a non-magnetic layer positioned between the first ferromagnetic layer and the second ferromagnetic layer; and a spin-orbit torque wiring on which the first ferromagnetic layer is laminated, wherein the spin-orbit torque wiring extends in a second direction crossing a first direction which is an orthogonal direction of the first ferromagnetic layer, the first ferromagnetic layer includes a first laminate structure and an interfacial magnetic layer in order from the spin-orbit torque wiring side, the first laminate structure is a structure obtained by arranging a ferromagnetic conductor layer and an oxide-containing layer in order from the spin-orbit torque wiring side, the ferromagnetic conductor layer includes a ferromagnetic metal element, and the oxide-containing layer includes an oxide of a ferromagnetic metal element.
    Type: Grant
    Filed: May 13, 2019
    Date of Patent: December 28, 2021
    Assignee: TDK CORPORATION
    Inventor: Yohei Shiokawa
  • Patent number: 11156676
    Abstract: In a GSR sensor element, tm and ti of rising pulse detection are close, and the induced voltage is significantly high at tm. Thus, a variation due to the magnetic field cannot be ignored. To remove an induced voltage from an output voltage and achieve a GSR sensor with a rising pulse detection system. On the basis of the knowledge that the polarity of an induced voltage becomes opposite relative to a direction of the current flowing in a magnetic wire, if one coil includes therein two magnetic wires in which currents of opposite polarities flow, an induced current is cancelled, allowing for the detection of a voltage in proportion to a magnetic field.
    Type: Grant
    Filed: June 14, 2019
    Date of Patent: October 26, 2021
    Assignee: ASAHI INTECC CO., LTD.
    Inventors: Yoshinobu Honkura, Eiki Kikuchi, Kazue Kudo, Junichi Tanabe, Shinpei Honkura
  • Patent number: 11152561
    Abstract: A magnetic memory device includes a lower contact plug on a substrate, a magnetic tunnel junction pattern on the lower contact plug, a bottom electrode, which is between the lower contact plug and the magnetic tunnel junction pattern and is in contact with a bottom surface of the magnetic tunnel junction pattern, and a top electrode on a top surface of the magnetic tunnel junction pattern. Each of the bottom electrode, the magnetic tunnel junction pattern, and the top electrode has a thickness in a first direction, which is perpendicular to a top surface of the substrate. A first thickness of the bottom electrode is about 0.6 to 1.1 times a second thickness of the magnetic tunnel junction pattern.
    Type: Grant
    Filed: May 5, 2020
    Date of Patent: October 19, 2021
    Inventors: Bae-Seong Kwon, Yongjae Kim, Kyungtae Nam, Kuhoon Chung
  • Patent number: 11152426
    Abstract: Each memory cell in an array includes a vertical stack that comprises a bottom electrode, a memory element, and a top electrode. An etch stop dielectric layer is formed over the array of memory cells. A first dielectric matrix layer is formed over the etch stop dielectric layer. The top surface of the first dielectric matrix layer is raised in a memory array region relative to a logic region due to topography. The first dielectric matrix layer is planarized by performing a chemical mechanical planarization process using top portions of the etch stop dielectric layer. A second dielectric matrix layer is formed over the first dielectric matrix layer. Metallic cell contact structures are formed through the second dielectric matrix layer on a respective subset of the top electrodes over vertically protruding portions of the etch stop dielectric layer that laterally surround the array of vertical stacks.
    Type: Grant
    Filed: January 15, 2020
    Date of Patent: October 19, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Cheng-Tai Hsiao, Yen-Chang Chu, Hsun-Chung Kuang
  • Patent number: 11143719
    Abstract: A magnetic sensor senses a magnetic field in a predetermined magnetic sensing direction. The magnetic sensor includes a chip on which at least one magnetic device is provided. The length of the chip in the magnetic sensing direction is twice or more the length of the chip in an orthogonal direction that is orthogonal or substantially orthogonal to the magnetic sensing direction.
    Type: Grant
    Filed: November 4, 2019
    Date of Patent: October 12, 2021
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventors: Yasuhiro Shimizu, Takashi Kawanami, Nobumasa Kitamori, Noritaka Kishi
  • Patent number: 11145345
    Abstract: A storage element includes a first ferromagnetic layer; a second ferromagnetic layer; a nonmagnetic layer that is sandwiched between the first ferromagnetic layer and the second ferromagnetic layer in a first direction; a first wiring which extends in a second direction different from the first direction, and the first wiring being configured to sandwich the first ferromagnetic layer with the nonmagnetic layer in the first direction; an electrode which sandwiches the second ferromagnetic layer at least partially with the nonmagnetic layer in the first direction; and a compound part which is positioned inside the electrode and has a lower thermal conductivity than the electrode.
    Type: Grant
    Filed: March 25, 2020
    Date of Patent: October 12, 2021
    Assignee: TDK CORPORATION
    Inventors: Atsushi Tsumita, Yohei Shiokawa, Eiji Komura
  • Patent number: 11139428
    Abstract: A semiconductor device includes: a substrate comprising a magnetic tunneling junction (MTJ) region and a logic region; a first MTJ on the MTJ region; a first metal interconnection on the logic region; and a cap layer extending from a sidewall of the first MTJ to a sidewall of the first metal interconnection. Preferably, the cap layer on the MTJ region and the cap layer on the logic region comprise different thicknesses.
    Type: Grant
    Filed: September 30, 2019
    Date of Patent: October 5, 2021
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Hui-Lin Wang, Yu-Ping Wang, Chen-Yi Weng, Chin-Yang Hsieh, Si-Han Tsai, Che-Wei Chang, Jing-Yin Jhang
  • Patent number: 11127786
    Abstract: Disclosed is a magnetic memory device including a line pattern on a substrate, a magnetic tunnel junction pattern on the line pattern, and an upper conductive line that is spaced apart from the line pattern across the magnetic tunnel junction pattern and is connected to the magnetic tunnel junction pattern. The line pattern provides the magnetic tunnel junction pattern with spin-orbit torque. The line pattern includes a chalcogen-based topological insulator.
    Type: Grant
    Filed: August 30, 2019
    Date of Patent: September 21, 2021
    Assignees: SAMSUNG ELECTRONICS CO., LTD., I
    Inventors: Joonmyoung Lee, Whankyun Kim, Jeong-Heon Park, Woo Chang Lim, Junho Jeong
  • Patent number: 11049537
    Abstract: One or more embodiments described herein generally relate to patterning semiconductor film stacks. Unlike in conventional embodiments, the film stacks herein are patterned without the need of etching the magnetic tunnel junction (MTJ) stack. Instead, the film stack is etched before the MTJ stack is deposited such that the spin on carbon layer and the anti-reflective coating layer are completely removed and a trench is formed within the dielectric capping layer and the oxide layer. Thereafter, MTJ stacks are deposited on the buffer layer and on the dielectric capping layer. An oxide capping layer is deposited such that it covers the MTJ stacks. An oxide fill layer is deposited over the oxide capping layer and the film stack is polished by chemical mechanical polishing (CMP). The embodiments described herein advantageously result in no damage to the MTJ stacks since etching is not required.
    Type: Grant
    Filed: July 29, 2019
    Date of Patent: June 29, 2021
    Assignee: Applied Materials, Inc.
    Inventors: John O. Dukovic, Srinivas D. Nemani, Ellie Y. Yieh, Praburam Gopalraja, Steven Hiloong Welch, Bhargav S. Citla
  • Patent number: 11049903
    Abstract: The present disclosure relates to magnetic memory device. The magnetic memory device includes a bottom electrode, a selector layer disposed over the bottom electrode, and a MTJ stack disposed over the selector layer and comprising a reference layer and a free layer disposed over the reference layer and separated from the reference layer by a tunneling barrier layer. The magnetic memory device further includes a modulating layer disposed over the MTJ stack and a top electrode disposed over the switching threshold modulating layer. The modulating layer is configured to reinforce stability of the free layer by magnetically coupled to the free layer.
    Type: Grant
    Filed: June 9, 2020
    Date of Patent: June 29, 2021
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Katherine H. Chiang, Chung-Te Lin, Min Cao, Han-Ting Tsai, Pin-Cheng Hsu, Yen-Chung Ho
  • Patent number: 11031544
    Abstract: In some embodiments, the present application provides a memory device. The memory device includes a ferromagnetic free layer; a non-magnetic barrier layer overlying the ferromagnetic free layer; and a superparamagnetic free layer overlying the non-magnetic barrier layer.
    Type: Grant
    Filed: July 9, 2019
    Date of Patent: June 8, 2021
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Gaurav Gupta, William J. Gallagher
  • Patent number: 10971678
    Abstract: A semiconductor device includes a first and a second vertical Hall elements formed parallel to each other. Each of the first and the second vertical Hall elements includes: a semiconductor layer on the semiconductor substrate; a Hall voltage output electrode and a first and a second drive current supply electrodes each formed of an impurity region, and sequentially arranged along a straight line on the semiconductor layer; and a first electrode isolation diffusion layer between the first drive current supply electrode and the Hall voltage output electrode, and a second electrode isolation diffusion layer between the Hall voltage output electrode and the second drive current supply electrode. The first and the second drive current supply electrodes each has the second depth deeper than the first depth of the Hall voltage output electrode and the depth of each of the electrode isolation diffusion layers.
    Type: Grant
    Filed: April 22, 2019
    Date of Patent: April 6, 2021
    Assignee: ABLIC INC.
    Inventor: Takaaki Hioka
  • Patent number: 10950657
    Abstract: An integrated circuit device includes a memory portion and a logic portion. The memory portion may include a plurality of magnetoresistive devices and the logic portion may include logic circuits. The memory portion may include a plurality of metal conductors separated by a first interlayer dielectric material (ILD), wherein the first ILD is a low-k ILD or an ultra low-k ILD. And, the logic portion may include a plurality of metal conductors separated by a second interlayer dielectric material (ILD).
    Type: Grant
    Filed: November 8, 2018
    Date of Patent: March 16, 2021
    Assignee: Everspin Technologies. Inc.
    Inventors: Kerry Joseph Nagel, Sanjeev Aggarwal, Sarin A. Deshpande
  • Patent number: 10943948
    Abstract: A magnetic tunnel junction (MTJ) device includes two magnetic tunnel junction elements and a magnetic shielding layer. The two magnetic tunnel junction elements are arranged side by side. The magnetic shielding layer is disposed between the magnetic tunnel junction elements. A method of forming said magnetic tunnel junction (MTJ) device includes the following steps. An interlayer including a magnetic shielding layer is formed. The interlayer is etched to form recesses in the interlayer. The magnetic tunnel junction elements fill in the recesses. Or, a method of forming said magnetic tunnel junction (MTJ) device includes the following steps. A magnetic tunnel junction layer is formed. The magnetic tunnel junction layer is patterned to form magnetic tunnel junction elements. An interlayer including a magnetic shielding layer is formed between the magnetic tunnel junction elements.
    Type: Grant
    Filed: January 30, 2019
    Date of Patent: March 9, 2021
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Wei Chen, Hui-Lin Wang, Yu-Ru Yang, Chin-Fu Lin, Yi-Syun Chou, Chun-Yao Yang
  • Patent number: 10910553
    Abstract: A magnetoresistive random access memory (MRAM), including a bottom electrode layer on a substrate, a magnetic tunnel junction stack on the bottom electrode layer, and a top electrode layer on the magnetic tunnel junction stack, wherein the material of top electrode layer is titanium nitride, and the percentage of nitrogen in the titanium nitride gradually decreases from the top surface of top electrode layer to the bottom surface of top electrode layer.
    Type: Grant
    Filed: August 5, 2019
    Date of Patent: February 2, 2021
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Hui-Lin Wang, Chen-Yi Weng, Chin-Yang Hsieh, Yi-Hui Lee, Ying-Cheng Liu, Yi-An Shih, Jing-Yin Jhang, I-Ming Tseng, Yu-Ping Wang, Chien-Ting Lin, Kun-Chen Ho, Yi-Syun Chou, Chang-Min Li, Yi-Wei Tseng, Yu-Tsung Lai, Jun Xie
  • Patent number: 10877107
    Abstract: A magnetic field sensing device including a substrate, a plurality of magnetic flux concentrators and a plurality of magneto-resistive sensors and a plurality of magnetic setting structures is provided. The magnetic flux concentrators, the magneto-resistive sensors and the magnetic setting structures are disposed on the substrate. At least a portion of the magneto resistive sensors is disposed at two opposite sides of each of the magnetic flux concentrators. The orthogonal projection regions of each of the magnetic flux concentrators, at least a portion of the magneto-resistive sensors, and each of the magnetic setting structures on the substrate are respectively a first orthogonal projection region, a second orthogonal projection region, and a third orthogonal projection region. The third orthogonal projection region at least overlaps the first orthogonal projection region and at least a portion of the second orthogonal projection region. Furthermore, a magnetic field sensing apparatus is also provided.
    Type: Grant
    Filed: July 17, 2018
    Date of Patent: December 29, 2020
    Assignee: iSentek Inc.
    Inventors: Fu-Te Yuan, Meng-Huang Lai
  • Patent number: 10862026
    Abstract: A memory device includes a semiconductor substrate, a first dielectric layer, a metal contact, a metal nitride layer, an etch stop layer, a second dielectric layer, a metal via, and a memory stack. The first dielectric layer is over the semiconductor substrate. The metal contact passes through the first dielectric layer. The metal nitride layer spans the first dielectric layer and the metal contact. The etch stop layer extends along a top surface of the metal nitride layer, in which a thickness of the metal nitride layer is less than a thickness of the etch stop layer. The second dielectric layer is over the etch stop layer. The metal via passes through the second dielectric layer, the etch stop layer, and the metal nitride layer and lands on the metal contact. The memory stack is in contact with the metal via.
    Type: Grant
    Filed: January 13, 2020
    Date of Patent: December 8, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Jung-Tang Wu, Szu-Ping Tung, Szu-Hua Wu, Shing-Chyang Pan, Meng-Yu Wu
  • Patent number: 10861754
    Abstract: A TMR element includes a magnetic tunnel junction, a side wall portion that covers a side surface of the magnetic tunnel junction, and a minute particle region that is disposed in the side wall portion. The side wall portion includes an insulation material. The minute particle region includes the insulation material and a plurality of minute magnetic metal particles that are dispersed in the insulation material. The minute particle region is electrically connected in parallel with the magnetic tunnel junction.
    Type: Grant
    Filed: February 20, 2020
    Date of Patent: December 8, 2020
    Assignee: TDK CORPORATION
    Inventors: Zhenyao Tang, Tomoyuki Sasaki
  • Patent number: 10840439
    Abstract: Embodiments of the present invention facilitate efficient and effective increased memory cell density configuration. In one embodiment, the method comprises: forming a first pitch reference component and a second pitch reference component; forming a first pillar magnetic tunnel junction (pMTJ) located in a first level and a second pMTJ located in a second level, wherein the location of the second pMTJ with respect to the first pMTJ is coordinated based upon a reference pitch distance between the first pitch reference component and first pitch reference component. In one exemplary implementation, the first pitch reference component is a first switch coupled to the first pMTJ and the second pitch reference component is a second switch coupled to the second pMTJ. The reference component size can be based upon a minimum lithographic processing dimension.
    Type: Grant
    Filed: December 29, 2017
    Date of Patent: November 17, 2020
    Assignee: Spin Memory, Inc.
    Inventors: Mustafa Pinarbasi, Thomas Boone, Pirachi Shrivastava, Pradeep Manandhar
  • Patent number: 10833258
    Abstract: MRAM devices with in-situ encapsulation are provided. In one aspect, a method of forming an MRAM device includes: patterning an MRAM stack disposed on a dielectric into individual memory cell stacks, wherein the MRAM stack includes a bottom electrode, a MTJ, and a top electrode, and wherein the patterning is performed using an intermediate angle IBE landing on the dielectric; removing redeposited metal from the memory cell stacks using a high angle IBE; redepositing the dielectric along the sidewalls of the memory cell stacks using a low angle IBE to form a first layer of dielectric encapsulating the memory cell stacks; and depositing a second layer of dielectric, wherein the first/second layers of dielectric form a bilayer dielectric spacer structure, wherein the patterning, removing of the redeposited metal, and redepositing the dielectric steps are all performed in-situ. An MRAM device is also provided.
    Type: Grant
    Filed: May 2, 2019
    Date of Patent: November 10, 2020
    Assignee: International Business Machines Corporation
    Inventors: Ashim Dutta, Chih-Chao Yang, Daniel C. Edelstein, Karthik Yogendra, John C. Arnold
  • Patent number: 10809321
    Abstract: According to one embodiment, a magnetic sensor includes first and second elements, first and second interconnects, a first circuit portion electrically connected to the first and second interconnects and a second circuit portion electrically connected to the first and second elements. The first circuit portion supplies a first alternating current to the first interconnect and supplies a second alternating current to the second interconnect. The second circuit portion supplies a first element current to the first element and supplies a second element current to the second element. At a first time, the first alternating current has a first alternating current orientation, and the second alternating current has a second alternating current orientation. At a second time, the first alternating current has an opposite orientation to the first alternating current orientation, and the second alternating current has an opposite orientation to the second alternating current orientation.
    Type: Grant
    Filed: February 15, 2019
    Date of Patent: October 20, 2020
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Akira Kikitsu, Satoshi Shirotori, Kenichiro Yamada
  • Patent number: 10790439
    Abstract: The present disclosure, in some embodiments, relates to an integrated chip. The integrated chip includes a magnetoresistive random access memory (MRAM) device surrounded by a dielectric structure disposed over a substrate. The MRAM device includes a magnetic tunnel junction disposed between a bottom electrode and a top electrode. A bottom electrode via couples the bottom electrode to a lower interconnect wire. A top electrode via couples the top electrode to an upper interconnect wire. A bottom surface of the top electrode via has a first width that is smaller than a second width of a bottom surface of the bottom electrode via.
    Type: Grant
    Filed: May 20, 2019
    Date of Patent: September 29, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Ming-Che Ku, Harry-Hak-Lay Chuang, Hung Cho Wang, Tsun Chung Tu, Jiunyu Tsai, Sheng-Huang Huang
  • Patent number: 10727274
    Abstract: Some embodiments relate to a memory device. The memory device includes a first magnetoresistive random-access memory (MRAM) cell disposed on a substrate, and a second MRAM cell disposed on the substrate. An inter-level dielectric (ILD) layer is disposed over the substrate. The ILD layer comprises sidewalls defining a trough between the first and second MRAM cells. A dielectric layer disposed over the ILD layer. The dielectric layer completely fills the trough.
    Type: Grant
    Filed: May 15, 2019
    Date of Patent: July 28, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Sheng-Chang Chen, Harry-Hak-Lay Chuang, Hung Cho Wang, Sheng-Huang Huang
  • Patent number: 10663536
    Abstract: A magnetoresistive sensor wafer layout scheme used for a laser writing system and laser scanning method are disclosed. The layout scheme comprises a magnetoresistive multilayer film including an antiferromagnetic pinning layer arranged into a rectangular array of sensor dice on the wafer surface. Pinning layers of magnetoresistive sensing units are magnetically oriented and directionally aligned by the laser writing system. Sensing units are electrically connected into bridge arms electrically connected into a magnetoresistive sensor. Magnetoresistive sensing units in the dice are arranged into at least two spatially-isolated magnetoresistive orientation groups. In the magnetoresistive orientation groups, pinning layers of the sensing units have an angle of magnetic orientation of 0-360 degrees. Angles of magnetic orientation of two adjacent magnetoresistive orientation groups are different.
    Type: Grant
    Filed: September 13, 2017
    Date of Patent: May 26, 2020
    Assignee: MultiDimension Technology Co., Ltd.
    Inventors: James Geza Deak, Zhimin Zhou
  • Patent number: 10622132
    Abstract: Described is an apparatus which comprises: an input magnet formed of one or more materials with a sufficiently high anisotropy and sufficiently low magnetic saturation to increase injection of spin currents; and a first interface layer coupled to the input magnet, wherein the first interface layer is formed of non-magnetic material such that the first interface layer and the input magnet together have sufficiently matched atomistic crystalline layers.
    Type: Grant
    Filed: June 24, 2015
    Date of Patent: April 14, 2020
    Assignee: Intel Corporation
    Inventors: Sasikanth Manipatruni, Anurag Chaudhry, Dmitri E. Nikonov, David J. Michalak, Ian A. Young
  • Patent number: 10615103
    Abstract: Provided is a semiconductor device according to an embodiment including a first electrode terminal containing copper, a second electrode terminal containing copper, a semiconductor chip provide the first electrode terminal and provided inside the first electrode terminal, a metal member provided on the semiconductor chip, protruding to an outside of the semiconductor chip in at least two directions, electrically connected to the second electrode terminal, and containing copper, and a mold resin surrounding the semiconductor chip.
    Type: Grant
    Filed: July 5, 2018
    Date of Patent: April 7, 2020
    Assignees: Kabushiki Kaisha Toshiba, Toshiba Electronic Devices & Storage Corporation
    Inventor: Kazuhiro Inoue
  • Patent number: 10586920
    Abstract: A semiconductor structure is disclosed herein. The semiconductor structure includes two or more pillar structures disposed over a top surface of a substrate. The semiconductor structure further includes two or more contacts to the two or more pillar structures. The semiconductor structure further includes an insulator disposed between the two or more pillar structures and the two or more contacts. The two or more contacts are self-aligned to the two or more pillar structures.
    Type: Grant
    Filed: June 28, 2018
    Date of Patent: March 10, 2020
    Assignee: International Business Machines Corporation
    Inventors: Anthony J. Annunziata, Daniel C. Edelstein, Eugene J. O'Sullivan, Henry K. Utomo
  • Patent number: 10564055
    Abstract: A stress sensor includes a semiconductor die to which a mechanical stress is applied. The semiconductor die includes at least one bipolar junction transistor; at least one current source configured to inject at least one current through the at least one bipolar junction transistor; and a processing circuit configured to measure a first current gain and a second current gain of the at least one bipolar junction transistor based on the at least one injected current, to determine a first mechanical stress level based on the first current gain, to determine a second mechanical stress level based on the second current gain, and to generate a mechanical stress level signal based on the first mechanical stress level and the second mechanical stress level, wherein the mechanical stress level signal represents the applied mechanical stress, at least a portion of which is applied to the at least one bipolar junction transistor.
    Type: Grant
    Filed: July 31, 2018
    Date of Patent: February 18, 2020
    Assignee: Infineon Technologies AG
    Inventor: Udo Ausserlechner
  • Patent number: 10566521
    Abstract: Magnetic switching devices, including magnetic memory devices, are provided. The devices use high-quality crystalline films of 4d or 5d transition metal perovskite having a strong spin-orbit coupling (SOC) to produce spin-orbit torque in adjacent ferromagnetic materials via a strong spin-Hall effect. Spin-orbit torque can be generated by the devices with a high efficiency, even at or near room temperature.
    Type: Grant
    Filed: June 27, 2018
    Date of Patent: February 18, 2020
    Assignee: Wisconsin Alumni Research Foundation
    Inventors: Chang-Beom Eom, Tianxiang Nan, Trevor Jeffrey Anderson
  • Patent number: 10557894
    Abstract: In a system and method for correcting a stress-impaired signal in a circuit, a calibration circuit produces a first calibrated voltage based on a base-emitter voltage of one or more pnp transistors, a second calibrated voltage based on a base-emitter voltage of one or more npn transistors, and a voltage proportional to absolute temperature. A set of reference values are generated based on these voltages. A gain correction factor is calculated based on a function of the set of reference values and a set of temperature-dependent values, and the stress-impaired signal is corrected based on the gain correction factor.
    Type: Grant
    Filed: August 7, 2017
    Date of Patent: February 11, 2020
    Assignee: Linear Technology Holding LLC
    Inventors: Kalin V. Lazarov, Robert C. Chiacchia
  • Patent number: 10529399
    Abstract: According to one embodiment, a magnetic memory device includes a conductive layer, a first magnetic layer, a second magnetic layer, and a first nonmagnetic layer. The conductive layer includes a first region, a second region, and a third region between the first region and the second region. The second magnetic layer is provided between the third region and the first magnetic layer in a first direction crossing a second direction. The second direction is from the first region toward the second region. The first nonmagnetic layer is provided between the first magnetic layer and the second magnetic layer. The third region includes first and second end portions. The first end portion includes a first protrusion. The second end portion includes a second protrusion. A first position along the second direction of the first protrusion is different from a second position along the second direction of the second protrusion.
    Type: Grant
    Filed: August 21, 2018
    Date of Patent: January 7, 2020
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yuichi Ohsawa, Mariko Shimizu, Satoshi Shirotori, Hideyuki Sugiyama, Altansargai Buyandalai, Hiroaki Yoda, Katsuhiko Koui, Tomoaki Inokuchi, Naoharu Shimomura
  • Patent number: 10429455
    Abstract: A hall element is provided to suppress variations in a hall output voltage of the hall element due to a stacked structure of an electrode portion, an insulating film, and a magnetosensitive portion. The hall element may include a substrate, a magnetosensitive portion formed on the substrate, an insulating film formed on the magnetosensitive portion, electrode portions formed on the insulating film, and contact portions electrically connecting the electrode portions and the magnetosensitive portion to each other through the insulating film, in which the entire region surrounded by the contact portions is included in the region of the magnetosensitive portion, and the proportion of regions extending with the corresponding contact portions of the electrode portions as reference points is set to be equal to or less than a predetermined value in a quadrangle formed by the region surrounded by the contact portions.
    Type: Grant
    Filed: March 22, 2018
    Date of Patent: October 1, 2019
    Assignee: Asahi Kasei Microdevices Corporation
    Inventors: Tomoya Shoji, Tetsuya Takahashi
  • Patent number: 10431734
    Abstract: A perpendicular magnetic tunnel junction may include a free layer, a reference layer, and a barrier layer. The barrier layer may be arranged between the free layer and the reference layer. The barrier layer may include a first interface and a second interface. The first interface may face the free layer, and a second interface may face the reference layer. The first interface may not physically correlate with the second interface.
    Type: Grant
    Filed: March 23, 2017
    Date of Patent: October 1, 2019
    Assignee: QUALCOMM Incorporated
    Inventors: Chando Park, Jimmy Jianan Kan, Peiyuan Wang, Seung Hyuk Kang