Magnetic Field Sensor In Integrated Circuit (e.g., In Bipolar Transistor Integrated Circuit) Patents (Class 257/427)
  • Patent number: 11156676
    Abstract: In a GSR sensor element, tm and ti of rising pulse detection are close, and the induced voltage is significantly high at tm. Thus, a variation due to the magnetic field cannot be ignored. To remove an induced voltage from an output voltage and achieve a GSR sensor with a rising pulse detection system. On the basis of the knowledge that the polarity of an induced voltage becomes opposite relative to a direction of the current flowing in a magnetic wire, if one coil includes therein two magnetic wires in which currents of opposite polarities flow, an induced current is cancelled, allowing for the detection of a voltage in proportion to a magnetic field.
    Type: Grant
    Filed: June 14, 2019
    Date of Patent: October 26, 2021
    Assignee: ASAHI INTECC CO., LTD.
    Inventors: Yoshinobu Honkura, Eiki Kikuchi, Kazue Kudo, Junichi Tanabe, Shinpei Honkura
  • Patent number: 11152426
    Abstract: Each memory cell in an array includes a vertical stack that comprises a bottom electrode, a memory element, and a top electrode. An etch stop dielectric layer is formed over the array of memory cells. A first dielectric matrix layer is formed over the etch stop dielectric layer. The top surface of the first dielectric matrix layer is raised in a memory array region relative to a logic region due to topography. The first dielectric matrix layer is planarized by performing a chemical mechanical planarization process using top portions of the etch stop dielectric layer. A second dielectric matrix layer is formed over the first dielectric matrix layer. Metallic cell contact structures are formed through the second dielectric matrix layer on a respective subset of the top electrodes over vertically protruding portions of the etch stop dielectric layer that laterally surround the array of vertical stacks.
    Type: Grant
    Filed: January 15, 2020
    Date of Patent: October 19, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Cheng-Tai Hsiao, Yen-Chang Chu, Hsun-Chung Kuang
  • Patent number: 11152561
    Abstract: A magnetic memory device includes a lower contact plug on a substrate, a magnetic tunnel junction pattern on the lower contact plug, a bottom electrode, which is between the lower contact plug and the magnetic tunnel junction pattern and is in contact with a bottom surface of the magnetic tunnel junction pattern, and a top electrode on a top surface of the magnetic tunnel junction pattern. Each of the bottom electrode, the magnetic tunnel junction pattern, and the top electrode has a thickness in a first direction, which is perpendicular to a top surface of the substrate. A first thickness of the bottom electrode is about 0.6 to 1.1 times a second thickness of the magnetic tunnel junction pattern.
    Type: Grant
    Filed: May 5, 2020
    Date of Patent: October 19, 2021
    Inventors: Bae-Seong Kwon, Yongjae Kim, Kyungtae Nam, Kuhoon Chung
  • Patent number: 11143719
    Abstract: A magnetic sensor senses a magnetic field in a predetermined magnetic sensing direction. The magnetic sensor includes a chip on which at least one magnetic device is provided. The length of the chip in the magnetic sensing direction is twice or more the length of the chip in an orthogonal direction that is orthogonal or substantially orthogonal to the magnetic sensing direction.
    Type: Grant
    Filed: November 4, 2019
    Date of Patent: October 12, 2021
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventors: Yasuhiro Shimizu, Takashi Kawanami, Nobumasa Kitamori, Noritaka Kishi
  • Patent number: 11145345
    Abstract: A storage element includes a first ferromagnetic layer; a second ferromagnetic layer; a nonmagnetic layer that is sandwiched between the first ferromagnetic layer and the second ferromagnetic layer in a first direction; a first wiring which extends in a second direction different from the first direction, and the first wiring being configured to sandwich the first ferromagnetic layer with the nonmagnetic layer in the first direction; an electrode which sandwiches the second ferromagnetic layer at least partially with the nonmagnetic layer in the first direction; and a compound part which is positioned inside the electrode and has a lower thermal conductivity than the electrode.
    Type: Grant
    Filed: March 25, 2020
    Date of Patent: October 12, 2021
    Assignee: TDK CORPORATION
    Inventors: Atsushi Tsumita, Yohei Shiokawa, Eiji Komura
  • Patent number: 11139428
    Abstract: A semiconductor device includes: a substrate comprising a magnetic tunneling junction (MTJ) region and a logic region; a first MTJ on the MTJ region; a first metal interconnection on the logic region; and a cap layer extending from a sidewall of the first MTJ to a sidewall of the first metal interconnection. Preferably, the cap layer on the MTJ region and the cap layer on the logic region comprise different thicknesses.
    Type: Grant
    Filed: September 30, 2019
    Date of Patent: October 5, 2021
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Hui-Lin Wang, Yu-Ping Wang, Chen-Yi Weng, Chin-Yang Hsieh, Si-Han Tsai, Che-Wei Chang, Jing-Yin Jhang
  • Patent number: 11127786
    Abstract: Disclosed is a magnetic memory device including a line pattern on a substrate, a magnetic tunnel junction pattern on the line pattern, and an upper conductive line that is spaced apart from the line pattern across the magnetic tunnel junction pattern and is connected to the magnetic tunnel junction pattern. The line pattern provides the magnetic tunnel junction pattern with spin-orbit torque. The line pattern includes a chalcogen-based topological insulator.
    Type: Grant
    Filed: August 30, 2019
    Date of Patent: September 21, 2021
    Assignees: SAMSUNG ELECTRONICS CO., LTD., I
    Inventors: Joonmyoung Lee, Whankyun Kim, Jeong-Heon Park, Woo Chang Lim, Junho Jeong
  • Patent number: 11049537
    Abstract: One or more embodiments described herein generally relate to patterning semiconductor film stacks. Unlike in conventional embodiments, the film stacks herein are patterned without the need of etching the magnetic tunnel junction (MTJ) stack. Instead, the film stack is etched before the MTJ stack is deposited such that the spin on carbon layer and the anti-reflective coating layer are completely removed and a trench is formed within the dielectric capping layer and the oxide layer. Thereafter, MTJ stacks are deposited on the buffer layer and on the dielectric capping layer. An oxide capping layer is deposited such that it covers the MTJ stacks. An oxide fill layer is deposited over the oxide capping layer and the film stack is polished by chemical mechanical polishing (CMP). The embodiments described herein advantageously result in no damage to the MTJ stacks since etching is not required.
    Type: Grant
    Filed: July 29, 2019
    Date of Patent: June 29, 2021
    Assignee: Applied Materials, Inc.
    Inventors: John O. Dukovic, Srinivas D. Nemani, Ellie Y. Yieh, Praburam Gopalraja, Steven Hiloong Welch, Bhargav S. Citla
  • Patent number: 11049903
    Abstract: The present disclosure relates to magnetic memory device. The magnetic memory device includes a bottom electrode, a selector layer disposed over the bottom electrode, and a MTJ stack disposed over the selector layer and comprising a reference layer and a free layer disposed over the reference layer and separated from the reference layer by a tunneling barrier layer. The magnetic memory device further includes a modulating layer disposed over the MTJ stack and a top electrode disposed over the switching threshold modulating layer. The modulating layer is configured to reinforce stability of the free layer by magnetically coupled to the free layer.
    Type: Grant
    Filed: June 9, 2020
    Date of Patent: June 29, 2021
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Katherine H. Chiang, Chung-Te Lin, Min Cao, Han-Ting Tsai, Pin-Cheng Hsu, Yen-Chung Ho
  • Patent number: 11031544
    Abstract: In some embodiments, the present application provides a memory device. The memory device includes a ferromagnetic free layer; a non-magnetic barrier layer overlying the ferromagnetic free layer; and a superparamagnetic free layer overlying the non-magnetic barrier layer.
    Type: Grant
    Filed: July 9, 2019
    Date of Patent: June 8, 2021
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Gaurav Gupta, William J. Gallagher
  • Patent number: 10971678
    Abstract: A semiconductor device includes a first and a second vertical Hall elements formed parallel to each other. Each of the first and the second vertical Hall elements includes: a semiconductor layer on the semiconductor substrate; a Hall voltage output electrode and a first and a second drive current supply electrodes each formed of an impurity region, and sequentially arranged along a straight line on the semiconductor layer; and a first electrode isolation diffusion layer between the first drive current supply electrode and the Hall voltage output electrode, and a second electrode isolation diffusion layer between the Hall voltage output electrode and the second drive current supply electrode. The first and the second drive current supply electrodes each has the second depth deeper than the first depth of the Hall voltage output electrode and the depth of each of the electrode isolation diffusion layers.
    Type: Grant
    Filed: April 22, 2019
    Date of Patent: April 6, 2021
    Assignee: ABLIC INC.
    Inventor: Takaaki Hioka
  • Patent number: 10950657
    Abstract: An integrated circuit device includes a memory portion and a logic portion. The memory portion may include a plurality of magnetoresistive devices and the logic portion may include logic circuits. The memory portion may include a plurality of metal conductors separated by a first interlayer dielectric material (ILD), wherein the first ILD is a low-k ILD or an ultra low-k ILD. And, the logic portion may include a plurality of metal conductors separated by a second interlayer dielectric material (ILD).
    Type: Grant
    Filed: November 8, 2018
    Date of Patent: March 16, 2021
    Assignee: Everspin Technologies. Inc.
    Inventors: Kerry Joseph Nagel, Sanjeev Aggarwal, Sarin A. Deshpande
  • Patent number: 10943948
    Abstract: A magnetic tunnel junction (MTJ) device includes two magnetic tunnel junction elements and a magnetic shielding layer. The two magnetic tunnel junction elements are arranged side by side. The magnetic shielding layer is disposed between the magnetic tunnel junction elements. A method of forming said magnetic tunnel junction (MTJ) device includes the following steps. An interlayer including a magnetic shielding layer is formed. The interlayer is etched to form recesses in the interlayer. The magnetic tunnel junction elements fill in the recesses. Or, a method of forming said magnetic tunnel junction (MTJ) device includes the following steps. A magnetic tunnel junction layer is formed. The magnetic tunnel junction layer is patterned to form magnetic tunnel junction elements. An interlayer including a magnetic shielding layer is formed between the magnetic tunnel junction elements.
    Type: Grant
    Filed: January 30, 2019
    Date of Patent: March 9, 2021
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Wei Chen, Hui-Lin Wang, Yu-Ru Yang, Chin-Fu Lin, Yi-Syun Chou, Chun-Yao Yang
  • Patent number: 10910553
    Abstract: A magnetoresistive random access memory (MRAM), including a bottom electrode layer on a substrate, a magnetic tunnel junction stack on the bottom electrode layer, and a top electrode layer on the magnetic tunnel junction stack, wherein the material of top electrode layer is titanium nitride, and the percentage of nitrogen in the titanium nitride gradually decreases from the top surface of top electrode layer to the bottom surface of top electrode layer.
    Type: Grant
    Filed: August 5, 2019
    Date of Patent: February 2, 2021
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Hui-Lin Wang, Chen-Yi Weng, Chin-Yang Hsieh, Yi-Hui Lee, Ying-Cheng Liu, Yi-An Shih, Jing-Yin Jhang, I-Ming Tseng, Yu-Ping Wang, Chien-Ting Lin, Kun-Chen Ho, Yi-Syun Chou, Chang-Min Li, Yi-Wei Tseng, Yu-Tsung Lai, Jun Xie
  • Patent number: 10877107
    Abstract: A magnetic field sensing device including a substrate, a plurality of magnetic flux concentrators and a plurality of magneto-resistive sensors and a plurality of magnetic setting structures is provided. The magnetic flux concentrators, the magneto-resistive sensors and the magnetic setting structures are disposed on the substrate. At least a portion of the magneto resistive sensors is disposed at two opposite sides of each of the magnetic flux concentrators. The orthogonal projection regions of each of the magnetic flux concentrators, at least a portion of the magneto-resistive sensors, and each of the magnetic setting structures on the substrate are respectively a first orthogonal projection region, a second orthogonal projection region, and a third orthogonal projection region. The third orthogonal projection region at least overlaps the first orthogonal projection region and at least a portion of the second orthogonal projection region. Furthermore, a magnetic field sensing apparatus is also provided.
    Type: Grant
    Filed: July 17, 2018
    Date of Patent: December 29, 2020
    Assignee: iSentek Inc.
    Inventors: Fu-Te Yuan, Meng-Huang Lai
  • Patent number: 10862026
    Abstract: A memory device includes a semiconductor substrate, a first dielectric layer, a metal contact, a metal nitride layer, an etch stop layer, a second dielectric layer, a metal via, and a memory stack. The first dielectric layer is over the semiconductor substrate. The metal contact passes through the first dielectric layer. The metal nitride layer spans the first dielectric layer and the metal contact. The etch stop layer extends along a top surface of the metal nitride layer, in which a thickness of the metal nitride layer is less than a thickness of the etch stop layer. The second dielectric layer is over the etch stop layer. The metal via passes through the second dielectric layer, the etch stop layer, and the metal nitride layer and lands on the metal contact. The memory stack is in contact with the metal via.
    Type: Grant
    Filed: January 13, 2020
    Date of Patent: December 8, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Jung-Tang Wu, Szu-Ping Tung, Szu-Hua Wu, Shing-Chyang Pan, Meng-Yu Wu
  • Patent number: 10861754
    Abstract: A TMR element includes a magnetic tunnel junction, a side wall portion that covers a side surface of the magnetic tunnel junction, and a minute particle region that is disposed in the side wall portion. The side wall portion includes an insulation material. The minute particle region includes the insulation material and a plurality of minute magnetic metal particles that are dispersed in the insulation material. The minute particle region is electrically connected in parallel with the magnetic tunnel junction.
    Type: Grant
    Filed: February 20, 2020
    Date of Patent: December 8, 2020
    Assignee: TDK CORPORATION
    Inventors: Zhenyao Tang, Tomoyuki Sasaki
  • Patent number: 10840439
    Abstract: Embodiments of the present invention facilitate efficient and effective increased memory cell density configuration. In one embodiment, the method comprises: forming a first pitch reference component and a second pitch reference component; forming a first pillar magnetic tunnel junction (pMTJ) located in a first level and a second pMTJ located in a second level, wherein the location of the second pMTJ with respect to the first pMTJ is coordinated based upon a reference pitch distance between the first pitch reference component and first pitch reference component. In one exemplary implementation, the first pitch reference component is a first switch coupled to the first pMTJ and the second pitch reference component is a second switch coupled to the second pMTJ. The reference component size can be based upon a minimum lithographic processing dimension.
    Type: Grant
    Filed: December 29, 2017
    Date of Patent: November 17, 2020
    Assignee: Spin Memory, Inc.
    Inventors: Mustafa Pinarbasi, Thomas Boone, Pirachi Shrivastava, Pradeep Manandhar
  • Patent number: 10833258
    Abstract: MRAM devices with in-situ encapsulation are provided. In one aspect, a method of forming an MRAM device includes: patterning an MRAM stack disposed on a dielectric into individual memory cell stacks, wherein the MRAM stack includes a bottom electrode, a MTJ, and a top electrode, and wherein the patterning is performed using an intermediate angle IBE landing on the dielectric; removing redeposited metal from the memory cell stacks using a high angle IBE; redepositing the dielectric along the sidewalls of the memory cell stacks using a low angle IBE to form a first layer of dielectric encapsulating the memory cell stacks; and depositing a second layer of dielectric, wherein the first/second layers of dielectric form a bilayer dielectric spacer structure, wherein the patterning, removing of the redeposited metal, and redepositing the dielectric steps are all performed in-situ. An MRAM device is also provided.
    Type: Grant
    Filed: May 2, 2019
    Date of Patent: November 10, 2020
    Assignee: International Business Machines Corporation
    Inventors: Ashim Dutta, Chih-Chao Yang, Daniel C. Edelstein, Karthik Yogendra, John C. Arnold
  • Patent number: 10809321
    Abstract: According to one embodiment, a magnetic sensor includes first and second elements, first and second interconnects, a first circuit portion electrically connected to the first and second interconnects and a second circuit portion electrically connected to the first and second elements. The first circuit portion supplies a first alternating current to the first interconnect and supplies a second alternating current to the second interconnect. The second circuit portion supplies a first element current to the first element and supplies a second element current to the second element. At a first time, the first alternating current has a first alternating current orientation, and the second alternating current has a second alternating current orientation. At a second time, the first alternating current has an opposite orientation to the first alternating current orientation, and the second alternating current has an opposite orientation to the second alternating current orientation.
    Type: Grant
    Filed: February 15, 2019
    Date of Patent: October 20, 2020
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Akira Kikitsu, Satoshi Shirotori, Kenichiro Yamada
  • Patent number: 10790439
    Abstract: The present disclosure, in some embodiments, relates to an integrated chip. The integrated chip includes a magnetoresistive random access memory (MRAM) device surrounded by a dielectric structure disposed over a substrate. The MRAM device includes a magnetic tunnel junction disposed between a bottom electrode and a top electrode. A bottom electrode via couples the bottom electrode to a lower interconnect wire. A top electrode via couples the top electrode to an upper interconnect wire. A bottom surface of the top electrode via has a first width that is smaller than a second width of a bottom surface of the bottom electrode via.
    Type: Grant
    Filed: May 20, 2019
    Date of Patent: September 29, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Ming-Che Ku, Harry-Hak-Lay Chuang, Hung Cho Wang, Tsun Chung Tu, Jiunyu Tsai, Sheng-Huang Huang
  • Patent number: 10727274
    Abstract: Some embodiments relate to a memory device. The memory device includes a first magnetoresistive random-access memory (MRAM) cell disposed on a substrate, and a second MRAM cell disposed on the substrate. An inter-level dielectric (ILD) layer is disposed over the substrate. The ILD layer comprises sidewalls defining a trough between the first and second MRAM cells. A dielectric layer disposed over the ILD layer. The dielectric layer completely fills the trough.
    Type: Grant
    Filed: May 15, 2019
    Date of Patent: July 28, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Sheng-Chang Chen, Harry-Hak-Lay Chuang, Hung Cho Wang, Sheng-Huang Huang
  • Patent number: 10663536
    Abstract: A magnetoresistive sensor wafer layout scheme used for a laser writing system and laser scanning method are disclosed. The layout scheme comprises a magnetoresistive multilayer film including an antiferromagnetic pinning layer arranged into a rectangular array of sensor dice on the wafer surface. Pinning layers of magnetoresistive sensing units are magnetically oriented and directionally aligned by the laser writing system. Sensing units are electrically connected into bridge arms electrically connected into a magnetoresistive sensor. Magnetoresistive sensing units in the dice are arranged into at least two spatially-isolated magnetoresistive orientation groups. In the magnetoresistive orientation groups, pinning layers of the sensing units have an angle of magnetic orientation of 0-360 degrees. Angles of magnetic orientation of two adjacent magnetoresistive orientation groups are different.
    Type: Grant
    Filed: September 13, 2017
    Date of Patent: May 26, 2020
    Assignee: MultiDimension Technology Co., Ltd.
    Inventors: James Geza Deak, Zhimin Zhou
  • Patent number: 10622132
    Abstract: Described is an apparatus which comprises: an input magnet formed of one or more materials with a sufficiently high anisotropy and sufficiently low magnetic saturation to increase injection of spin currents; and a first interface layer coupled to the input magnet, wherein the first interface layer is formed of non-magnetic material such that the first interface layer and the input magnet together have sufficiently matched atomistic crystalline layers.
    Type: Grant
    Filed: June 24, 2015
    Date of Patent: April 14, 2020
    Assignee: Intel Corporation
    Inventors: Sasikanth Manipatruni, Anurag Chaudhry, Dmitri E. Nikonov, David J. Michalak, Ian A. Young
  • Patent number: 10615103
    Abstract: Provided is a semiconductor device according to an embodiment including a first electrode terminal containing copper, a second electrode terminal containing copper, a semiconductor chip provide the first electrode terminal and provided inside the first electrode terminal, a metal member provided on the semiconductor chip, protruding to an outside of the semiconductor chip in at least two directions, electrically connected to the second electrode terminal, and containing copper, and a mold resin surrounding the semiconductor chip.
    Type: Grant
    Filed: July 5, 2018
    Date of Patent: April 7, 2020
    Assignees: Kabushiki Kaisha Toshiba, Toshiba Electronic Devices & Storage Corporation
    Inventor: Kazuhiro Inoue
  • Patent number: 10586920
    Abstract: A semiconductor structure is disclosed herein. The semiconductor structure includes two or more pillar structures disposed over a top surface of a substrate. The semiconductor structure further includes two or more contacts to the two or more pillar structures. The semiconductor structure further includes an insulator disposed between the two or more pillar structures and the two or more contacts. The two or more contacts are self-aligned to the two or more pillar structures.
    Type: Grant
    Filed: June 28, 2018
    Date of Patent: March 10, 2020
    Assignee: International Business Machines Corporation
    Inventors: Anthony J. Annunziata, Daniel C. Edelstein, Eugene J. O'Sullivan, Henry K. Utomo
  • Patent number: 10564055
    Abstract: A stress sensor includes a semiconductor die to which a mechanical stress is applied. The semiconductor die includes at least one bipolar junction transistor; at least one current source configured to inject at least one current through the at least one bipolar junction transistor; and a processing circuit configured to measure a first current gain and a second current gain of the at least one bipolar junction transistor based on the at least one injected current, to determine a first mechanical stress level based on the first current gain, to determine a second mechanical stress level based on the second current gain, and to generate a mechanical stress level signal based on the first mechanical stress level and the second mechanical stress level, wherein the mechanical stress level signal represents the applied mechanical stress, at least a portion of which is applied to the at least one bipolar junction transistor.
    Type: Grant
    Filed: July 31, 2018
    Date of Patent: February 18, 2020
    Assignee: Infineon Technologies AG
    Inventor: Udo Ausserlechner
  • Patent number: 10566521
    Abstract: Magnetic switching devices, including magnetic memory devices, are provided. The devices use high-quality crystalline films of 4d or 5d transition metal perovskite having a strong spin-orbit coupling (SOC) to produce spin-orbit torque in adjacent ferromagnetic materials via a strong spin-Hall effect. Spin-orbit torque can be generated by the devices with a high efficiency, even at or near room temperature.
    Type: Grant
    Filed: June 27, 2018
    Date of Patent: February 18, 2020
    Assignee: Wisconsin Alumni Research Foundation
    Inventors: Chang-Beom Eom, Tianxiang Nan, Trevor Jeffrey Anderson
  • Patent number: 10557894
    Abstract: In a system and method for correcting a stress-impaired signal in a circuit, a calibration circuit produces a first calibrated voltage based on a base-emitter voltage of one or more pnp transistors, a second calibrated voltage based on a base-emitter voltage of one or more npn transistors, and a voltage proportional to absolute temperature. A set of reference values are generated based on these voltages. A gain correction factor is calculated based on a function of the set of reference values and a set of temperature-dependent values, and the stress-impaired signal is corrected based on the gain correction factor.
    Type: Grant
    Filed: August 7, 2017
    Date of Patent: February 11, 2020
    Assignee: Linear Technology Holding LLC
    Inventors: Kalin V. Lazarov, Robert C. Chiacchia
  • Patent number: 10529399
    Abstract: According to one embodiment, a magnetic memory device includes a conductive layer, a first magnetic layer, a second magnetic layer, and a first nonmagnetic layer. The conductive layer includes a first region, a second region, and a third region between the first region and the second region. The second magnetic layer is provided between the third region and the first magnetic layer in a first direction crossing a second direction. The second direction is from the first region toward the second region. The first nonmagnetic layer is provided between the first magnetic layer and the second magnetic layer. The third region includes first and second end portions. The first end portion includes a first protrusion. The second end portion includes a second protrusion. A first position along the second direction of the first protrusion is different from a second position along the second direction of the second protrusion.
    Type: Grant
    Filed: August 21, 2018
    Date of Patent: January 7, 2020
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yuichi Ohsawa, Mariko Shimizu, Satoshi Shirotori, Hideyuki Sugiyama, Altansargai Buyandalai, Hiroaki Yoda, Katsuhiko Koui, Tomoaki Inokuchi, Naoharu Shimomura
  • Patent number: 10429455
    Abstract: A hall element is provided to suppress variations in a hall output voltage of the hall element due to a stacked structure of an electrode portion, an insulating film, and a magnetosensitive portion. The hall element may include a substrate, a magnetosensitive portion formed on the substrate, an insulating film formed on the magnetosensitive portion, electrode portions formed on the insulating film, and contact portions electrically connecting the electrode portions and the magnetosensitive portion to each other through the insulating film, in which the entire region surrounded by the contact portions is included in the region of the magnetosensitive portion, and the proportion of regions extending with the corresponding contact portions of the electrode portions as reference points is set to be equal to or less than a predetermined value in a quadrangle formed by the region surrounded by the contact portions.
    Type: Grant
    Filed: March 22, 2018
    Date of Patent: October 1, 2019
    Assignee: Asahi Kasei Microdevices Corporation
    Inventors: Tomoya Shoji, Tetsuya Takahashi
  • Patent number: 10431734
    Abstract: A perpendicular magnetic tunnel junction may include a free layer, a reference layer, and a barrier layer. The barrier layer may be arranged between the free layer and the reference layer. The barrier layer may include a first interface and a second interface. The first interface may face the free layer, and a second interface may face the reference layer. The first interface may not physically correlate with the second interface.
    Type: Grant
    Filed: March 23, 2017
    Date of Patent: October 1, 2019
    Assignee: QUALCOMM Incorporated
    Inventors: Chando Park, Jimmy Jianan Kan, Peiyuan Wang, Seung Hyuk Kang
  • Patent number: 10424575
    Abstract: Based on a basic idea to effectively utilize a space created in a third wiring layer (M3) by a zero-th wiring layer (M0) which can exist by miniaturization of a FINFET, an auxiliary line AL is arranged in the space created in the third wiring layer, and this auxiliary line AL and a word line WL are electrically connected to each other. Thus, a measure (device) based on such new knowledge that rising time of a word line voltage is largely affected by a wiring resistance of the word line is achieved, a high-speed operation in an SRAM using the FINFET is achieved.
    Type: Grant
    Filed: March 26, 2015
    Date of Patent: September 24, 2019
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Yuta Yoshida, Makoto Yabuuchi, Yoshisato Yokoyama
  • Patent number: 10424616
    Abstract: Integrated circuit devices including vertical Hall elements and lateral Hall elements and methods for fabricating integrated circuits are provided. In an exemplary embodiment, an integrated circuit device includes a substrate including a lateral element region and a vertical element region. The integrated circuit device includes a well in the lateral element region and in the vertical element region of the substrate. Further, the integrated circuit device includes an insulating layer disposed over the substrate in the lateral element region, a semiconductor-over-insulator (SOI) semiconductor layer disposed over the insulating layer in the lateral element region, and lateral element conductive taps located in the semiconductor layer, wherein a lateral Hall element is defined in the lateral element region. Also, the integrated circuit device includes vertical element taps located in the well in the vertical element region, wherein a vertical Hall element is defined in the vertical element region.
    Type: Grant
    Filed: June 20, 2018
    Date of Patent: September 24, 2019
    Assignee: GLOBALFOUNDRIES SINGAPORE PTE. LTD.
    Inventors: Yongshun Sun, Eng Huat Toh
  • Patent number: 10395708
    Abstract: An electronic device may include a semiconductor memory, and the semiconductor memory may include a free layer having a variable magnetization direction; a pinned layer having a fixed magnetization direction; and a tunnel barrier layer interposed between the free layer and the pinned layer, wherein the free layer may include: a first sublayer having a damping constant of 0.1 or less; a second sublayer having a perpendicular magnetic anisotropy energy density ranging from 1.0×104 to 1.0×108 erg/cm3; and an insertion layer interposed between the first sublayer and the second sublayer.
    Type: Grant
    Filed: August 6, 2018
    Date of Patent: August 27, 2019
    Assignee: SK hynix Inc.
    Inventors: Ku-Youl Jung, Jong-Koo Lim, Yang-Kon Kim, Jae-Hyoung Lee
  • Patent number: 10388858
    Abstract: A method including forming a device stack including a dielectric layer between a fixed magnetic layer and a free magnetic layer on a fully-crystalline sacrificial film or substrate including a crystal lattice similar to the crystal lattice of the dielectric material; and transferring the device stack from the sacrificial film to a device substrate. An apparatus including a device stack including a dielectric layer between a fixed magnetic layer and a free magnetic layer on a device substrate wherein the fixed magnetic layer and the free magnetic layer each have a crystalline lattice conforming to a crystalline lattice of the sacrificial film or substrate on which they were formed prior to transfer to the device substrate.
    Type: Grant
    Filed: September 26, 2014
    Date of Patent: August 20, 2019
    Assignee: Intel Corporation
    Inventors: Kevin P. O'Brien, Brian S. Doyle, Kaan Oguz, Robert S. Chau, Satyarth Suri
  • Patent number: 10359269
    Abstract: Aspects include a method of manufacturing a flexible electronic structure that includes a metal or doped silicon substrate. Aspects include depositing an insulating layer on a silicon substrate. Aspects also include patterning a metal on a silicon substrate. Aspects also include selectively masking the structure to expose the metal and a portion of the silicon substrate. Aspects also include depositing a conductive layer including a conductive metal on the structure. Aspects also include plating the conductive material on the structure. Aspects also include spalling the structure.
    Type: Grant
    Filed: March 30, 2017
    Date of Patent: July 23, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Huan Hu, Ning Li, Xiao Hu Liu, Katsuyuki Sakuma
  • Patent number: 10353017
    Abstract: A Hall effect sensor system for detecting magnetic fields includes a Hall effect sensor having a central body with a substantially square shape, a first pair of outwardly oriented and opposing arms projecting outwardly from opposing sides of the central body and a second pair of outwardly oriented and opposing arms projecting outwardly transverse from the first pair of arms to form a cross-shape. Each of the arms has a plurality of fingers projecting outwardly therefrom and electrodes are provided on the fingers. In operation, at least two electrodes on the first pair of opposing arms provide a path for bias current through the Hall effect sensor. An electrode on each of the second pair of opposing arms senses voltage formed in the Hall effect sensor by a magnetic field and provides an output to an amplifier.
    Type: Grant
    Filed: August 13, 2014
    Date of Patent: July 16, 2019
    Assignee: The Timken Company
    Inventor: Lei Wang
  • Patent number: 10330748
    Abstract: A push-pull X-axis magnetoresistive sensor, comprising: a substrate upon which an interlocked array of soft ferromagnetic flux concentrators and a push-pull magnetoresistive sensor bridge unit are placed. It further may comprise calibration coils and/or initialization coils. At least one of each of the soft ferromagnetic flux concentrators is present such that an interlocking structure may be formed such that there are alternately interlocked and non-interlocked gaps along the X direction. Push/pull magnetoresistive sensing unit strings are respectively located in the interlocked and non-interlocked gaps and are electrically connected to form a push-pull magnetoresistive bridge sensing unit. This magnetoresistive sensing unit is sensitive to magnetic field along the X direction.
    Type: Grant
    Filed: June 1, 2016
    Date of Patent: June 25, 2019
    Assignee: MultiDimension Technology Co., Ltd.
    Inventors: James Geza Deak, Zhimin Zhou
  • Patent number: 10333057
    Abstract: A hall element is provided to suppress fluctuation in a Hall output voltage of the hall element which is generated due to a fluctuation in stress. The hall element may be formed to include a substrate, a magnetosensitive portion formed on the substrate, an insulating film formed on the magnetosensitive portion, four conductive portions (electrode portions and contact portions) which are formed on the insulating film, electrically connected to the magnetosensitive portion through the insulating film, and disposed at positions serving as vertexes of a quadrangle, and ball portions electrically connected to the conductive portions, and at least one ball portion is disposed on a diagonal line of the quadrangle formed by a region surrounded by the four conductive portions and above a portion where the conductive portion and the insulating film are in contact with each other.
    Type: Grant
    Filed: March 22, 2018
    Date of Patent: June 25, 2019
    Assignee: Asahi Kasei Microdevices Corporation
    Inventors: Tomoya Shoji, Tsuyoshi Akagi
  • Patent number: 10302461
    Abstract: To provide a rotation detection device that has a miniaturized sensor IC in comparison with a prior art. A rotation detection device includes: a magnet that forms a magnetic field toward a tooth surface of a gear; and a sensor disposed between the magnet and the gear, the sensor including: at least a pair of magnetic detection elements x1 and x2 that outputs signals according to a magnetic flux density in a radial direction of the gear; and a magnetic concentrator that induces, in the radial direction of the gear, a component in a circumferential direction of the gear in the magnetic flux density on detection surfaces of the magnetic detection elements x1 and x2, the sensor detecting a variation in a magnetic flux density accompanying the rotation of the gear.
    Type: Grant
    Filed: February 18, 2016
    Date of Patent: May 28, 2019
    Assignee: MELEXIS TECHNOLOGIES SA
    Inventor: Takumi Yoshiya
  • Patent number: 10263176
    Abstract: A vertical Hall element having an improved sensitivity and reduced offset voltage includes: a second conductivity type semiconductor layer formed on a semiconductor substrate and having an impurity concentration that is distributed uniformly; a second conductivity type impurity diffusion layer formed on the semiconductor layer and having a concentration higher than in the semiconductor layer; a plurality of electrodes formed in a straight line on a surface of the impurity diffusion layer, and each formed from a second conductivity type impurity region that is higher in concentration than the impurity diffusion layer; and a plurality of first conductivity type electrode isolation diffusion layers each formed between two electrodes out of the plurality of electrodes on the surface of the impurity diffusion layer, to isolate the plurality of electrodes from one another.
    Type: Grant
    Filed: November 9, 2017
    Date of Patent: April 16, 2019
    Assignee: ABLIC INC.
    Inventors: Takaaki Hioka, Mika Ebihara
  • Patent number: 10215593
    Abstract: A sensor system for detecting a characteristic of a target object is described. The sensor system can include a sensor, such as a magnetic sensor, configured to sense magnet field components and to generate corresponding magnet field component signals based on the sensed magnet field components. The sensor system can include a processor that is configured to calculate a magnetic field angle based third magnetic field components. For example, the magnetic field angle can be calculated by determining a quadratic sum of a plurality of the magnetic field components. The characteristic of the target object can be determined based on the calculated magnetic field angle.
    Type: Grant
    Filed: March 24, 2016
    Date of Patent: February 26, 2019
    Assignee: Infineon Technologies AG
    Inventors: Tobias Werth, Mario Motz, Gregor Wautischer
  • Patent number: 10186550
    Abstract: A sensor device module comprises: a substrate having a sensor element covered with a protective film, an integrated circuit formed on the substrate, and a bonding pad part formed on the substrate; wherein the integrated circuit and the sensor element are connected at a contact part, and the sensor element and the contact part have a metal thin film layer which consists of first metal layers and second metal layers, an insulating film which is formed on the metal thin film layer and made from the same material as the protective film, and an exfoliation sacrifice layer which is formed on the insulating film and in contact with the protective film, further wherein an upper most film or a lower most film of the exfoliation sacrifice layer is made from the same material as an upper most film of the metal thin film layer.
    Type: Grant
    Filed: May 10, 2017
    Date of Patent: January 22, 2019
    Assignee: Mitsubishi Electric Corporation
    Inventors: Hirobumi Matsui, Yuji Kawano, Shinichi Hosomi
  • Patent number: 10170519
    Abstract: According to one embodiment, a magnetoresistive element includes a first metal layer having a body-centered cubic structure, a second metal layer having a hexagonal close-packed structure on the first metal layer, a metal nitride layer on the second metal layer, a first magnetic layer on the metal nitride layer, an insulating layer on the first magnetic layer, and a second magnetic layer on the insulating layer.
    Type: Grant
    Filed: September 9, 2016
    Date of Patent: January 1, 2019
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Youngmin Eeh, Toshihiko Nagase, Daisuke Watanabe, Koji Ueda, Makoto Nagamine, Kazuya Sawada
  • Patent number: 10109675
    Abstract: A method of forming a semiconductor structure includes forming two or more pillar structures over a top surface of a substrate. The method also includes forming two or more contacts to the two or more pillar structures. The method further includes forming an insulator between the two or more pillar structures and the two or more contacts. The two or more contacts are self-aligned to the two or more pillar structures by forming the insulator via conformal deposition and etching the insulator selective to a spin-on material formed over the insulator between the two or more pillar structures.
    Type: Grant
    Filed: March 8, 2017
    Date of Patent: October 23, 2018
    Assignee: International Business Machines Corporation
    Inventors: Anthony J. Annunziata, Daniel C. Edelstein, Eugene J. O'Sullivan, Henry K. Utomo
  • Patent number: 10103198
    Abstract: A magnetoresistive element according to an embodiment includes: a multilayer structure including a first magnetic layer, a second magnetic layer disposed above the first magnetic layer, and a nonmagnetic layer disposed between the first magnetic layer and the second magnetic layer; a conductor disposed above the second magnetic layer, and including a lower face, an upper face opposing to the lower face, and a side face that is different from the lower face and the upper face, an area of the lower face of the conductor being smaller than an area of the upper face of the conductor, and smaller than an area of an upper face of the second magnetic layer; and a carbon-containing layer disposed on the side face of the conductor.
    Type: Grant
    Filed: March 7, 2016
    Date of Patent: October 16, 2018
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Saori Kashiwada, Yuichi Ohsawa, Daisuke Saida, Chikayoshi Kamata, Kazutaka Ikegami, Megumi Yakabe, Hiroaki Maekawa
  • Patent number: 10103050
    Abstract: Stress compensated systems and methods of compensating for electrical and mechanical stress are discussed. One example system can include a first circuit and a global stress compensation component. The first circuit can be configured to generate a first signal and can comprise at least one local stress compensation component (e.g., employing dynamic element matching, chopping, etc.). The global stress compensation component can comprise one or more stress sensors configured to sense one or more stress components associated with the system. The global stress compensation component can be configured to receive the first signal and to compensate for stress effects on the first signal.
    Type: Grant
    Filed: February 16, 2015
    Date of Patent: October 16, 2018
    Assignee: Infineon Technologies AG
    Inventor: Mario Motz
  • Patent number: 10020278
    Abstract: A semiconductor chip includes a semiconductor body having a bottom side and a top side opposite the bottom side, and passivation arranged on the top side. The semiconductor chip is positioned on the carrier by picking the semiconductor chip and placing the semiconductor chip on the carrier, and pressing the semiconductor chip onto the carrier by a pressing force in a pressing direction, such that the pressing force acts on the semiconductor chip only above one or more continuous chip metallization sections arranged on the top side. Each of the one or more continuous chip metallization sections includes an annularly closed edge section which has a minimum width of more than zero in each direction perpendicular to the pressing direction. The pressing force does not act on the semiconductor chip above any of the edge sections.
    Type: Grant
    Filed: July 22, 2016
    Date of Patent: July 10, 2018
    Assignee: Infineon Technologies AG
    Inventor: Niels Oeschler
  • Patent number: 10002884
    Abstract: To provide a semiconductor device which occupies a small area and is highly integrated. The semiconductor device includes an oxide semiconductor layer, an electrode layer, and a contact plug. The electrode layer includes one end portion in contact with the oxide semiconductor layer and the other end portion facing the one end portion. The other end portion includes a semicircle notch portion when seen from the above. The contact plug is in contact with the semicircle notch portion.
    Type: Grant
    Filed: May 2, 2017
    Date of Patent: June 19, 2018
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Motomu Kurata, Ryota Hodo, Shinya Sasagawa, Yuki Hata