Abstract: MRAM devices with in-situ encapsulation are provided. In one aspect, a method of forming an MRAM device includes: patterning an MRAM stack disposed on a dielectric into individual memory cell stacks, wherein the MRAM stack includes a bottom electrode, a MTJ, and a top electrode, and wherein the patterning is performed using an intermediate angle IBE landing on the dielectric; removing redeposited metal from the memory cell stacks using a high angle IBE; redepositing the dielectric along the sidewalls of the memory cell stacks using a low angle IBE to form a first layer of dielectric encapsulating the memory cell stacks; and depositing a second layer of dielectric, wherein the first/second layers of dielectric form a bilayer dielectric spacer structure, wherein the patterning, removing of the redeposited metal, and redepositing the dielectric steps are all performed in-situ. An MRAM device is also provided.

Abstract: According to one embodiment, a magnetic sensor includes first and second elements, first and second interconnects, a first circuit portion electrically connected to the first and second interconnects and a second circuit portion electrically connected to the first and second elements. The first circuit portion supplies a first alternating current to the first interconnect and supplies a second alternating current to the second interconnect. The second circuit portion supplies a first element current to the first element and supplies a second element current to the second element. At a first time, the first alternating current has a first alternating current orientation, and the second alternating current has a second alternating current orientation. At a second time, the first alternating current has an opposite orientation to the first alternating current orientation, and the second alternating current has an opposite orientation to the second alternating current orientation.

Abstract: The present disclosure, in some embodiments, relates to an integrated chip. The integrated chip includes a magnetoresistive random access memory (MRAM) device surrounded by a dielectric structure disposed over a substrate. The MRAM device includes a magnetic tunnel junction disposed between a bottom electrode and a top electrode. A bottom electrode via couples the bottom electrode to a lower interconnect wire. A top electrode via couples the top electrode to an upper interconnect wire. A bottom surface of the top electrode via has a first width that is smaller than a second width of a bottom surface of the bottom electrode via.

Abstract: Some embodiments relate to a memory device. The memory device includes a first magnetoresistive random-access memory (MRAM) cell disposed on a substrate, and a second MRAM cell disposed on the substrate. An inter-level dielectric (ILD) layer is disposed over the substrate. The ILD layer comprises sidewalls defining a trough between the first and second MRAM cells. A dielectric layer disposed over the ILD layer. The dielectric layer completely fills the trough.

Abstract: A magnetoresistive sensor wafer layout scheme used for a laser writing system and laser scanning method are disclosed. The layout scheme comprises a magnetoresistive multilayer film including an antiferromagnetic pinning layer arranged into a rectangular array of sensor dice on the wafer surface. Pinning layers of magnetoresistive sensing units are magnetically oriented and directionally aligned by the laser writing system. Sensing units are electrically connected into bridge arms electrically connected into a magnetoresistive sensor. Magnetoresistive sensing units in the dice are arranged into at least two spatially-isolated magnetoresistive orientation groups. In the magnetoresistive orientation groups, pinning layers of the sensing units have an angle of magnetic orientation of 0-360 degrees. Angles of magnetic orientation of two adjacent magnetoresistive orientation groups are different.

Abstract: Described is an apparatus which comprises: an input magnet formed of one or more materials with a sufficiently high anisotropy and sufficiently low magnetic saturation to increase injection of spin currents; and a first interface layer coupled to the input magnet, wherein the first interface layer is formed of non-magnetic material such that the first interface layer and the input magnet together have sufficiently matched atomistic crystalline layers.

Abstract: Provided is a semiconductor device according to an embodiment including a first electrode terminal containing copper, a second electrode terminal containing copper, a semiconductor chip provide the first electrode terminal and provided inside the first electrode terminal, a metal member provided on the semiconductor chip, protruding to an outside of the semiconductor chip in at least two directions, electrically connected to the second electrode terminal, and containing copper, and a mold resin surrounding the semiconductor chip.

Abstract: A semiconductor structure is disclosed herein. The semiconductor structure includes two or more pillar structures disposed over a top surface of a substrate. The semiconductor structure further includes two or more contacts to the two or more pillar structures. The semiconductor structure further includes an insulator disposed between the two or more pillar structures and the two or more contacts. The two or more contacts are self-aligned to the two or more pillar structures.

Abstract: Magnetic switching devices, including magnetic memory devices, are provided. The devices use high-quality crystalline films of 4d or 5d transition metal perovskite having a strong spin-orbit coupling (SOC) to produce spin-orbit torque in adjacent ferromagnetic materials via a strong spin-Hall effect. Spin-orbit torque can be generated by the devices with a high efficiency, even at or near room temperature.

Abstract: A stress sensor includes a semiconductor die to which a mechanical stress is applied. The semiconductor die includes at least one bipolar junction transistor; at least one current source configured to inject at least one current through the at least one bipolar junction transistor; and a processing circuit configured to measure a first current gain and a second current gain of the at least one bipolar junction transistor based on the at least one injected current, to determine a first mechanical stress level based on the first current gain, to determine a second mechanical stress level based on the second current gain, and to generate a mechanical stress level signal based on the first mechanical stress level and the second mechanical stress level, wherein the mechanical stress level signal represents the applied mechanical stress, at least a portion of which is applied to the at least one bipolar junction transistor.

Abstract: In a system and method for correcting a stress-impaired signal in a circuit, a calibration circuit produces a first calibrated voltage based on a base-emitter voltage of one or more pnp transistors, a second calibrated voltage based on a base-emitter voltage of one or more npn transistors, and a voltage proportional to absolute temperature. A set of reference values are generated based on these voltages. A gain correction factor is calculated based on a function of the set of reference values and a set of temperature-dependent values, and the stress-impaired signal is corrected based on the gain correction factor.

Abstract: According to one embodiment, a magnetic memory device includes a conductive layer, a first magnetic layer, a second magnetic layer, and a first nonmagnetic layer. The conductive layer includes a first region, a second region, and a third region between the first region and the second region. The second magnetic layer is provided between the third region and the first magnetic layer in a first direction crossing a second direction. The second direction is from the first region toward the second region. The first nonmagnetic layer is provided between the first magnetic layer and the second magnetic layer. The third region includes first and second end portions. The first end portion includes a first protrusion. The second end portion includes a second protrusion. A first position along the second direction of the first protrusion is different from a second position along the second direction of the second protrusion.

Abstract: A hall element is provided to suppress variations in a hall output voltage of the hall element due to a stacked structure of an electrode portion, an insulating film, and a magnetosensitive portion. The hall element may include a substrate, a magnetosensitive portion formed on the substrate, an insulating film formed on the magnetosensitive portion, electrode portions formed on the insulating film, and contact portions electrically connecting the electrode portions and the magnetosensitive portion to each other through the insulating film, in which the entire region surrounded by the contact portions is included in the region of the magnetosensitive portion, and the proportion of regions extending with the corresponding contact portions of the electrode portions as reference points is set to be equal to or less than a predetermined value in a quadrangle formed by the region surrounded by the contact portions.

Abstract: A perpendicular magnetic tunnel junction may include a free layer, a reference layer, and a barrier layer. The barrier layer may be arranged between the free layer and the reference layer. The barrier layer may include a first interface and a second interface. The first interface may face the free layer, and a second interface may face the reference layer. The first interface may not physically correlate with the second interface.

Abstract: Based on a basic idea to effectively utilize a space created in a third wiring layer (M3) by a zero-th wiring layer (M0) which can exist by miniaturization of a FINFET, an auxiliary line AL is arranged in the space created in the third wiring layer, and this auxiliary line AL and a word line WL are electrically connected to each other. Thus, a measure (device) based on such new knowledge that rising time of a word line voltage is largely affected by a wiring resistance of the word line is achieved, a high-speed operation in an SRAM using the FINFET is achieved.

Abstract: Integrated circuit devices including vertical Hall elements and lateral Hall elements and methods for fabricating integrated circuits are provided. In an exemplary embodiment, an integrated circuit device includes a substrate including a lateral element region and a vertical element region. The integrated circuit device includes a well in the lateral element region and in the vertical element region of the substrate. Further, the integrated circuit device includes an insulating layer disposed over the substrate in the lateral element region, a semiconductor-over-insulator (SOI) semiconductor layer disposed over the insulating layer in the lateral element region, and lateral element conductive taps located in the semiconductor layer, wherein a lateral Hall element is defined in the lateral element region. Also, the integrated circuit device includes vertical element taps located in the well in the vertical element region, wherein a vertical Hall element is defined in the vertical element region.

Abstract: An electronic device may include a semiconductor memory, and the semiconductor memory may include a free layer having a variable magnetization direction; a pinned layer having a fixed magnetization direction; and a tunnel barrier layer interposed between the free layer and the pinned layer, wherein the free layer may include: a first sublayer having a damping constant of 0.1 or less; a second sublayer having a perpendicular magnetic anisotropy energy density ranging from 1.0×104 to 1.0×108 erg/cm3; and an insertion layer interposed between the first sublayer and the second sublayer.

Abstract: A method including forming a device stack including a dielectric layer between a fixed magnetic layer and a free magnetic layer on a fully-crystalline sacrificial film or substrate including a crystal lattice similar to the crystal lattice of the dielectric material; and transferring the device stack from the sacrificial film to a device substrate. An apparatus including a device stack including a dielectric layer between a fixed magnetic layer and a free magnetic layer on a device substrate wherein the fixed magnetic layer and the free magnetic layer each have a crystalline lattice conforming to a crystalline lattice of the sacrificial film or substrate on which they were formed prior to transfer to the device substrate.

Abstract: Aspects include a method of manufacturing a flexible electronic structure that includes a metal or doped silicon substrate. Aspects include depositing an insulating layer on a silicon substrate. Aspects also include patterning a metal on a silicon substrate. Aspects also include selectively masking the structure to expose the metal and a portion of the silicon substrate. Aspects also include depositing a conductive layer including a conductive metal on the structure. Aspects also include plating the conductive material on the structure. Aspects also include spalling the structure.

Abstract: A Hall effect sensor system for detecting magnetic fields includes a Hall effect sensor having a central body with a substantially square shape, a first pair of outwardly oriented and opposing arms projecting outwardly from opposing sides of the central body and a second pair of outwardly oriented and opposing arms projecting outwardly transverse from the first pair of arms to form a cross-shape. Each of the arms has a plurality of fingers projecting outwardly therefrom and electrodes are provided on the fingers. In operation, at least two electrodes on the first pair of opposing arms provide a path for bias current through the Hall effect sensor. An electrode on each of the second pair of opposing arms senses voltage formed in the Hall effect sensor by a magnetic field and provides an output to an amplifier.

Abstract: A push-pull X-axis magnetoresistive sensor, comprising: a substrate upon which an interlocked array of soft ferromagnetic flux concentrators and a push-pull magnetoresistive sensor bridge unit are placed. It further may comprise calibration coils and/or initialization coils. At least one of each of the soft ferromagnetic flux concentrators is present such that an interlocking structure may be formed such that there are alternately interlocked and non-interlocked gaps along the X direction. Push/pull magnetoresistive sensing unit strings are respectively located in the interlocked and non-interlocked gaps and are electrically connected to form a push-pull magnetoresistive bridge sensing unit. This magnetoresistive sensing unit is sensitive to magnetic field along the X direction.

Abstract: A hall element is provided to suppress fluctuation in a Hall output voltage of the hall element which is generated due to a fluctuation in stress. The hall element may be formed to include a substrate, a magnetosensitive portion formed on the substrate, an insulating film formed on the magnetosensitive portion, four conductive portions (electrode portions and contact portions) which are formed on the insulating film, electrically connected to the magnetosensitive portion through the insulating film, and disposed at positions serving as vertexes of a quadrangle, and ball portions electrically connected to the conductive portions, and at least one ball portion is disposed on a diagonal line of the quadrangle formed by a region surrounded by the four conductive portions and above a portion where the conductive portion and the insulating film are in contact with each other.

Abstract: To provide a rotation detection device that has a miniaturized sensor IC in comparison with a prior art. A rotation detection device includes: a magnet that forms a magnetic field toward a tooth surface of a gear; and a sensor disposed between the magnet and the gear, the sensor including: at least a pair of magnetic detection elements x1 and x2 that outputs signals according to a magnetic flux density in a radial direction of the gear; and a magnetic concentrator that induces, in the radial direction of the gear, a component in a circumferential direction of the gear in the magnetic flux density on detection surfaces of the magnetic detection elements x1 and x2, the sensor detecting a variation in a magnetic flux density accompanying the rotation of the gear.

Abstract: A vertical Hall element having an improved sensitivity and reduced offset voltage includes: a second conductivity type semiconductor layer formed on a semiconductor substrate and having an impurity concentration that is distributed uniformly; a second conductivity type impurity diffusion layer formed on the semiconductor layer and having a concentration higher than in the semiconductor layer; a plurality of electrodes formed in a straight line on a surface of the impurity diffusion layer, and each formed from a second conductivity type impurity region that is higher in concentration than the impurity diffusion layer; and a plurality of first conductivity type electrode isolation diffusion layers each formed between two electrodes out of the plurality of electrodes on the surface of the impurity diffusion layer, to isolate the plurality of electrodes from one another.

Abstract: A sensor system for detecting a characteristic of a target object is described. The sensor system can include a sensor, such as a magnetic sensor, configured to sense magnet field components and to generate corresponding magnet field component signals based on the sensed magnet field components. The sensor system can include a processor that is configured to calculate a magnetic field angle based third magnetic field components. For example, the magnetic field angle can be calculated by determining a quadratic sum of a plurality of the magnetic field components. The characteristic of the target object can be determined based on the calculated magnetic field angle.

Abstract: A sensor device module comprises: a substrate having a sensor element covered with a protective film, an integrated circuit formed on the substrate, and a bonding pad part formed on the substrate; wherein the integrated circuit and the sensor element are connected at a contact part, and the sensor element and the contact part have a metal thin film layer which consists of first metal layers and second metal layers, an insulating film which is formed on the metal thin film layer and made from the same material as the protective film, and an exfoliation sacrifice layer which is formed on the insulating film and in contact with the protective film, further wherein an upper most film or a lower most film of the exfoliation sacrifice layer is made from the same material as an upper most film of the metal thin film layer.

Abstract: According to one embodiment, a magnetoresistive element includes a first metal layer having a body-centered cubic structure, a second metal layer having a hexagonal close-packed structure on the first metal layer, a metal nitride layer on the second metal layer, a first magnetic layer on the metal nitride layer, an insulating layer on the first magnetic layer, and a second magnetic layer on the insulating layer.

Abstract: A method of forming a semiconductor structure includes forming two or more pillar structures over a top surface of a substrate. The method also includes forming two or more contacts to the two or more pillar structures. The method further includes forming an insulator between the two or more pillar structures and the two or more contacts. The two or more contacts are self-aligned to the two or more pillar structures by forming the insulator via conformal deposition and etching the insulator selective to a spin-on material formed over the insulator between the two or more pillar structures.

Abstract: Stress compensated systems and methods of compensating for electrical and mechanical stress are discussed. One example system can include a first circuit and a global stress compensation component. The first circuit can be configured to generate a first signal and can comprise at least one local stress compensation component (e.g., employing dynamic element matching, chopping, etc.). The global stress compensation component can comprise one or more stress sensors configured to sense one or more stress components associated with the system. The global stress compensation component can be configured to receive the first signal and to compensate for stress effects on the first signal.

Abstract: A magnetoresistive element according to an embodiment includes: a multilayer structure including a first magnetic layer, a second magnetic layer disposed above the first magnetic layer, and a nonmagnetic layer disposed between the first magnetic layer and the second magnetic layer; a conductor disposed above the second magnetic layer, and including a lower face, an upper face opposing to the lower face, and a side face that is different from the lower face and the upper face, an area of the lower face of the conductor being smaller than an area of the upper face of the conductor, and smaller than an area of an upper face of the second magnetic layer; and a carbon-containing layer disposed on the side face of the conductor.

Abstract: A semiconductor chip includes a semiconductor body having a bottom side and a top side opposite the bottom side, and passivation arranged on the top side. The semiconductor chip is positioned on the carrier by picking the semiconductor chip and placing the semiconductor chip on the carrier, and pressing the semiconductor chip onto the carrier by a pressing force in a pressing direction, such that the pressing force acts on the semiconductor chip only above one or more continuous chip metallization sections arranged on the top side. Each of the one or more continuous chip metallization sections includes an annularly closed edge section which has a minimum width of more than zero in each direction perpendicular to the pressing direction. The pressing force does not act on the semiconductor chip above any of the edge sections.

Abstract: To provide a semiconductor device which occupies a small area and is highly integrated. The semiconductor device includes an oxide semiconductor layer, an electrode layer, and a contact plug. The electrode layer includes one end portion in contact with the oxide semiconductor layer and the other end portion facing the one end portion. The other end portion includes a semicircle notch portion when seen from the above. The contact plug is in contact with the semicircle notch portion.

Abstract: A monolithic three-axis linear magnetic sensor and manufacturing method wherein the sensor comprises an X-axis sensor, a Y-axis sensor and a Z-axis sensor. The X-axis sensor comprises a referenced bridge and at least two X ferromagnetic flux guides. The Y-axis sensor comprises a push-pull bridge and at least two Y ferromagnetic flux guides. The Z-axis sensor comprises a push-pull bridge and at least one Z ferromagnetic flux guide. The bridge arms of the referenced bridge and push-pull bridge are each formed by one or more magnetoresistive elements that are electrically interconnected. The directions of the sensing axes and the directions of magnetization of the pinned layers of the magnetoresistive elements are all oriented along the X-axis. This manufacturing method comprises first depositing a magnetoresistive thin film on a wafer, and then performing several processes such as magnetic annealing, photolithography, etching, coating, and the like in order to realize a sensor.

Abstract: A vertical Hall device includes a Hall effect region, a separator, a first plurality of contacts, and a second plurality of contacts. The Hall effect region includes a first straight section, a second straight section that is offset parallel to the first straight section, and a connecting section that connects the first straight section and the second straight section. The separator separates a portion of the first straight section from a portion of the second straight section. The first and second plurality of contacts are arranged in or at the surface of the first and second straight sections, respectively. With respect to a first clock phase of a spinning current scheme, the first plurality of contacts comprises a first supply contact and a first sense contact. The second plurality of contacts comprises a second supply contact and a second sense contact.

Abstract: Embodiments of the present disclosure provide an integrated circuit (IC) structure and methods of electrically connecting multiple IC structures. An IC structure according to embodiments of the present disclosure can include: a first conductive region; a second conductive region laterally separated from the first conductive region; a first vertically-oriented semiconductor fin formed over and contacting the first conductive region; a second vertically-oriented semiconductor fin formed over and contacting the second conductive region; and a first gate contacting each of the first vertically-oriented semiconductor fin and the second conductive region, wherein the first gate includes: a substantially horizontal section contacting the first vertically-oriented semiconductor fin, and a substantially vertical section contacting the second conductive region.

Abstract: A device for monitoring signal levels of signals that are generated, for the purpose of detecting a magnetic field, by a plurality of Hall sensors includes a first, second, and third input and a diagnostic device. The first input is configured to receive a first signal from a first Hall sensor. A first electrical resistor is connected between the first input and a central point. The second input is configured to receive a second signal from a second Hall sensor. A second electrical resistor is connected between the second input and the central point. The third input is configured to receive a third signal from a third Hall sensor. A third electrical resistor is connected between the third input and the central point. The diagnostic device is connected to the central point and is configured to determine a position of the detected magnetic field using an average value.

Abstract: A Hall effect sensor arrangement comprises at least four (2×n) Hall effect components (where n=integer and n?2), wherein the Hall effect components each have two contact terminals C1, C2 and a signal terminal T1-T4, wherein the contact terminals of the at least four Hall effect components are interconnected with one another such that the at least four Hall effect components are arranged together in a parallel-series interconnection, and comprises a control device 150, which is couplable to the signal terminals T1-T4 of the at least four Hall effect components in a plurality of operating phases such that in the different operating phases at least one of the Hall effect components responds to a first magnetic field component B1 in a first detection direction, and at least another of the Hall effect components responds to a second magnetic field component B2 in a second detection direction, wherein the second detection direction is different than the first detection direction.

Abstract: A method of fabricating a semiconductor device having a first region, a second region, and a third region between the first and second regions includes forming first and second preliminary active patterns protruding from a substrate in the first and second regions, respectively, forming mask patterns exposing the third region on the substrate, performing a first etching process using the mask patterns an etch mask to form first and second active patterns, respectively, and forming gate structures on the substrate.

Abstract: Structures include a tunneling device disposed over first and second lattice-mismatched semiconductor materials. Process embodiments include forming tunneling devices over lattice-mismatched materials.

Abstract: A nonvolatile semiconductor memory device according to an embodiment includes: a semiconductor layer; a control gate electrode; and an organic molecular layer, which is provided between the semiconductor layer and the control gate electrode, and has organic molecules including a molecular structure described by a molecular formula (1).

Abstract: A magnetic element is disclosed wherein a composite seed layer such as TaN/Mg enhances perpendicular magnetic anisotropy (PMA) in an overlying magnetic layer that may be a reference layer, free layer, or dipole layer. The first seed layer is selected from one or more of Ta, Zr, Nb, TaN, ZrN, NbN, and Ru. The second seed layer is selected from one or more of Mg, Sr, Ti, Al, V, Hf, B, and Si. A growth promoting layer made of NiCr or an alloy thereof may be inserted between the seed layer and magnetic layer. The magnetic element has thermal stability to at least 400° C.

Abstract: A magnetic memory array and a method for implementing the magnetic memory array for use in Solid-State Drives (SSDs) are provided. A plurality of magnetic pillar memory cells is formed using a deposition and/or growth process to produce a magnetic memory array substantially avoiding milling of magnetic materials.

Abstract: A method for fabricating a semiconductor device includes etching semiconductor substrate to form bulb-type trenches that define a plurality of active regions in the semiconductor substrate; forming a supporter in each of the bulb-type trenches; dividing each active region, of the plurality of active regions, into a pair of body lines by forming a trench through each active region; and forming a bit line in each body line of the pair of body lines.

Abstract: A method of fabricating a semiconductor device having a first region, a second region, and a third region between the first and second regions includes forming first and second preliminary active patterns protruding from a substrate in the first and second regions, respectively, forming mask patterns exposing the third region on the substrate, performing a first etching process using the mask patterns an etch mask to form first and second active patterns, respectively, and forming gate structures on the substrate.

Abstract: An embodiment of the invention includes a memory cell having a magnet layer coupled to a metal layer and read line. The metal layer is also coupled to write and sense lines. During a write operation charge current is supplied to the metal layer via the write line and induces spin current and a magnetic state within the magnet layer based on the spin Hall effect. During a read operation read current is supplied, via the read line, to the magnet layer and then the metal layer and induces another spin current, within the metal layer, that generates an electric field and voltage, based on inverse spin Hall effect, at a sense node coupled to the sense line. The voltage polarity is based on the aforementioned magnetic state. The memory operates with a low supply voltage to drive charge, read, and spin currents. Other embodiments are described herein.

Abstract: Structures include a tunneling device disposed over first and second lattice-mismatched semiconductor materials. Process embodiments include forming tunneling devices over lattice-mismatched materials.

Abstract: Disclosed is a memory circuit and method of forming the same. The memory circuit comprises a lower metallization layer defining first conducting lines. A continuous magnetic storage element stack is atop the lower metallization layer wherein a bottom electrode of the stack is in direct contact with the first conducting lines. An upper metallization layer is atop the continuous magnetic storage element stack, the upper metallization layer defining second conducting lines, which are in direct contact with said continuous magnetic storage element stack. Localized areas of the continuous magnetic storage element stack define discrete magnetic bits, each energizable through a selected pair of the first and second conducting lines. In a second aspect and a third aspect, the continuous magnetic storage element stack is respectively partially and fully etched through a single mask, to define the discrete magnetic bits.

Abstract: An embodiment integrates memory, such as spin-torque transfer magnetoresistive random access memory (STT-MRAM) within a logic chip. The STT-MRAM includes a magnetic tunnel junction (MTJ) with an upper MTJ layer, lower MTJ layer, and tunnel barrier directly contacting the upper MTJ layer and the lower MTJ layer; wherein the upper MTJ layer includes an upper MTJ layer sidewall and the lower MTJ layer includes a lower MTJ sidewall horizontally offset from the upper MTJ layer. Another embodiment includes a memory area, comprising a MTJ, and a logic area located on a substrate; wherein a horizontal plane intersects the MTJ, a first Inter-Layer Dielectric (ILD) material adjacent the MTJ, and a second ILD material included in the logic area, the first and second ILD materials being unequal to one another. In an embodiment the first and second ILDs directly contact one another. Other embodiments are described herein.

Abstract: According to one embodiment, a semiconductor memory device comprises a cell transistor includes a first gate electrode buried in a semiconductor substrate and a first diffusion layer and a second diffusion layer formed to sandwich the first gate electrode, a first lower electrode formed on the first diffusion layer, a magnetoresistive element formed on the first lower electrode to store data according to a change in a magnetization state and connected to a bit line located above, a second lower electrode formed on the second diffusion layer, and a first contact formed on the second lower electrode and connected to a source line located above. A contact area between the second lower electrode and the second diffusion layer is larger than a contact area between the first contact and the second lower electrode.

Abstract: A method for providing a dual magnetic junction usable in a magnetic device and the dual magnetic junction are described. First and second nonmagnetic spacer layers, a free layer and pinned are provided. The first pinned layer, free layer and nonmagnetic spacer layer may be annealed at an anneal temperature of at least three hundred fifty degrees Celsius before a second pinned layer is provided. The second pinned layer may include Co, Fe and Tb. The nonmagnetic spacer layers are between the pinned layers and the free layer. The magnetic junction is configured such that the free layer is switchable between a plurality of stable magnetic states when a write current is passed through the magnetic junction.