With Specific Isolation Means In Integrated Circuit Patents (Class 257/446)
  • Patent number: 10980997
    Abstract: The present invention relates to a photosensitive implant comprising at least one pixel (10) having at least one diode (12, 12?), a stimulating electrode (14), a counter electrode (18), and a resistor (16), wherein the resistance of the resistor (16) is chosen according to a predetermined relation of resistance, a size of the stimulating electrode (14), and a size of the diode (12, 12?). Further, the present invention concerns a method to provide such an implant.
    Type: Grant
    Filed: April 28, 2016
    Date of Patent: April 20, 2021
    Assignee: PIXIUM VISION SA
    Inventor: Martin Deterre
  • Patent number: 10908302
    Abstract: On the front side of an n-type semiconductor substrate, p-type regions are two-dimensionally arranged in an array. A high-concentration n-type region and a p-type region are disposed between the p-type regions adjacent each other. The high-concentration n-type region is formed by diffusing an n-type impurity from the front side of the substrate so as to surround the p-type region as seen from the front side. The p-type region is formed by diffusing a p-type impurity from the front side of the substrate so as to surround the p-type region and high-concentration n-type region as seen from the front side. Formed on the front side of the n-type semiconductor substrate are an electrode electrically connected to the p-type region and an electrode electrically connected to the high-concentration n-type region and the p-type region.
    Type: Grant
    Filed: July 25, 2016
    Date of Patent: February 2, 2021
    Assignee: HAMAMATSU PHOTONICS K.K.
    Inventor: Tatsumi Yamanaka
  • Patent number: 10892298
    Abstract: A light emitting diode display device is provided.
    Type: Grant
    Filed: November 30, 2018
    Date of Patent: January 12, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Tan Sakong, Yong Il Kim, Jong Uk Seo, Ji Hye Yeon
  • Patent number: 10818719
    Abstract: A semiconductor device includes a semiconductor substrate, a radiation-sensing region, at least one isolation structure, and a doped passivation layer. The radiation-sensing region is present in the semiconductor substrate. The isolation structure is present in the semiconductor substrate and adjacent to the radiation-sensing region. The doped passivation layer at least partially surrounds the isolation structure in a substantially conformal manner.
    Type: Grant
    Filed: September 23, 2019
    Date of Patent: October 27, 2020
    Assignee: Taiwan Semicondutor Manufacturing Co., Ltd.
    Inventors: Tsung-Han Tsai, Yun-Wei Cheng, Kuo-Cheng Lee, Chun-Hao Chou, Yung-Lung Hsu
  • Patent number: 10700117
    Abstract: Methods for forming an image sensor structure are provided. The method includes forming a light-sensing region in a substrate and forming a storage node adjacent to light-sensing region in the substrate. The method further includes forming a front side isolation structure partially surrounding an upper portion of the light-sensing region and forming a trench fully surrounding a bottom portion of the light-sensing region to expose a bottom surface of the front side isolations structure. The method further includes forming a backside isolation structure in the trench.
    Type: Grant
    Filed: November 27, 2018
    Date of Patent: June 30, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yuichiro Yamashita, Chun-Hao Chuang, Hirofumi Sumi
  • Patent number: 10658378
    Abstract: Embodiments of interconnect structures of a three-dimensional (3D) memory device and method for forming the interconnect structures are disclosed. In an example, a 3D NAND memory device includes a semiconductor substrate, an alternating layer stack disposed on the semiconductor substrate, and a dielectric structure, which extends vertically through the alternating layer stack, on an isolation region of the substrate. Further, the alternating layer stack abuts a sidewall surface of the dielectric structure and the dielectric structure is formed of a dielectric material. The 3D memory device additionally includes one or more through array contacts that extend vertically through the dielectric structure and the isolation region, and one or more channel structures that extend vertically through the alternating layer stack.
    Type: Grant
    Filed: July 27, 2018
    Date of Patent: May 19, 2020
    Assignee: Yangtze Memory Technologies Co., Ltd.
    Inventors: Qian Tao, Yushi Hu, Zhenyu Lu, Li Hong Xiao, Xiaowang Dai, Yu Ting Zhou, Zhao Hui Tang, Mei Lan Guo, ZhiWu Tang, Qinxiang Wei, Qianbing Xu, Sha Sha Liu, Jian Hua Sun, Enbo Wang
  • Patent number: 10644051
    Abstract: An image sensor includes a substrate including opposite first and second surfaces, first and second gates, on the first surface of the substrate, which each extend in a first direction, a first isolation layer in the substrate between the first and second gates and having a first width in a second direction crossing the first direction, a second isolation layer on the first isolation layer, in the substrate, and having a second width smaller than the first width in the second direction. The second isolation layer is closer to the second surface of the substrate than the first isolation layer. A vertical distance between the first isolation layer and the second isolation layer is ? or less of a height of the first isolation layer.
    Type: Grant
    Filed: March 23, 2018
    Date of Patent: May 5, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Seung Joo Nah, Dong Min Han
  • Patent number: 10613202
    Abstract: A pixel is formed on a semiconductor substrate that includes a photosensitive area having a first doped layer and a charge collection area of a first conductivity type extending through at least part of the first doped layer. At least two charge storage areas, each including a well of the first conductivity type, are separated from the charge collection area at least by a first portion of the first layer. The first portion is covered by a first gate. Each charge storage area is laterally delimited by two insulated conductive electrodes. A second doped layer of the second conductivity type covers the charge collection area and the charge storage areas.
    Type: Grant
    Filed: November 19, 2018
    Date of Patent: April 7, 2020
    Assignee: STMicroelectronics (Crolles 2) SAS
    Inventors: Francois Roy, Boris Rodrigues Goncalves, Marie Guillon, Yvon Cazaux, Benoit Giffard
  • Patent number: 10504953
    Abstract: The present technology relates to a solid-state imaging device, manufacturing method of a solid-state imaging device, and an electronic device, which can provide a solid-state imaging device having further improved features such as reduced optical color mixing and the like. Also, an electronic device using the solid-state imaging device thereof is provided. According to a solid-state imaging device having a substrate and multiple photoelectric converters that are formed on the substrate, an insulating film forms an embedded element separating unit. The element separating unit is configured of an insulating film having a fixed charge that is formed so as to coat the inner wall face of a groove portion, within the groove portion which is formed in the depth direction from the light input side of the substrate.
    Type: Grant
    Filed: March 7, 2019
    Date of Patent: December 10, 2019
    Assignee: Sony Corporation
    Inventors: Takeshi Yanagita, Itaru Oshiyama, Takayuki Enomoto, Harumi Ikeda, Shinichiro Izawa, Atsuhiko Yamamoto, Kazunobu Ota
  • Patent number: 10418404
    Abstract: The present technology relates to a solid-state imaging device, manufacturing method of a solid-state imaging device, and an electronic device, which can provide a solid-state imaging device having further improved features such as reduced optical color mixing and the like. Also, an electronic device using the solid-state imaging device thereof is provided. According to a solid-state imaging device having a substrate and multiple photoelectric converters that are formed on the substrate, an insulating film forms an embedded element separating unit. The element separating unit is configured of an insulating film having a fixed charge that is formed so as to coat the inner wall face of a groove portion, within the groove portion which is formed in the depth direction from the light input side of the substrate.
    Type: Grant
    Filed: September 13, 2018
    Date of Patent: September 17, 2019
    Assignee: Sony Corporation
    Inventors: Takeshi Yanagita, Itaru Oshiyama, Takayuki Enomoto, Harumi Ikeda, Shinichiro Izawa, Atsuhiko Yamamoto, Kazunobu Ota
  • Patent number: 10325949
    Abstract: An image sensor device is provided. The image sensor device includes a substrate having a first surface, a second surface, and a light-sensing region. The image sensor device includes a first isolation structure in the substrate and adjacent to the first surface. The first isolation structure surrounds the light-sensing region. The image sensor device includes a second isolation structure passing through the first isolation structure and the substrate under the first isolation structure. The second isolation structure surrounds the light-sensing region and a portion of the first isolation structure.
    Type: Grant
    Filed: August 6, 2018
    Date of Patent: June 18, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD
    Inventors: Chao-Ching Chang, Sheng-Chan Li, Cheng-Hsien Chou, Tsung-Wei Huang, Min-Hui Lin, Yi-Ming Lin
  • Patent number: 10192924
    Abstract: An image pickup device according to the present disclosure includes a first pixel and a second pixel each including a photodetection section and a light condensing section, the photodetection section including a photoelectric conversion element, the light condensing section condensing incident light toward the photodetection section, the first pixel and the second pixel being adjacent to each other and each having a step part on a photodetection surface of the photodetection section, in which at least a part of a wall surface of the step part is covered with a first light shielding section.
    Type: Grant
    Filed: May 30, 2018
    Date of Patent: January 29, 2019
    Assignee: Sony Corporation
    Inventors: Takeshi Yanagita, Suguru Saito, Kaoru Koike
  • Patent number: 10177187
    Abstract: An image sensor is disclosed. The image sensor includes an epitaxial layer, a plurality of plug structures and an interconnect structure. Wherein the plurality of plug structures are formed in the epitaxial layer, and each plug structure has doped sidewalls, the epitaxial layer and the doped sidewalls form a plurality of photodiodes, the plurality of plug structures are used to separate adjacent photodiodes, and the epitaxial layer and the doped sidewalls are coupled to the interconnect structure via the plug structures. An associated method of fabricating the image sensor is also disclosed. The method includes: providing a substrate having a first-type doped epitaxial substrate layer on a second-type doped epitaxial substrate layer; forming a plurality of isolation trenches in the first-type doped epitaxial substrate layer; forming a second-type doped region along sidewalls and bottoms of the plurality of isolation trenches; and filling the plurality of isolation trenches by depositing metal.
    Type: Grant
    Filed: May 28, 2015
    Date of Patent: January 8, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Alexander Kalnitsky, Jhy-Jyi Sze, Dun-Nian Yaung, Chen-Jong Wang, Yimin Huang, Yuichiro Yamashita
  • Patent number: 10128291
    Abstract: The present technology relates to a solid-state imaging device, manufacturing method of a solid-state imaging device, and an electronic device, which can provide a solid-state imaging device having further improved features such as reduced optical color mixing and the like. Also, an electronic device using the solid-state imaging device thereof is provided. According to a solid-state imaging device having a substrate and multiple photoelectric converters that are formed on the substrate, an insulating film forms an embedded element separating unit. The element separating unit is configured of an insulating film having a fixed charge that is formed so as to coat the inner wall face of a groove portion, within the groove portion which is formed in the depth direction from the light input side of the substrate.
    Type: Grant
    Filed: May 31, 2017
    Date of Patent: November 13, 2018
    Assignee: Sony Corporation
    Inventors: Takeshi Yanagita, Itaru Oshiyama, Takayuki Enomoto, Harumi Ikeda, Shinichiro Izawa, Atsuhiko Yamamoto, Kazunobu Ota
  • Patent number: 10096638
    Abstract: The present technology relates to a solid-state imaging device, manufacturing method of a solid-state imaging device, and an electronic device, which can provide a solid-state imaging device having further improved features such as reduced optical color mixing and the like. Also, an electronic device using the solid-state imaging device thereof is provided. According to a solid-state imaging device having a substrate and multiple photoelectric converters that are formed on the substrate, an insulating film forms an embedded element separating unit. The element separating unit is configured of an insulating film having a fixed charge that is formed so as to coat the inner wall face of a groove portion, within the groove portion which is formed in the depth direction from the light input side of the substrate.
    Type: Grant
    Filed: May 31, 2017
    Date of Patent: October 9, 2018
    Assignee: Sony Corporation
    Inventors: Takeshi Yanagita, Itaru Oshiyama, Takayuki Enomoto, Harumi Ikeda, Shinichiro Izawa, Atsuhiko Yamamoto, Kazunobu Ota
  • Patent number: 10083963
    Abstract: An integrated circuit device may include a p-type metal oxide semiconductor (PMOS) transistor supported by a backside of an isolation layer. The integrated circuit device may also include an n-type metal oxide semiconductor (NMOS) transistor supported by a front-side of the isolation layer, opposite the backside. The integrated circuit device may further include a shared contact extending through the isolation layer and electrically coupling a first terminal of the PMOS transistor to the first terminal of the NMOS transistor.
    Type: Grant
    Filed: December 21, 2016
    Date of Patent: September 25, 2018
    Assignee: QUALCOMM Incorporated
    Inventors: Sinan Goktepeli, Jean Richaud
  • Patent number: 10026774
    Abstract: A method of manufacturing a solid-state image sensor including preparing a wafer including a pixel region where a photoelectric conversion element is provided, a peripheral circuit region where a gate electrode of a peripheral MOS transistor for constituting a peripheral circuit is provided, and a scribe region. The method includes forming an insulating film covering the pixel region, the peripheral circuit region, and the scribe region, and forming a sidewall spacer on a side surface of the gate electrode by etching the insulating film so that portions of the insulating film remains to cover the pixel region and the scribe region, and forming a metal silicide layer in the peripheral circuit region by using, as a mask for protection from silicidation, the insulating film covering the pixel region and the scribe region.
    Type: Grant
    Filed: May 27, 2015
    Date of Patent: July 17, 2018
    Assignee: CANON KABUSHIKI KAISHA
    Inventors: Yusuke Onuki, Masatsugu Itahashi, Nobuaki Kakinuma, Mineo Shimotsusa, Masato Fujita, Takumi Ogino, Keita Torii
  • Patent number: 9986192
    Abstract: An image sensor includes a semiconductor material including a photodiode disposed in the semiconductor material and an insulating material. A surface of the semiconductor material is disposed between the insulating material and the photodiode. The image sensor also includes isolation structures disposed in the semiconductor material and in the insulating material, and the isolation structures extend from within the semiconductor material through the surface and into the insulating material. The isolation structures include a core material and a liner material. The liner material is disposed between the core material and the semiconductor material, and is also disposed between the insulating material and the core material.
    Type: Grant
    Filed: November 28, 2016
    Date of Patent: May 29, 2018
    Assignee: OmniVision Technologies, Inc.
    Inventors: Dyson H. Tai, Duli Mao, Vincent Venezia, Gang Chen, Chih-Wei Hsiung
  • Patent number: 9929291
    Abstract: A photo-detector having a photonic crystal structure for absorbing photons passing perpendicular to a surface of the photo-detector and a plasmonic resonance structure for absorbing photons passing along the surface of the photo-detector.
    Type: Grant
    Filed: February 6, 2014
    Date of Patent: March 27, 2018
    Assignee: RAYTHEON COMPANY
    Inventors: Edward P. Smith, Anne Itsuno, Justin Gordon Adams Wehner
  • Patent number: 9887235
    Abstract: Backside illuminated (BSI) image sensor devices are described as having pixel isolation structures formed on a sacrificial substrate. A photolayer is epitaxially grown over the pixel isolation structures. Radiation-detecting regions are formed in the photolayer adjacent to the pixel isolation structures. The pixel isolation structures include a dielectric material. The radiation-detecting regions include photodiodes. A backside surface of the BSI image sensor device is produced by planarized removal of the sacrificial substrate to physically expose the pixel isolation structures or at least optically expose the photolayer.
    Type: Grant
    Filed: December 11, 2015
    Date of Patent: February 6, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yu-Hung Cheng, Tung-I Lin, Wei-Li Chen, Yeur-Luen Tu
  • Patent number: 9825147
    Abstract: A method of forming a HVMOS transistor device is provided. A substrate is provided. A first insulation structure and a trench are formed in the substrate. A base region having a second conductivity type is formed, wherein the base region completely encompasses the trench. Next, a gate dielectric layer and a gate structure are formed in the trench and covering a portion of the first insulation structure. Then, a drain region and a source region are formed in the substrate at two respective sides of the gate structure, and the drain region and the source region comprise a first conductivity type complementary to the second conductivity type. A channel is defined between the source region and the drain region along a first direction.
    Type: Grant
    Filed: August 9, 2016
    Date of Patent: November 21, 2017
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventor: Ming-Shun Hsu
  • Patent number: 9799691
    Abstract: Channel stop sections formed by multiple times of impurity ion implanting processes. Four-layer impurity regions are formed across the depth of a semiconductor substrate (across the depth of the bulk), so that a P-type impurity region is formed deep in the semiconductor substrate; thus, incorrect movement of electric charges is prevented. Other four-layer impurity regions of another channel stop section are decreased in width step by step across the depth of the substrate, so that the reduction of a charge storage region of a light receiving section due to the dispersion of P-type impurity in the channel stop section is prevented in the depth of the substrate.
    Type: Grant
    Filed: October 18, 2016
    Date of Patent: October 24, 2017
    Assignee: Sony Corporation
    Inventor: Kiyoshi Hirata
  • Patent number: 9711550
    Abstract: A method of manufacturing a pinned photodiode, including: forming a region of photon conversion into electric charges of a first conductivity type on a substrate of the second conductivity type; coating said region with a layer of a heavily-doped insulator of the second conductivity type; and annealing to ensure a dopant diffusion from the heavily-doped insulator layer.
    Type: Grant
    Filed: August 31, 2015
    Date of Patent: July 18, 2017
    Assignees: STMicroelectronics SA, STMicroelectronics (Crolles 2) SAS
    Inventors: Laurent Favennec, Didier Dutartre, Francois Roy
  • Patent number: 9490126
    Abstract: An electronic structure includes a resistive memory device, and a P-I-N diode in operative association with the resistive memory device. A plurality of such electronic structures are used in a resistive memory array, with the P-I-N diodes functioning as select devices in the array. Methods are provided for fabricating such resistive memory deviceā€”P-I-N diode structures.
    Type: Grant
    Filed: June 21, 2011
    Date of Patent: November 8, 2016
    Assignee: Cypress Semiconductor Corporation
    Inventors: Seungmoo Choi, Sameer Haddad
  • Patent number: 9397130
    Abstract: A semiconductor device includes a substrate, a semiconductor layer, light-sensing devices, a transparent dielectric layer and a grid shielding layer. The semiconductor layer overlies the substrate, and has a first surface and a second surface opposite to the first surface. The semiconductor layer includes microstructures disposed on the second surface of the semiconductor layer. The light-sensing devices are disposed on the first surface of the semiconductor layer. The transparent dielectric layer is disposed on the second surface of the semiconductor layer, and covers the microstructures. The grid shielding layer extends from the first surface of the semiconductor layer toward the second surface of the semiconductor layer, and surrounds each of the light-sensing devices to separate the light-sensing devices from each other, in which a depth of the grid shielding layer is greater than two-thirds of a thickness of the semiconductor layer.
    Type: Grant
    Filed: December 26, 2014
    Date of Patent: July 19, 2016
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chien-Chang Huang, Hsing-Chih Lin, Chien-Nan Tu, Yu-Lung Yeh
  • Patent number: 9318523
    Abstract: A solid-state imaging device that includes a pixel including a photoelectric conversion section, and a conversion section that converts an electric charge generated by photoelectric conversion into a pixel signal. In the solid-state imaging device, substantially only a gate insulation film is formed on a substrate corresponding to an area under a gate electrode of at least one transistor in the pixel.
    Type: Grant
    Filed: July 11, 2013
    Date of Patent: April 19, 2016
    Assignee: SONY CORPORATION
    Inventor: Kazuichiro Itonaga
  • Patent number: 9293486
    Abstract: An image capturing device includes an intermediate region located between a pixel circuit region and a peripheral circuit region and forming a boundary with the pixel circuit region and the peripheral circuit region. The pixel circuit region, the peripheral circuit region, and the intermediate region are provided with a semiconductor layer, a first wiring layer on the semiconductor layer, and a second wiring layer located away from the semiconductor layer relative to the first wiring layer. Pixel circuits and a peripheral circuit are connected via one of at least the first wiring layer and the second wiring layer in the intermediate region. The area occupancy of the one wiring layer in the intermediate region relative to a total area thereof is between 0.5 times and 1.5 times the area occupancy of the one wiring layer in the pixel circuit region relative to a total area thereof.
    Type: Grant
    Filed: October 6, 2014
    Date of Patent: March 22, 2016
    Assignee: CANON KABUSHIKI KAISHA
    Inventors: Aiko Kato, Shingo Kitamura, Takehiro Toyoda, Hiroaki Naruse
  • Patent number: 9293494
    Abstract: An image sensor includes a substrate including a pixel region and a peripheral circuit region, and a first device isolation layer disposed in the substrate to define a plurality of unit pixels that are adjacent to each other in a first direction in the pixel region. Each of the plurality of unit pixels includes at least one light sensing element disposed in the substrate. The image sensor includes an interlayer insulating structure on the substrate, and a first blocking structure disposed on the first device isolation layer and penetrating the interlayer insulating structure. The first blocking structure is disposed between the plurality of unit pixels when viewed from a plan view. The first blocking structure extends in a second direction intersecting the first direction when viewed from a plan view.
    Type: Grant
    Filed: April 1, 2015
    Date of Patent: March 22, 2016
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jungchak Ahn, Youngsun Oh, Kyungho Lee, Dongyoung Jang
  • Patent number: 9287308
    Abstract: An image sensor pixel includes one or more photodiodes disposed in a semiconductor layer. Pixel circuitry is disposed in the semiconductor layer coupled to the one or more photodiodes. A passivation layer is disposed proximate to the semiconductor layer over the pixel circuitry and the one or more photodiodes. A contact etch stop layer is disposed over the passivation layer. One or more metal contacts are coupled to the pixel circuitry through the contact etch stop layer. One or more isolation regions are defined in the contact etch stop layer that isolate contact etch stop layer material through which the one or more metal contacts are coupled are coupled to the pixel circuitry from the one or more photodiodes.
    Type: Grant
    Filed: April 8, 2013
    Date of Patent: March 15, 2016
    Assignee: OmniVision Technologies, Inc.
    Inventors: Sing-Chung Hu, Dajiang Yang, Oray Orkun Cellek, Hsin-Chih Tai, Gang Chen
  • Patent number: 9231145
    Abstract: A solar cell includes polysilicon P-type and N-type doped regions on a backside of a substrate, such as a silicon wafer. A trench structure separates the P-type doped region from the N-type doped region. Each of the P-type and N-type doped regions may be formed over a thin dielectric layer. The trench structure may include a textured surface for increased solar radiation collection. Among other advantages, the resulting structure increases efficiency by providing isolation between adjacent P-type and N-type doped regions, thereby preventing recombination in a space charge region where the doped regions would have touched.
    Type: Grant
    Filed: February 3, 2015
    Date of Patent: January 5, 2016
    Assignee: SunPower Corporation
    Inventor: David D. Smith
  • Patent number: 9202830
    Abstract: An imaging element includes an amplifying transistor. A signal charge from the photodiode is transferable to the gate of amplifying transistor, the photodiode being within a semiconductor substrate. The source and drain of the amplifying transistor are electrically isolated from a semiconductor substrate, wherein the source is within a well or the source and drain are within a silicon-on-insulator layer.
    Type: Grant
    Filed: November 12, 2010
    Date of Patent: December 1, 2015
    Assignee: Sony Corporation
    Inventors: Toshiyuki Nishihara, Hirofumi Sumi
  • Patent number: 9190441
    Abstract: Provided is a semiconductor image sensor device. The image sensor device includes a substrate. The image sensor device includes a first pixel and a second pixel disposed in the substrate. The first and second pixels are neighboring pixels. The image sensor device includes an isolation structure disposed in the substrate and between the first and second pixels. The image sensor device includes a doped isolation device disposed in the substrate and between the first and second pixels. The doped isolation device surrounds the isolation structure in a conformal manner.
    Type: Grant
    Filed: October 7, 2014
    Date of Patent: November 17, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Yu Lai, Yeur-Luen Tu, Chih-Hui Huang, Cheng-Ta Wu, Chia-Shiung Tsai, Luan C. Tran
  • Patent number: 9165966
    Abstract: CMOS image sensors are provided. A CMOS image sensor may include a semiconductor substrate including a light-receiving region and a logic region adjacent the light-receiving region. The CMOS image sensor may include a photoelectric conversion region in the light-receiving region. Moreover, the CMOS image sensor may include an isolation region including an interface with a sidewall of the photoelectric conversion region. The isolation region may include a first refractive index that is smaller than a second refractive index of the semiconductor substrate, and the isolation region may be between the logic region and the sidewall of the photoelectric conversion region.
    Type: Grant
    Filed: May 2, 2014
    Date of Patent: October 20, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jae Sung Shin, Minseok Oh, Sungsoo Choi, Hyoungsoo Ko, Taechan Kim
  • Patent number: 9111833
    Abstract: According to one embodiment, a method of manufacturing a solid-state imaging device includes a trench forming process, a concave portion forming process, a coating process, and a burying process. In the trench forming process, a trench is formed at the position to isolate a plurality of photoelectric conversion elements. In the concave portion forming process, a concave portion is formed at the position to form a light shielding film of shielding at least part of subject light incident on an adjustment photoelectric conversion element used for an image quality adjustment of an imaged image. In the coating process, inner circumferential surfaces of the trench and the concave portion are coated with an insulating film. In the burying process, a light shielding member is buried inside the trench and the concave portion whose inner circumferential surface are coated with the insulating film.
    Type: Grant
    Filed: April 22, 2013
    Date of Patent: August 18, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yosuke Kitamura, Hisashi Aikawa, Kazunori Kakehi
  • Publication number: 20150145092
    Abstract: A semiconductor device includes a semiconductor substrate, a photoelectric conversion element, a first isolation insulating film, and a current blocking region. The first isolation insulating film is formed around the photoelectric conversion element. The current blocking region is formed in a region between the photoelectric conversion element and the first isolation insulating film. The current blocking region includes an impurity diffusion layer, and a defect extension preventing layer disposed in contact with the impurity diffusion layer to form a twin with the impurity diffusion layer. The defect extension preventing layer has a different crystal structure from that of the impurity diffusion layer. At least a part of the current blocking region is disposed in contact with the first isolation insulating film.
    Type: Application
    Filed: November 25, 2014
    Publication date: May 28, 2015
    Inventor: Keiichi ITAGAKI
  • Patent number: 9040891
    Abstract: A method of forming of an image sensor device includes a substrate having a pixel region and a periphery region. A plurality of first trenches is etched in the periphery region. Each of the first trenches has a depth D1. A mask layer is formed over the substrate. The mask layer has a plurality of openings in the pixel region. A spacer is formed in an interior surface of each opening. A plurality of second trenches is etched through each opening having the spacer in the pixel region. Each of the second trenches has a depth D2. The depth D1 is larger than the depth D2.
    Type: Grant
    Filed: June 8, 2012
    Date of Patent: May 26, 2015
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: U-Ting Chen, Dun-Nian Yaung, Jen-Cheng Liu, Yu-Hao Shih, Chih-Chien Wang, Shih Pei Chou, Wei-Tung Huang, Cheng-Ta Wu
  • Patent number: 9025063
    Abstract: A unit pixel of an image sensor is provided. The unit pixel includes a photoelectric conversion element configured to generate photocharge varying with the intensity of incident light, a transfer transistor configured to transfer the photocharge to a floating diffusion in response to a transfer control signal, and a supplemental transistor connected to the floating diffusion. Because the unit pixel includes only one transistor in addition to the transfer transistor, the area of the unit pixel is minimized, and, as a result, the resolution of a pixel array is increased and the power consumption of the pixel array is decreased.
    Type: Grant
    Filed: February 27, 2013
    Date of Patent: May 5, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jung Chak Ahn, Hisanori Ihara
  • Publication number: 20150115388
    Abstract: A solid-state imaging device includes a plurality of photoelectric transducers disposed in an array in a semiconductor layer. Each photoelectric transducer includes a first semiconductor region of a first conductivity type and a second semiconductor region of a second conductivity type. The first and second regions are in direct contact. An isolation region is between each adjacent pair of photoelectric transducers. The isolation region includes an insulating material extending from a surface of the semiconductor layer and a third semiconductor region of the first conductivity type surrounding the insulating material. The third semiconductor region is between the insulating material and the first semiconductor region, and the first semiconductor region is between the second and third semiconductor regions.
    Type: Application
    Filed: October 24, 2014
    Publication date: April 30, 2015
    Inventors: Kentaro EDA, Kenichi YOSHINO, Shintaro OKUJO, Hiroyuki FUKUMIZU, Takaaki MINAMI, Takeshi YOUSYOU, Hiroaki ASHIDATE
  • Publication number: 20150102443
    Abstract: An infrared sensor device includes at least one sensor element formed in a semiconductor substrate, an SOI wafer that defines a gap below and around the sensor element, and a suspension device that is configured to suspend the sensor element in the SOI wafer. The sensor element is substantially arranged below the suspension device, thereby achieving a high sensitivity, low thermal capacity, low thermal coupling to the substrate and a high image refresh rate.
    Type: Application
    Filed: April 12, 2013
    Publication date: April 16, 2015
    Inventors: Ingo Herrmann, Christoph Schelling
  • Publication number: 20150102448
    Abstract: Provided is an image pickup device, including: a first trench provided between a plurality of pixels in a light-receiving region of a semiconductor substrate, the semiconductor substrate including the light-receiving region and a peripheral region, the light-receiving region being provided with the plurality of pixels each including a photoelectric conversion section; and a second trench provided in the peripheral region of the semiconductor substrate, wherein the semiconductor substrate has a variation in thickness between a portion where the first trench is provided and a portion where the second trench is provided.
    Type: Application
    Filed: October 6, 2014
    Publication date: April 16, 2015
    Inventor: Shinya Sato
  • Patent number: 9006846
    Abstract: This document refers to apparatus and methods for a device layer of a microelectromechanical system (MEMS) sensor having vias with reduced shunt capacitance. In an example, a device layer can include a substrate having a pair of trenches separated in a horizontal direction by a portion of the substrate, wherein each trench of the pair of trenches includes first and second vertical layers including dielectric, the first and second vertical layers separated by a third vertical layer including polysilicon.
    Type: Grant
    Filed: September 20, 2011
    Date of Patent: April 14, 2015
    Assignee: Fairchild Semiconductor Corporation
    Inventors: Janusz Bryzek, John Gardner Bloomsburgh, Cenk Acar
  • Publication number: 20150091122
    Abstract: Systems and methods for providing a solid state image sensor (30) are provided. More particularly, an image sensor (30) that suppresses color mixing is provided. Moreover, embodiments of the present disclosure provide for the creation of light blocking features (32) that avoid the creation of stress concentrations. More particularly, embodiments of the present disclosure provide for the creation of light blocking structures (32) using trenches formed in a substrate (44) that are arranged such that no two trenches intersect one another.
    Type: Application
    Filed: May 16, 2013
    Publication date: April 2, 2015
    Inventors: Hiromi Okazaki, Masayuki Uchiyama, Kazufumi Watanabe
  • Patent number: 8987841
    Abstract: A CMOS (Complementary Metal Oxide Semiconductor) pixel for sensing at least one selected from a biological, chemical, ionic, electrical, mechanical and magnetic stimulus. The CMOS pixel includes a substrate including a backside, a source coupled with the substrate to generate a background current, and a detection element electrically coupled to measure the background current. The stimulus, which is to be provided to the backside, affects a measurable change in the background current.
    Type: Grant
    Filed: March 11, 2014
    Date of Patent: March 24, 2015
    Assignee: OmniVision Technologies, Inc.
    Inventors: Manoj Bikumandla, Dominic Massetti
  • Publication number: 20150076648
    Abstract: Systems and methods are provided for fabricating a backside illuminated image sensor including an array of pixels. An example image sensor includes a first pixel, a second pixel, and an isolation structure. The first pixel is disposed in a front side of a substrate and is configured to generate charged carriers in response to light incident upon a backside of the substrate. The second pixel is disposed in the front side of the substrate and is configured to generate charged carriers in response to light incident upon the backside of the substrate. The isolation structure is disposed to separate the second pixel from the first pixel, and extends from the backside of the substrate toward the front side of the substrate. The isolation structure includes a sidewall substantially vertically to the front side of the substrate.
    Type: Application
    Filed: September 18, 2013
    Publication date: March 19, 2015
    Inventor: SHIH-I YANG
  • Publication number: 20150076572
    Abstract: A semiconductor device includes a semiconductor substrate, a plurality of photoelectric conversion elements arranged on the semiconductor substrate to collectively form an image sensor, a plurality of trenches each formed between the photoelectric conversion elements adjacent to each other, and a plurality of impurity diffusion layers each provided at a bottom of the trench at a position deeper than a p-n junction of the photoelectric conversion element.
    Type: Application
    Filed: September 10, 2014
    Publication date: March 19, 2015
    Applicant: RICOH COMPANY, LTD.
    Inventors: Katsuyuki Sakurano, Hirobumi Watanabe, Takaaki Negoro, Katsuhiko Aisu, Kazuhiro Yoneda
  • Publication number: 20150076649
    Abstract: An electronic device may include a first semiconductor layer, a first electrode layer on the semiconductor layer, an adhesive insulating layer on the first electrode layer, a second electrode layer on the adhesive insulating layer, a second semiconductor layer. The first electrode layer may include a first plurality of electrodes, the first electrode layer may be between the adhesive insulating layer and the first semiconductor layer, and the adhesive insulating layer may include at least one of SiOCN, SiBN, and/or BN. The second electrode layer may include a second plurality of electrodes, the adhesive insulating layer may be between the first and second electrode layers, and the second electrode layer may be between the adhesive insulating layer and the second semiconductor layer.
    Type: Application
    Filed: September 15, 2014
    Publication date: March 19, 2015
    Inventors: Sung-kwan KIM, Doo-Won Kwon, Jeong-ki Kim, Wook-hwan Kim, Byung-jun Park, Seung-hun Shin, June-taeg Lee, Ha-kyu Choi, Tae-Seok Oh
  • Patent number: 8981438
    Abstract: A photoelectric conversion apparatus includes: a first semiconductor region forming a part of a photoelectric conversion element; a second semiconductor region stacked on the first semiconductor region, and forming a part of the photoelectric conversion element; a third semiconductor region to which a signal charge transferred from the photoelectric conversion element; a fourth semiconductor region of the first conductivity type having an higher impurity concentration, between the first and third semiconductor region and between the second and third semiconductor regions, closer to a main surface than the first semiconductor region, and connected to the first semiconductor region; a first gate electrode over the fourth semiconductor region, an insulating film on the main surface and between the first gate electrode and the fourth semiconductor region; and a second gate electrode between the third and fourth semiconductor regions, and over the insulating film.
    Type: Grant
    Filed: March 7, 2013
    Date of Patent: March 17, 2015
    Assignee: Canon Kabushiki Kaisha
    Inventor: Yuichiro Yamashita
  • Patent number: 8963280
    Abstract: Semiconductor devices with reduced substrate defects and methods of manufacture are disclosed. The method includes forming a dielectric material on a substrate. The method further includes forming a shallow trench structure and deep trench structure within the dielectric material. The method further includes forming a material within the shallow trench structure and deep trench structure. The method further includes forming active areas of the material separated by shallow trench isolation structures. The shallow trench isolation structures are formed by: removing the material from within the deep trench structure and portions of the shallow trench structure to form trenches; and depositing an insulator material within the trenches.
    Type: Grant
    Filed: September 11, 2013
    Date of Patent: February 24, 2015
    Assignee: International Business Machines Corporation
    Inventor: Effendi Leobandung
  • Patent number: 8957488
    Abstract: A system and method for fabricating a self-powering integrated circuit chip having an integrated circuit, which may be a MEMS or CMOS device or the like and a thin film photovoltaic cell stack overlayed thereupon or on the opposite side of the substrate on which the IC is manufactured upon.
    Type: Grant
    Filed: March 22, 2011
    Date of Patent: February 17, 2015
    Assignee: Sol Chip Ltd.
    Inventors: Shani Keysar, Ofer Navon
  • Publication number: 20150041945
    Abstract: A device includes a device isolation region formed into a semiconductor substrate, a doped pickup region formed into the device isolation region, a dummy gate structure that includes at least one structure that partially surrounds the doped pickup region, and a via connected to the doped pickup region.
    Type: Application
    Filed: October 22, 2014
    Publication date: February 12, 2015
    Inventors: Min-Feng Kao, Dun-Nian Yaung, Jen-Cheng Liu, Tzu-Hsuan Hsu, Szu-Ying Chen, Wei-Cheng Hsu, Hsiao-Hui Tseng