Abstract: A method is disclosed, including positioning a lead wire of a gate chip at a distance of less than 10 nm from a semiconductor heterostructure. The heterostructure includes a surface layer and a subsurface layer. The method also includes inducing an electrostatic potential in the subsurface layer by applying a voltage to the lead wire. The method also includes loading a charge carrier into the subsurface layer. The method also includes detecting the charge carrier in the subsurface layer of the semiconductor heterostructure by emitting a radio-frequency pulse using a resonator coupled to the at least one lead wire of the gate chip, detecting a reflected pulse of the emitted radio-frequency pulse, and determining a phase shift of the reflected pulse relative to the emitted radio-frequency pulse. The method also includes characterizing the quantum dot by measuring valley splitting of the quantum dot.

Abstract: A method of eliminating interconnect strains in a stack-up is provided. The method includes providing a detector portion including a detector substrate and detector layers, providing a read-out integrated circuit (ROIC) stack-up including ROIC layers and an initial ROIC substrate, removing the initial ROIC substrate from the ROIC layers, attaching a new ROIC substrate to a first surface of the ROIC layers, the new ROIC substrate having a coefficient of thermal expansion (CTE) that matches a CTE of the detector substrate and hybridizing the detector layers to a second surface of the ROIC layers by way of interconnects.

Abstract: A method includes forming a plurality of identical arrays on a semiconductor wafer, each array having a plurality of detectors, screening each of the plurality of arrays to determine an operational status of each of the plurality of arrays, and selecting one of the plurality of arrays for use based on the determination of the operational status of the plurality of arrays. Also described is a focal plane array including a circuit having a plurality of electrical contacts and a die including a plurality of identical arrays, each including a plurality of detectors. The plurality of identical arrays includes at least one selected array that is fully functional and at least one non-selected array that is not fully functional and the selected array is positioned with respect to the circuit so that the detectors of the selected array contact the plurality of electrical contacts of the circuit.

Abstract: The present disclosure provides devices and methods in which a semiconductor chip has a reduced size and thickness. The device is manufactured by utilizing a sacrificial or dummy silicon wafer. A recess is formed in the dummy silicon wafer where the semiconductor chip is mounted in the recess. The space between the dummy silicon wafer and the chip is filled with underfill material. The dummy silicon wafer and the backside of the chip are etched using any suitable etching process until the dummy silicon wafer is removed, and the thickness of the chip is reduced. With this process, the overall thickness of the semiconductor chip can be thinned down to less than 50 ?m in some embodiments. The ultra-thin semiconductor chip can be incorporated in manufacturing flexible/rollable display panels, foldable mobile devices, wearable displays, or any other electrical or electronic devices.

Abstract: An image sensor includes a substrate, first and second insulating structures, a first wiring structure, a through via, and first and second connection patterns. The substrate includes a sensor array region and a pad region. The first insulating structure is disposed on a second surface of the substrate. The first wiring structure is formed in the first insulating structure and includes first conductive layers and first vias. The through via passes through the substrate in the pad region and connects to the first wiring structure. The first connection pattern is connected to the first wiring structure. The second insulating structure is disposed on a fourth surface of the first insulating structure. The second connection pattern is connected to the first connection pattern. The first conductive layers include a first wiring, and a second wiring spaced farther from the substrate than the first wiring. The through via contacts the second wiring.

Abstract: A photodetection element includes a semiconductor layer having, on one surface side, a periodic concave/convex structure that includes periodic convex portions and concave portions and converts light into surface plasmon, and a metal film provided on the one surface side of the semiconductor layer in correspondence to the periodic concave/convex structure, and in the periodic concave/convex structure, a Schottky junction portion that has a Schottky junction with the metal film is provided on a base end side of the convex portion, and a non-Schottky junction portion that does not have a Schottky junction with the metal film is provided on a distal end side of the convex portion.

Abstract: A backside-illuminated photodetector structure comprising a first reflecting region, a second reflecting region and a semiconductor region. The semiconductor region is between the first reflecting region and the second reflecting region. The semiconductor region comprises a first doped region and a second doped region.

Abstract: A backside-illuminated photodetector structure comprising a first reflecting region, a second reflecting region and a semiconductor region. The semiconductor region is between the first reflecting region and the second reflecting region. The semiconductor region comprises a first doped region and a second doped region.

Abstract: A nanostructured or microstructured array of elements on a conductor layer together form a device electrode of a photovoltaic or detector structure. The array on the conductor layer has a high surface area to volume ratio configuration defining a void matrix between elements. An active layer or active layer precursors is disposed into the void matrix as a liquid to form a thickness coverage giving an interface on which a counter-electrode is positioned parallel to the conduction layer or as a vapor to form a conformal thickness coverage of the array and conduction layer. The thickness coverage is controlled to enhance collection of at least one of electrons and holes arising from photogeneration, or excitons arising from photogeneration, to the device electrode or a device counter-electrode as well as light absorption in said active layer via reflection and light trapping of said device electrode.

Abstract: A semiconductor device is provided with a substrate including a main surface and a back surface that face in opposite directions to each other in a thickness direction, and first, second and third direction sensor elements having different detection reference axes from each other. The substrate is formed with a recessed portion that is recessed from the main surface toward the back surface side. The first direction sensor element is disposed at least partially within the recessed portion. The second direction sensor element is disposed so as to overlap with the main surface as viewed in the thickness direction.

Abstract: A semiconductor device manufacturing method includes a wafer stack manufacturing process and a dicing process. The wafer stack manufacturing process includes: a first wafer manufacturing process of manufacturing a resin film covering circuits and heated to a temperature higher than a glass transition point of the resin film, manufacturing first holes extending from a surface of the resin film to wirings of the circuits, and providing electrodes electrically connected to the wirings in the first holes to form a first wafer; a second wafer manufacturing process of manufacturing a resin film covering circuits and heated to a temperature lower than a glass transition point of the resin film, manufacturing second holes extending from a surface of the resin film to wirings of the circuits, and providing the electrodes electrically connected to the wirings in the second holes to form a second wafer; and a wafer bonding process.

Abstract: A method of making a diode begins by depositing an AlxGa1-xN nucleation layer on a SiC substrate, then depositing an n+ GaN buffer layer, an n? GaN layer, an AlxGa1-xN barrier layer, and an SiO2 dielectric layer. A portion of the dielectric layer is removed and a Schottky metal deposited in the void. The dielectric layer is affixed to the support layer with a metal bonding layer using an Au—Sn utectic wafer bonding process, the substrate is removed using reactive ion etching to expose the n+ layer, selected portions of the n+, n?, and barrier layers are removed to form a mesa diode structure on the dielectric layer over the Schottky metal; and an ohmic contact is deposited on the n+ layer.

Abstract: A semiconductor apparatus includes: a first sheet-like member having a light receiving surface of an imaging device and a first connection terminal disposed thereon, the imaging device generating an image by receiving incident light from a light collecting section for collecting external light disposed thereon; a second sheet-like member having a second connection terminal to be connected to the first connection terminal provided thereon; a conductive bonding portion made of a conductive material and bonded with the first connection terminal; and a bonding wire connecting the conductive bonding portion and the second connection terminal, wherein the bonding wire is disposed along the plane of the first sheet-like member such that reflected light from the bonding wire does not impinge on the light receiving surface.

Abstract: An iridium interfacial stack (“IrIS”) and a method for producing the same are provided. The IrIS may include ordered layers of TaSi2, platinum, iridium, and platinum, and may be placed on top of a titanium layer and a silicon carbide layer. The IrIS may prevent, reduce, or mitigate against diffusion of elements such as oxygen, platinum, and gold through at least some of its layers.

Abstract: An object is to provide a display device with a high aperture ratio or a semiconductor device in which the area of an element is large. A channel formation region of a TFT with a multi-gate structure is provided under a wiring that is provided between adjacent pixel electrodes (or electrodes of an element). In addition, a channel width direction of each of a plurality of channel formation regions is parallel to a longitudinal direction of the pixel electrode. In addition, when a channel width is longer than a channel length, the area of the channel formation region can be increased.

Abstract: A method of manufacturing an LED package including steps: providing an electrode, the electrode including a first electrode, a second electrode, a channel defined between the first electrode and the second electrode, the first electrode and the second electrode arranged with intervals mutually, a cavity arranged on the first electrode, and the cavity communicating with the channel; arranging an LED chip electrically connecting with the first electrode and the second electrode and arranged inside the cavity; providing a shield covering the first electrode and the second electrode; injecting a transparent insulating material to the cavity via the channel, and the first electrode, the second electrode, and the shield being interconnected by the transparent insulating material; solidifying the transparent insulating material to obtain the LED package.

Abstract: A photodetector having a ridge-in-slit geometry is provided, where a semiconductor ridge is laterally sandwiched in a metallic slit. This assembly is disposed on a layer of semiconducting material, which in turn is disposed on an insulating substrate. These structures can provide efficient resonant detectors having the wavelength of peak response set by the ridge width. Thus a lateral feature defines the wavelength of peak responsivity, as opposed to a vertical feature.

Abstract: A semiconductor chip is specified that has a contact layer that is not optimum for many common applications. For example, the contact layer is too thin to tolerate an operating current intended for the semiconductor chip without considerable degradation. Also specified is an optoelectronic component in which the semiconductor chip can be integrated so that the suboptimal quality of the contact layer is compensated for. In the component the semiconductor chip is applied to a carrier body so that the contact layer is arranged on a side of the semiconductor body that is remote from the carrier body. The semiconductor chip and the carrier body are at least partly covered with an electrically isolating layer, and an electrical conductor applied to the isolating layer extends laterally away from the semiconductor body and contacts at least a partial surface of the contact layer. In addition, an advantageous process for producing the component is specified.

Abstract: A method of fabricating a semiconductor device is disclosed. A first contact layer of the semiconductor device is fabricated. An electrical connection is formed between a carbon nanotube and the first contact layer by electrically coupling of the carbon nanotube and a second contact layer. The first contact layer and second contact layer may be electrically coupled.

Abstract: A semiconductor chip is specified that has a contact layer that is not optimum for many common applications. For example, the contact layer is too thin to tolerate an operating current intended for the semiconductor chip without considerable degradation. Also specified is an optoelectronic component in which the semiconductor chip can be integrated so that the suboptimal quality of the contact layer is compensated for. In the component the semiconductor chip is applied to a carrier body so that the contact layer is arranged on a side of the semiconductor body that is remote from the carrier body. The semiconductor chip and the carrier body are at least partly covered with an electrically isolating layer, and an electrical conductor applied to the isolating layer extends laterally away from the semiconductor body and contacts at least a partial surface of the contact layer. In addition, an advantageous process for producing the component is specified.

Abstract: A component and a method for producing a component are disclosed. The component comprises an integrated circuit, a housing body, a wiring device overlapping the integrated circuit and the housing body, and one or more external contact devices in communication with the wiring device.

Abstract: A germanium semiconductor radiation detector contact made of yttrium metal. A thin (˜1000 ?) deposited layer of yttrium metal forms a thin hole-barrier and/or electron-barrier contact on both p- and n-type germanium semiconductor radiation detectors. Yttrium contacts provide a sufficiently high hole barrier to prevent measurable contact leakage current below ˜120 K. The yttrium contacts can be conveniently segmented into multiple electrically independent electrodes having inter-electrode resistances greater than 10 G?. Germanium semiconductor radiation detector diodes fabricated with yttrium contacts provide good gamma-ray spectroscopy data.

Abstract: According to one embodiment, a semiconductor light emitting device includes: a stacked structure body, first and second electrodes, and a pad layer. The body includes first semiconductor layer of a first conductivity type, a light emitting layer, and a second semiconductor layer of second conductivity type. The first semiconductor layer has first and second portions. The light emitting layer is provided on the second portion. The second semiconductor layer is provided on the light emitting layer. The first electrode is provided on the first portion. The second electrode is provided on the second semiconductor layer and is transmittable to light emitted from the light emitting layer. The pad layer is connected to the second electrode. A transmittance of the pad layer is lower than that of the second electrode. A sheet resistance of the second electrode increases continuously along a direction from the pad layer toward the first electrode.

Abstract: A photoelectric conversion device is provided which is capable of improving the light condensation efficiency without substantially decreasing the sensitivity. The photoelectric conversion device has a first pattern provided above an element isolation region formed between adjacent two photoelectric conversion elements, a second pattern provided above the element isolation region and above the first pattern, and microlenses provided above the photoelectric conversion elements with the first and the second patterns provided therebetween. The photoelectric conversion device further has convex-shaped interlayer lenses in optical paths between the photoelectric conversion elements and the microlenses, the peak of each convex shape projecting in the direction from the electro-optical element to the microlens.

Abstract: A photodetector is described along with corresponding materials, systems, and methods. The photodetector comprises an integrated circuit and at least two optically sensitive layers. A first optically sensitive layer is over at least a portion of the integrated circuit, and a second optically sensitive layer is over the first optically sensitive layer. Each optically sensitive layer is interposed between two electrodes. The two electrodes include a respective first electrode and a respective second electrode. The integrated circuit selectively applies a bias to the electrodes and reads signals from the optically sensitive layers. The signal is related to the number of photons received by the respective optically sensitive layer.

Abstract: A photodetector is described along with corresponding materials, systems, and methods. The photodetector comprises an integrated circuit and at least two optically sensitive layers. A first optically sensitive layer is over at least a portion of the integrated circuit, and a second optically sensitive layer is over the first optically sensitive layer. Each optically sensitive layer is interposed between two electrodes. The two electrodes include a respective first electrode and a respective second electrode. The integrated circuit selectively applies a bias to the electrodes and reads signals from the optically sensitive layers. The signal is related to the number of photons received by the respective optically sensitive layer.

Abstract: A photodetector is described along with corresponding materials, systems, and methods. The photodetector comprises an integrated circuit and at least two optically sensitive layers. A first optically sensitive layer is over at least a portion of the integrated circuit, and a second optically sensitive layer is over the first optically sensitive layer. Each optically sensitive layer is interposed between two electrodes. The two electrodes include a respective first electrode and a respective second electrode. The integrated circuit selectively applies a bias to the electrodes and reads signals from the optically sensitive layers. The signal is related to the number of photons received by the respective optically sensitive layer.

Abstract: A photodetector is described along with corresponding materials, systems, and methods. The photodetector comprises an integrated circuit and at least two optically sensitive layers. A first optically sensitive layer is over at least a portion of the integrated circuit, and a second optically sensitive layer is over the first optically sensitive layer. Each optically sensitive layer is interposed between two electrodes. The two electrodes include a respective first electrode and a respective second electrode. The integrated circuit selectively applies a bias to the electrodes and reads signals from the optically sensitive layers. The signal is related to the number of photons received by the respective optically sensitive layer.

Abstract: Charged particle sensing devices and methods of forming charged particle sensing devices are provided. The charged particle sensing device includes a source of charged particles, a plurality of collector electrodes for receiving a first portion of the charged particles and a grid formed around and spaced apart from the plurality of collector electrodes. The grid receives a second portion of the charged particles and directs backscattered charged particles, generated responsive to the second portion, to adjacent collector electrodes.

Abstract: A photodetector is described along with corresponding materials, systems, and methods. The photodetector comprises an integrated circuit and at least two optically sensitive layers. A first optically sensitive layer is over at least a portion of the integrated circuit, and a second optically sensitive layer is over the first optically sensitive layer. Each optically sensitive layer is interposed between two electrodes. The two electrodes include a respective first electrode and a respective second electrode. The integrated circuit selectively applies a bias to the electrodes and reads signals from the optically sensitive layers. The signal is related to the number of photons received by the respective optically sensitive layer.

Abstract: A photodetector is described along with corresponding materials, systems, and methods. The photodetector comprises an integrated circuit and at least two optically sensitive layers. A first optically sensitive layer is over at least a portion of the integrated circuit, and a second optically sensitive layer is over the first optically sensitive layer. Each optically sensitive layer is interposed between two electrodes. The two electrodes include a respective first electrode and a respective second electrode. The integrated circuit selectively applies a bias to the electrodes and reads signals from the optically sensitive layers. The signal is related to the number of photons received by the respective optically sensitive layer.

Abstract: The present invention is to provide an electromagnetic wave detecting element that can prevent a decrease in light utilization efficiency at sensor portions. The sensor portions are provided so as to correspond to respective intersection portions of scan lines and signal lines, and have semiconductor layer that generate charges due to electromagnetic waves being irradiated, and at whose electromagnetic wave irradiation surface sides upper electrodes are formed, and at whose electromagnetic wave non-irradiation surface sides lower electrodes are formed. Bias voltage is supplied to the respective upper electrodes via respective contact holes by a common electrode line that is formed further toward an electromagnetic wave downstream side than the semiconductor layer.

Abstract: An object is to provide a display device with a high aperture ratio or a semiconductor device in which the area of an element is large. A channel formation region of a TFT with a multi-gate structure is provided under a wiring that is provided between adjacent pixel electrodes (or electrodes of an element). In addition, a channel width direction of each of a plurality of channel formation regions is parallel to a longitudinal direction of the pixel electrode. In addition, when a channel width is longer than a channel length, the area of the channel formation region can be increased.

Abstract: A method of making a diode begins by depositing an AlxGa1-xN nucleation layer on a SiC substrate, then depositing an n+ GaN buffer layer, an n? GaN layer, an AlxGa1-xN barrier layer, and an SiO2 dielectric layer. A portion of the dielectric layer is removed and a Schottky metal deposited in the void. The dielectric layer is affixed to the support layer with a metal bonding layer using an Au—Sn utectic wafer bonding process, the substrate is removed using reactive ion etching to expose the n+ layer, selected portions of the n+, n?, and barrier layers are removed to form a mesa diode structure on the dielectric layer over the Schottky metal, and an ohmic contact is deposited on the n+ layer.

Abstract: Flexible laminated thin film photovoltaic systems that include flexible support structures having a upper surface and a lower surface, at least one thin film photovoltaic module laminated to the upper surface of the flexible support structure, the at least one thin film photovoltaic module including lead wires and a flexible wiring conduit system attached to the lower side of the flexible support structure though which the lead wires of the at least one thin film photovoltaic module are routed. The peripheral edges of the thin film photovoltaic modules and adjacent surrounding portions of the flexible support structure are laminated with flexible strip members which prevent the peripheral edges of the thin film photovoltaic modules from peeling off the flexible support structure.

Abstract: A device that includes a signal generating unit having a surface that can receive photons, a first metal structure located on the surface of the signal generating unit, and a second metal structure located on the surface of the signal generating unit. The second metal structure being spaced apart from the first metal structure.

Abstract: It is an object of the present invention to surely protect a predetermined semiconductor element or a predetermined semiconductor element group in an analog block from a noise generated from a digital block. A semiconductor device according to the present invention includes a semiconductor substrate, a digital block to be a region in which a digital circuit is formed and an analog block to be a region in which an analog circuit is formed, arranged by separating an upper surface of the semiconductor substrate and a substrate potential fixing region provided on the semiconductor substrate so as to surround in a planar view the predetermined semiconductor element group in the analog block, and a pad connected to the substrate potential fixing region and receiving a predetermined potential from an external part.

Abstract: The present invention is to provide an electromagnetic wave detecting element that can prevent a decrease in light utilization efficiency at sensor portions. The sensor portions are provided so as to correspond to respective intersection portions of scan lines and signal lines, and have semiconductor layer that generate charges due to electromagnetic waves being irradiated, and at whose electromagnetic wave irradiation surface sides upper electrodes are formed, and at whose electromagnetic wave non-irradiation surface sides lower electrodes are formed. Bias voltage is supplied to the respective upper electrodes via respective contact holes by a common electrode line that is formed further toward an electromagnetic wave downstream side than the semiconductor layer.

Abstract: In one embodiment, active diffusion junctions of a solar cell are formed by diffusing dopants from dopant sources selectively deposited on the back side of a wafer. The dopant sources may be selectively deposited using a printing method, for example. Multiple dopant sources may be employed to form active diffusion regions of varying doping levels. For example, three or four active diffusion regions may be fabricated to optimize the silicon/dielectric, silicon/metal, or both interfaces of a solar cell. The front side of the wafer may be textured prior to forming the dopant sources using a texturing process that minimizes removal of wafer material. Openings to allow metal gridlines to be connected to the active diffusion junctions may be formed using a self-aligned contact opening etch process to minimize the effects of misalignments.

Abstract: A low profile high power Schottky barrier bypass diode for solar cells and panels with the cathode and anode electrodes on the same side of the diode and a method of fabrication thereof are disclosed for generating a thin chip with both electrodes being on the same side of the chip. In an embodiment, a mesa isolation with a Zener diode over the annular region surrounding the central region of the mesa anode in the Epi of the substrate is formed. In an embodiment, a P-type Boron dopant layer is ion implanted in the annular region for the Zener Diode. This controls recovery from high voltage spikes from the diode rated voltage. A Schottky barrier contact for the anode and a contact for the cathode are simultaneously created on the same side of the chip.

Abstract: A photovoltaic cell and a method of forming an electrode grid on a photovoltaic semiconductor substrate of a photovoltaic cell are disclosed. In one embodiment, the photovoltaic cell comprises a photovoltaic semiconductor substrate; a back electrode electrically connected to a back surface of the substrate; and a front electrode electrically connected to a front surface of the substrate. The substrate, back electrode, and front electrode form an electric circuit for generating an electric current when said substrate absorbs light. The front electrode is comprised of a metal grid defining a multitude of holes. These holes may be periodic, aperiodic, or partially periodic. The front electrode may be formed by depositing nanospheres on the substrate; forming a metallic layer on the substrate, around the nanospheres; and removing the nanospheres, leaving an electrode grid defining a multitude of holes on the substrate.

Abstract: A photodiode array PD1 comprises an n-type semiconductor substrate one face of which is an incident surface of light to be detected; a plurality of pn junction-type photosensitive regions 3 as photodiodes formed on the side of a detecting surface that is opposite to the incident surface of the semiconductor substrate; and a carrier capturing portion 12 formed between adjacent photosensitive regions 3 from among the plurality of photosensitive regions 3 on the detecting surface side of the semiconductor substrate. The carrier capturing portion 12 has one or plurality of carrier capturing regions 13 respectively including pn-junctions, arranged at intervals. Thereby can be realized a semiconductor photodetector and a radiation detecting apparatus which can favorably restrain crosstalk from occurring.

Abstract: A lateral photodiode, with improved response speed, includes a semiconductor substrate having active regions, and a p-type region and an n-type region arranged parallel to the surface of the substrate. The active regions are an n-layer and a p-layer respectively, and stacked in the thickness direction of the substrate to form a p-n junction. In addition, a barrier layer, for preventing movement of carriers from the substrate toward the active region, is provided on the side of the active regions toward the substrate.

Abstract: A system and method is disclosed for allowing a solid substrate, such as a printed circuit board (PCB), to act as the support structure for an electronic circuit. In one embodiment, the LEDs which form a part of a scrambler assembly are constructed on a first substrate and the electrical connections are run to the edges of the substrate and end in electrical contacts positioned thereat. The substrate is then connected to the scrambler package by a series of electrical and mechanical connections to form the LED package. The electrical contacts which are part of the LED package extend from the LED package so as to enable electrical contact with a separate controller substrate.

Abstract: A compact resistive thermal sensor is provided for an integrated circuit (IC), wherein different sensor components are placed on different layers of the IC. This allows the lateral area needed for the sensor resistance wire on any particular IC layer to be selectively reduced. In a useful embodiment, a plurality of first linear conductive members are positioned in a first IC layer, in spaced-apart parallel relationship with one another. A plurality of second linear conductive members are similarly positioned in a second IC layer in spaced-apart parallel relationship with one another, and in orthogonal relationship with the first linear members or in parallel with existing wiring channels of the second IC layer. Conductive elements respectively connect the first linear members into a first conductive path, and the second linear members into a second conductive path.

Abstract: In one example, an optical detector includes a photosensitive layer, and a group of additional layers associated with that photosensitive layer. The group of additional layers may include first and second contact layer configured for electrical communication with the photosensitive layer. In this example, one of the group of layers is shaped so as to define a corner whose radius of curvature is greater than about 2 microns.

Abstract: A method for forming a photodiode cathode in an integrated circuit imager includes defining and implanting a photodiode cathode region with a photodiode cathode implant dose of a dopant species and defining and implanting an edge region of the photodiode cathode region with a photodiode cathode edge implant dose of a dopant species to form a region of higher impurity concentration than the photodiode cathode impurity concentration.

Abstract: A component and a method for producing a component are disclosed. The component comprises an integrated circuit, a housing body, a wiring device overlapping the integrated circuit and the housing body, and one or more external contact devices in communication with the wiring device.

Abstract: An object is to provide a display device with a high aperture ratio or a semiconductor device in which the area of an element is large. A channel formation region of a TFT with a multi-gate structure is provided under a wiring that is provided between adjacent pixel electrodes (or electrodes of an element). In addition, a channel width direction of each of a plurality of channel formation regions is parallel to a longitudinal direction of the pixel electrode. In addition, when a channel width is longer than a channel length, the area of the channel formation region can be increased.

Abstract: In mixed-component, mixed-signal, semiconductor devices, selective seal ring isolation from the substrate and its electrical potential is provided in order to segregate noise sensitive circuitry from electrical noise generated by electrically noisy circuitry. Appropriate predetermined sections of such a mixed use chip are isolated from the substrate through a non-ohmic contact with the substrate without compromising reliability of the chip's isolation from scribe region contamination.