Schottky Barrier (e.g., A Transparent Schottky Metallic Layer Or A Schottky Barrier Containing At Least One Of Indium Or Tin (e.g., Sno 2 , Indium Tin Oxide)) Patents (Class 257/449)
  • Patent number: 10796953
    Abstract: For simplifying the dual-damascene formation steps of a multilevel Cu interconnect, a formation step of an antireflective film below a photoresist film is omitted. Described specifically, an interlayer insulating film is dry etched with a photoresist film formed thereover as a mask, and interconnect trenches are formed by terminating etching at the surface of a stopper film formed in the interlayer insulating film. The stopper film is made of an SiCN film having a low optical reflectance, thereby causing it to serve as an antireflective film when the photoresist film is exposed.
    Type: Grant
    Filed: March 12, 2020
    Date of Patent: October 6, 2020
    Assignee: Renesas Electronics Corporation
    Inventors: Katsuhiko Hotta, Kyoko Sasahara
  • Patent number: 10700225
    Abstract: Lateral and vertical microstructure enhanced photodetectors and avalanche photodetectors are monolithically integrated with CMOS/BiCMOS ASICs and can also be integrated with laser devices using fluidic assembly techniques. Photodetectors can be configured in a vertical PIN arrangement or lateral metal-semiconductor-metal arrangement where electrodes are in an inter-digitated pattern. Microstructures, such as holes and protrusions, can improve quantum efficiency in silicon, germanium and III-V materials and can also reduce avalanche voltages for avalanche photodiodes. Applications include optical communications within and between datacenters, telecommunications, LIDAR, and free space data communication.
    Type: Grant
    Filed: July 23, 2018
    Date of Patent: June 30, 2020
    Assignee: W&WSENS DEVICES, INC.
    Inventors: Shih-Yuan Wang, Shih-Ping Wang
  • Patent number: 10388806
    Abstract: The technique introduced herein decouples the traditional relationship between bandwidth and responsivity, thereby providing a more flexible and wider photodetector design space. In certain examples of the technique introduced here, a photodetector device includes a first mirror, a second mirror, and a light absorption region positioned between the first and second reflective mirrors. For example, the first mirror can be a low-reflectivity mirror, and the second mirror can be a high-reflectivity mirror. The light absorption region is positioned to absorb incident light that is passed through the first mirror and reflected between the first and second mirrors. The first mirror can be configured to exhibit a reflectivity that causes an amount of light energy that escapes from the first mirror, after the light being reflected back by the second mirror, to be zero or near zero.
    Type: Grant
    Filed: December 24, 2015
    Date of Patent: August 20, 2019
    Assignee: Artilux, Inc.
    Inventors: Shu-Lu Chen, Yun-Chung Na
  • Patent number: 10310060
    Abstract: An apparatus including a semiconductor substrate; an absorption layer coupled to the semiconductor substrate, the absorption layer including a photodiode region configured to absorb photons and to generate photo-carriers from the absorbed photons; one or more first switches controlled by a first control signal, the one or more first switches configured to collect at least a portion of the photo-carriers based on the first control signal; and one or more second switches controlled by a second control signal, the one or more second switches configured to collect at least a portion of the photo-carriers based on the second control signal, where the second control signal is different from the first control signal.
    Type: Grant
    Filed: October 5, 2018
    Date of Patent: June 4, 2019
    Assignees: Artilux Corporation, Artilux Inc.
    Inventors: Yun-Chung Na, Che-Fu Liang
  • Patent number: 10274808
    Abstract: A device, system, and method for in situ reconfigurable quasi-phase matching field-programmable nonlinear photonics that is reliably reconfigurable and maintains nonlinear conversion efficiency is presented. Devices include a ferroelectric waveguide susceptible to light-assisted poling; (UV-transparent) first electrode(s); one or more UV illumination sources; at least a second electrode; and a substrate. Reconfiguring the hybrid electronic/photonic field programmable array device includes selecting a device type; selecting parameters for the device; determining per-electrode voltages for the device; determining timing values for reconfiguring the device; initiating illumination of the device; applying per-electrode voltages of the device; terminating per-electrode voltages according to the timing values; and terminating illumination according to the timing values.
    Type: Grant
    Filed: March 14, 2018
    Date of Patent: April 30, 2019
    Assignee: BAE Systems Information and Electronic Systems Integration Inc.
    Inventor: Mackenzie A. Van Camp
  • Patent number: 9935081
    Abstract: Methods of packaging semiconductor devices and structures thereof are disclosed. In one embodiment, a method of packaging a semiconductor device includes providing a substrate, and adhering a first semiconductor device. Chip stacks are formed by providing a plurality of semiconductor devices and bonding them to the substrate and the first semiconductor device. At least one of the provided semiconductor devices is physically connected to both the substrate and the first semiconductor device it is stack on. Other semiconductor devices may stacked by forming conductive channels in the first semiconductor device, and placing the other semiconductor devices in physical contact with the first semiconductor device and the conductive channels.
    Type: Grant
    Filed: August 20, 2014
    Date of Patent: April 3, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kuo Lung Pan, Yu-Feng Chen, Chen-Shien Chen, Mirng-Ji Lii
  • Patent number: 9654027
    Abstract: A semiconductor device is provided that can prevent a current from being concentrated into a specific chip, and can reduce loss as well as noise. The semiconductor device according to the present invention includes: a switching element; a main diode that is connected in parallel to the switching element; and an auxiliary diode that is connected in parallel to the switching element and has a different structure from that of the main diode, wherein in a conductive state a current flowing through the auxiliary diode is smaller than that through the main diode, and in a transition period from the conductive state to a non-conductive state a current flowing through the auxiliary diode is larger than that through the main diode.
    Type: Grant
    Filed: May 22, 2015
    Date of Patent: May 16, 2017
    Assignee: Hitachi, Ltd.
    Inventors: Takashi Hirao, Mutsuhiro Mori
  • Patent number: 9455365
    Abstract: A light-induced diode-like response in multi-layered MoSe2 field-effect transistors resulting from a difference in the size of the Schottky barriers between drain and source contacts, wherein each barrier can be modeled as a Schottky diode but with opposite senses of current rectification, wherein the diode response results from the light induced promotion of photo-generated carriers across the smaller barrier. The sense of current rectification can be controlled by the gate voltage which is able to modulate the relative amplitude between both barriers, yielding a photovoltaic response.
    Type: Grant
    Filed: February 26, 2016
    Date of Patent: September 27, 2016
    Assignee: The Florida State University Research Foundation, Inc.
    Inventors: Luis Balicas, Nihar R. Pradhan, Efstratios Manousakis
  • Patent number: 9245991
    Abstract: A semiconductor device includes a substrate, a channel layer over the substrate, an active layer over the channel layer, and a barrier structure between the substrate and the channel layer. The active layer is configured to cause a two dimensional electron gas (2DEG) to be formed in the channel layer along an interface between the channel layer and the active layer. The barrier structure is configured to block diffusion of at least one of a material of the substrate or a dopant toward the channel layer.
    Type: Grant
    Filed: August 12, 2013
    Date of Patent: January 26, 2016
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Po-Chun Liu, Chi-Ming Chen, Chen-Hao Chiang, Chung-Yi Yu, Chia-Shiung Tsai, Xiaomeng Chen
  • Patent number: 9142705
    Abstract: An in-line production apparatus and a method for composition control of copper indium gallium diselenide (CIGS) solar cells fabricated by a co-evaporation deposition process. The deposition conditions are so that a deposited Cu-excessive overall composition is transformed into to a Cu-deficient overall composition, the final CIGS film. Substrates with a molybdenum layer move through the process chamber with constant speed. The transition from copper rich to copper deficient composition on a substrate is detected by using sensors which detect a physical parameter related to the transition. A preferred embodiment sensors are provided that detect the composition of elements in the deposited layer. A controller connected to the sensors adjusts the fluxes from the evaporant sources in order provide a CIGS layer with uniform composition and thickness over the width of the substrate.
    Type: Grant
    Filed: March 4, 2005
    Date of Patent: September 22, 2015
    Assignee: SOLIBRO RESEARCH AB
    Inventors: Lars Stolt, John Kessler
  • Patent number: 9041139
    Abstract: A method of making a diode begins by depositing an AlxGa1-xN nucleation layer on a SiC substrate, then depositing an n+ GaN buffer layer, an n? GaN layer, an AlxGa1-xN barrier layer, and an SiO2 dielectric layer. A portion of the dielectric layer is removed and a Schottky metal deposited in the void. The dielectric layer is affixed to the support layer with a metal bonding layer using an Au—Sn utectic wafer bonding process, the substrate is removed using reactive ion etching to expose the n+ layer, selected portions of the n+, n?, and barrier layers are removed to form a mesa diode structure on the dielectric layer over the Schottky metal; and an ohmic contact is deposited on the n+ layer.
    Type: Grant
    Filed: December 4, 2012
    Date of Patent: May 26, 2015
    Assignee: Cree, Inc.
    Inventors: Primit Parikh, Sten Heikman
  • Patent number: 9035410
    Abstract: An avalanche photodiode detector is provided. The avalanche photodiode detector comprises an absorber region having an absorption layer for receiving incident photons and generating charged carriers; and a multiplier region having a multiplication layer; wherein the multiplier region is on a mesa structure separate from the absorber region and is coupled to the absorber region by a bridge for transferring charged carriers between the absorber region and multiplier region.
    Type: Grant
    Filed: September 12, 2008
    Date of Patent: May 19, 2015
    Assignee: THE BOEING COMPANY
    Inventors: Ping Yuan, Joseph C. Boisvert, Dmitri D. Krut, Rengarajan Sudharsanan
  • Patent number: 9035321
    Abstract: There is provided a semiconductor device including an ohmic junction layer which is excellent in surface flatness and uniformity of composition in an interface with a semiconductor substrate and thus can give a sufficiently high adhesiveness with a Schottky junction layer.
    Type: Grant
    Filed: August 20, 2009
    Date of Patent: May 19, 2015
    Assignee: SHOWA DENKO K.K.
    Inventors: Akihiro Matsuse, Kotaro Yano
  • Publication number: 20150084061
    Abstract: A photo-detecting device includes a first nitride layer, a low-current blocking layer disposed on the first nitride layer, a light absorption layer disposed on the low-current blocking layer, and a Schottky junction layer disposed on the light-absorption layer. The low-current blocking layer includes a multilayer structure.
    Type: Application
    Filed: September 25, 2014
    Publication date: March 26, 2015
    Inventors: Ki Yon PARK, Hwa Mok KIM, Kyu-Ho LEE, Sung Hyun LEE, Hyung Kyu KIM
  • Patent number: 8963276
    Abstract: A semiconductor device that can achieve a high-speed operation at a time of switching, and the like. The semiconductor device includes: a p-type buried layer buried within an n?-type semiconductor layer; and a p-type surface layer formed in a central portion of each of cells. In a contact cell, the p-type buried layer is in contact with the p-type surface layer. The semiconductor device further includes: a p+-type contact layer formed on the p-type surface layer of the contact cell; and an anode electrode provided on the n?-type semiconductor layer. The anode electrode forms a Schottky junction with the n?-type semiconductor layer and forms an ohmic junction with the p+-type contact layer.
    Type: Grant
    Filed: December 22, 2011
    Date of Patent: February 24, 2015
    Assignee: Mitsubishi Electric Corporation
    Inventors: Hiroshi Watanabe, Naoki Yutani, Yoshiyuki Nakaki, Kenichi Ohtsuka
  • Patent number: 8946839
    Abstract: An absorber is disclosed. The disclosed absorber contains a base layer, and a plurality of pillars disposed above the base layer and composed of material configured to absorb an incident light and generate minority electrical carriers and majority electrical carrier, wherein the height of the pillars is predetermined to provide a common pyramidal outline shared by the pillars in the plurality of pillars.
    Type: Grant
    Filed: August 20, 2009
    Date of Patent: February 3, 2015
    Assignee: HRL Laboratories, LLC
    Inventors: Daniel Yap, Rajesh D. Rajavel, Sarabjit Mehta, James H. Schaffner
  • Patent number: 8916946
    Abstract: The present invention is intended to provide a compact and simple optical semiconductor device that reduces crosstalk (leakage current) between light receiving elements. According to the present invention, since a back surface electrode is a mirror-like thin film, crosstalk to an adjacent light receiving element can be suppressed, thereby reducing a detection error of a light intensity. By disposing a patterned back surface electrode or by disposing an ohmic electrode at the bottom of an insulating film over the whole back surface, contact resistance on the back surface can be reduced. By using the optical semiconductor elements with a two-dimensional arrangement and by using a mirror-like thin film as the back surface electrode, crosstalk can be reduced. By accommodating the optical semiconductor elements in the housing in a highly hermetic condition, the optical semiconductor elements can be protected from an external environment.
    Type: Grant
    Filed: March 4, 2014
    Date of Patent: December 23, 2014
    Assignees: Nippon Telegraph and Telephone Corporation, NTT Electronics Corporation
    Inventors: Yoshiyuki Doi, Yoshifumi Muramoto, Takaharu Ohyama
  • Patent number: 8828790
    Abstract: A method for local contacting and local doping of a semiconductor layer including the following process steps: A) Generation of a layer structure on the semiconductor layer through i) application of at least one intermediate layer on one side of the semiconductor layer, and ii) application of at least one metal layer onto the intermediate layer last applied in step i), wherein the metal layer at least partly covers the last applied intermediate layer, B) Local heating of the layer structure in such a manner that in a local region a short-time melt-mixture of at least partial regions of at least the layers: metal layer, intermediate layer and semiconductor layer, forms. After solidification of the melt-mixture, a contacting is created between metal layer and semiconductor layer. It is essential that in step A) i) at least one intermediate layer designed as dopant layer is applied, which contains a dopant wherein the dopant has a greater solubility in the semiconductor layer than the metal of the metal layer.
    Type: Grant
    Filed: August 20, 2009
    Date of Patent: September 9, 2014
    Assignee: Fraunhofer-Gesellschaft zur Forderung der Angewandten Forschung E.V.
    Inventors: Ralf Preu, Andreas Grohe, Daniel Biro, Jochen Rentsch, Marc Hofmann, Jan-Frederik Nekarda, Andreas Wolf
  • Patent number: 8796703
    Abstract: A display device includes a transparent substrate, and a plurality of single-crystal thin-film semiconductor light-emitting elements disposed on one side of the transparent substrate. Each of the single-crystal thin-film semiconductor light-emitting elements is composed of single-crystal thin-film semiconductor layers separated from a base substrate, and includes a light-emitting layer and two non-light-emitting layers disposed on both sides of the light-emitting layer.
    Type: Grant
    Filed: July 3, 2013
    Date of Patent: August 5, 2014
    Assignee: Oki Data Corporation
    Inventors: Mitsuhiko Ogihara, Kazuo Tokura
  • Patent number: 8759829
    Abstract: To reduce adverse effects on actual operation and to reduce adverse effects of noise. A structure including an electrode, a wiring electrically connected to the electrode, an oxide semiconductor layer overlapping with the electrode in a plane view, an insulating layer provided between the electrode and the oxide semiconductor layer in a cross-sectional view, and a functional circuit to which a signal is inputted from the electrode through the wiring and in which operation is controlled in accordance with the signal inputted. A capacitor is formed using an oxide semiconductor layer, an insulating layer, and a wiring or an electrode.
    Type: Grant
    Filed: August 14, 2012
    Date of Patent: June 24, 2014
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Hideki Uochi, Daisuke Kawae
  • Patent number: 8704322
    Abstract: The present invention is intended to provide a compact and simple optical semiconductor device that reduces crosstalk (leakage current) between light receiving elements. According to the present invention, since a back surface electrode is a mirror-like thin film, crosstalk to an adjacent light receiving element can be suppressed, thereby reducing a detection error of a light intensity. By disposing a patterned back surface electrode or by disposing an ohmic electrode at the bottom of an insulating film over the whole back surface, contact resistance on the back surface can be reduced. By using the optical semiconductor elements with a two-dimensional arrangement and by using a mirror-like thin film as the back surface electrode, crosstalk can be reduced. By accommodating the optical semiconductor elements in the housing in a highly hermetic condition, the optical semiconductor elements can be protected from an external environment.
    Type: Grant
    Filed: January 23, 2012
    Date of Patent: April 22, 2014
    Assignees: Nippon Telegraph and Telephone Corporation, NTT Electronics Corporation
    Inventors: Yoshiyuki Doi, Yoshifumi Muramoto, Takaharu Ohyama
  • Patent number: 8680642
    Abstract: A device with increased photo-sensitivity using laser treated semiconductor as detection material is disclosed. In some embodiments, the laser treated semiconductor may be placed between and an n-type and a p-type contact or two Schottky metals. The field within the p-n junction or the Schottky metal junction may aid in depleting the laser treated semiconductor section and may be capable of separating electron hole pairs. Multiple device configurations are presented, including lateral and vertical configurations.
    Type: Grant
    Filed: March 26, 2012
    Date of Patent: March 25, 2014
    Assignee: Sionyx, Inc.
    Inventors: Nathaniel J. McCaffrey, James E. Carey
  • Publication number: 20130334537
    Abstract: An electro-optically triggered power switch is disclosed utilizing a wide bandgap, high purity III-nitride semiconductor material such as BN, AN, GaN, InN and their compounds. The device is electro-optically triggered using a laser diode operating at a wavelength of 10 to 50 nanometers off the material's bandgap, and at a power level of 10 to 100 times less than that required in a conventionally triggered device. The disclosed device may be configured as a high power RF MOSFET, IGBT, FET, or HEMT that can be electro-optically controlled using photons rather than an electrical signal. Electro-optic control lowers the power losses in the semiconductor device, decreases the turn-on time, and simplifies the drive signal requirements. It also allows the power devices to be operated from the millisecond to the sub-picosecond timeframe, thus allowing the power device to be operated at RF frequencies (i.e., kilohertz to terahertz range) and at high temperatures where the bandgap changes with temperature.
    Type: Application
    Filed: June 5, 2013
    Publication date: December 19, 2013
    Applicants: The Curators of the University of Missouri, Helava Systems, Inc.
    Inventors: Heikki I. Helava, Randy D. Curry
  • Patent number: 8610289
    Abstract: A semiconductor component including a first layer (10) of a semiconductor material as a substrate, a second layer (12) running on said first layer (10), and at least two intermediate layers (14, 16) made of the materials of the first and second layers running between the first and second layer, where the first intermediate layer (16) facing the second layer (12) may contain a eutectic mixture (18) made of the materials of the first and second layers. The invention is also directed to an electroconductive contact (15, 15a, 15b) forming an electroconductive connection to the first layer and originating at or running through the second layer, as well as to a method for producing the metal-semiconductor contact.
    Type: Grant
    Filed: June 12, 2008
    Date of Patent: December 17, 2013
    Assignee: Schott Solar AG
    Inventors: Bernd Wildpanner, Hilmar Von Campe, Werner Buss
  • Patent number: 8592243
    Abstract: A method for forming a buffer layer in a dye-sensitized solar cell including a transparent electrode, a counter electrode, an electrolyte layer disposed between the electrodes, and a photocatalyst film disposed between the electrodes and near the transparent electrode, the buffer layer being disposed between the transparent electrode and photocatalyst film, the method including: forming the buffer layer by sintering a mixed solution of an alcohol solution and 0.03% to 5% by mass of metal alkoxide by laser beam irradiation after applying the mixed solution to the surface of the transparent electrode by spin coating, the transparent electrode being rotated by a rotating table.
    Type: Grant
    Filed: December 22, 2010
    Date of Patent: November 26, 2013
    Assignee: Hitachi Zosen Corporation
    Inventors: Takeshi Sugiyo, Tetsuya Inoue
  • Patent number: 8592935
    Abstract: A UV detector is designed to provide a photoresponse with a cutoff wavelength below a predetermined wavelength. The detector uses a sensor element having an active layer comprising a MgS component grown directly on a substrate. A thin layer metal layer is deposited over the active layer and forms a transparent Schottky metal layer.
    Type: Grant
    Filed: June 5, 2012
    Date of Patent: November 26, 2013
    Assignees: The Hong Kong University of Science and Technology, University of Macau
    Inventors: Iam Keong Sou, Ying Hoi Lai, Shu Kin Lok, Wai Yip Cheung, George Ke Lun Wong, Kam Weng Tam, Sut Kam Ho
  • Patent number: 8575727
    Abstract: A semiconductor device is provided. The device includes a semiconductor substrate, first and second projections extending upwardly from the substrate, the projections having respective first and second channel regions therein, and a first gate structure engaging the first projection adjacent the first channel region. The first gate structure includes a first dielectric material over the first channel region, a first opening over the first dielectric material and the first channel region, and a pure first metal with an n-type work function value conformally deposited in the first opening. The device also includes a second gate structure engaging the second projection adjacent the second channel region. The second gate structure includes a second dielectric material over the second channel region, a second opening over the second dielectric material and the second channel region, and a pure second metal with a p-type work function value conformally deposited in the second opening.
    Type: Grant
    Filed: May 2, 2013
    Date of Patent: November 5, 2013
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Peng-Soon Lim, Chia-Pin Lin, Kuang-Yuan Hsu
  • Patent number: 8445915
    Abstract: An organic light-emitting display device includes a thin film transistor (TFT) including an active layer, a gate electrode comprising a first electrode and a second electrode, a source electrode, and a drain electrode, a photoresist layer on the source electrode and the drain electrode, a pixel electrode electrically coupled to the TFT, comprising a same material as the first electrode, and at a same layer as the first electrode, a pixel defining layer having a hole exposing the pixel electrode, the pixel defining layer covering the photoresist layer, an intermediate layer on the pixel electrode and comprising a light-emitting layer, and an opposite electrode covering the intermediate layer and facing the pixel electrode.
    Type: Grant
    Filed: September 21, 2011
    Date of Patent: May 21, 2013
    Assignee: Samsung Display Co., Ltd.
    Inventor: Chun-Gi You
  • Patent number: 8441107
    Abstract: An apparatus includes a first device. The first device includes a first projection and a first gate structure, the first projection extending upwardly from a substrate and having a first channel region therein, and the first gate structure engaging the first projection adjacent the first channel region. The first structure includes an opening over the first channel region, and a conformal, pure metal with a low resistivity disposed in the opening. The apparatus also includes a second device that includes a second projection and a second gate structure, the second projection extending upwardly from the substrate and having a second channel region therein, and the second gate structure engaging the second projection adjacent the second channel region. The second structure includes a silicide disposed over the second channel region, wherein the silicide includes a metal that is the same metal disposed in the opening.
    Type: Grant
    Filed: August 30, 2012
    Date of Patent: May 14, 2013
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Peng-Soon Lim, Chia-Pin Lin, Kuang-Yuan Hsu
  • Patent number: 8410563
    Abstract: Electrical energy generation apparatuses, in which a solar battery device and a piezoelectric device are combined in a single body by using a plurality of nano wires formed of a semiconductor material having piezoelectric properties.
    Type: Grant
    Filed: August 30, 2012
    Date of Patent: April 2, 2013
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Young-jun Park, Seung-nam Cha
  • Patent number: 8399948
    Abstract: Disclosed are a light emitting device and a light emitting device package having the same. The light emitting device includes a first conductive type semiconductor layer; an active layer including a barrier layer and a well layer alternately disposed on the first conductive type semiconductor layer; and a second conductive type semiconductor layer on the active layer. At least one well layer includes an indium cluster having a density of 1E11/cm2 or more.
    Type: Grant
    Filed: November 12, 2010
    Date of Patent: March 19, 2013
    Assignee: LG Innotek Co., Ltd.
    Inventors: Ho Sang Yoon, Sang Kyun Shim
  • Patent number: 8389996
    Abstract: A method for forming a SnO-containing semiconductor film includes a first step of forming a SnO-containing film; a second step of forming an insulator film composed of an oxide or a nitride on the SnO-containing film to provide a laminated film including the SnO-containing film and the insulator film; and a third step of subjecting the laminated film to a heat treatment.
    Type: Grant
    Filed: March 1, 2010
    Date of Patent: March 5, 2013
    Assignee: Canon Kabushiki Kaisha
    Inventors: Hisato Yabuta, Nobuyuki Kaji, Ryo Hayashi
  • Patent number: 8384179
    Abstract: A black silicon based metal-semiconductor-metal photodetector includes a silicon substrate and a black silicon layer formed on the silicon substrate. An interdigitated electrode pattern structure is formed on the black silicon layer, which can be a planar or U-shaped structure. A thin potential barrier layer is deposited at the interdigitated electrode pattern structure. An Al or transparent conductive ITO thin film is deposited on the thin potential barrier layer. A passivation layer is provided on the black silicon layer. In the black silicon based metal-semiconductor-metal photodetector, the black silicon layer, as a light-sensitive area, can respond to ultraviolet, visible and near infrared light.
    Type: Grant
    Filed: July 13, 2010
    Date of Patent: February 26, 2013
    Assignee: University of Electronic Science and Technology of China
    Inventors: Yadong Jiang, Jing Jiang, Anyuan Zhang, Zhengyu Guo, Guodong Zhao, Zhiming Wu, Wei Li
  • Patent number: 8372738
    Abstract: This invention discloses a gallium nitride based semiconductor power device disposed in a semiconductor substrate. The power device comprises a termination area disposed at a peripheral area of the semiconductor power device comprises a termination structure having at least a guard ring disposed in a trench filled with doped gallium-based epitaxial layer therein.
    Type: Grant
    Filed: October 30, 2009
    Date of Patent: February 12, 2013
    Assignee: Alpha & Omega Semiconductor, Inc.
    Inventor: Tinggang Zhu
  • Publication number: 20130026382
    Abstract: A photovoltaic UV detector configured to generate an electrical output under UV irradiation. The photovoltaic UV detector comprises a first layer comprising an electrically polarized dielectric thin layer configured to generate a first electrical output under the UV irradiation; and a second, layer configured to form an electrical energy barrier at an interface between the second layer and the first layer so as to generate a second electrical output under the UV irradiation, the second electrical output having a same polarity as the first electrical output, the electrical output of the photovoltaic UV detector being a sum of at least the first electrical output and the second electrical output. The electrically polarized dielectric thin layer may be a ferroelectric thin film, which may comprise PZT or PZLT. The second layer may be a metal and the electrical energy barrier may be a Schottky barrier.
    Type: Application
    Filed: April 12, 2011
    Publication date: January 31, 2013
    Inventors: Kui Yao, Bee Keen Gan, Szu Cheng Lai
  • Patent number: 8344398
    Abstract: A method of making a diode begins by depositing an AlxGa1-xN nucleation layer on a SiC substrate, then depositing an n+ GaN buffer layer, an n? GaN layer, an AlxGa1-xN barrier layer, and an SiO2 dielectric layer. A portion of the dielectric layer is removed and a Schottky metal deposited in the void. The dielectric layer is affixed to the support layer with a metal bonding layer using an Au—Sn utectic wafer bonding process, the substrate is removed using reactive ion etching to expose the n+ layer, selected portions of the n+, n?, and barrier layers are removed to form a mesa diode structure on the dielectric layer over the Schottky metal, and an ohmic contact is deposited on the n+ layer.
    Type: Grant
    Filed: October 15, 2010
    Date of Patent: January 1, 2013
    Assignee: Cree, Inc.
    Inventors: Primit Parikh, Sten Heikman
  • Publication number: 20120306042
    Abstract: A UV detector is designed to provide a photoresponse with a cutoff wavelength below a predetermined wavelength. The detector uses a sensor element having an active layer comprising a MgS component grown directly on a substrate. A thin layer metal layer is deposited over the active layer and forms a transparent Schottky metal layer.
    Type: Application
    Filed: June 5, 2012
    Publication date: December 6, 2012
    Applicant: THE HONG KONG UNIVERSITY OF SCIENCE AND TECHNOLOGY
    Inventors: Iam Keong SOU, Ying Hoi LAI, Shu Kin LOK, Wai Yip CHEUNG, George Ke Lun WONG, Kam Weng TAM, Sut Kam HO
  • Patent number: 8319236
    Abstract: A metallization on a semiconductor substrate is disclosed in the form of a laminate comprising a plurality of layers of a “conducting” metallization for providing electrical conductivity, interspersed with a plurality of layers of another metallization. By providing many layers the thickness of each individual layer can be reduced. Reduction in thickness of each layer leads to a reduction in grain size and a consequent reduction in creep over the lifetime of a device.
    Type: Grant
    Filed: February 8, 2008
    Date of Patent: November 27, 2012
    Assignee: Oclaro Technology Limited
    Inventors: Richard Beanland, Stephen Jones, Ian Juland
  • Patent number: 8283739
    Abstract: Electrical energy generation apparatuses, in which a solar battery device and a piezoelectric device are combined in a single body by using a plurality of nano wires formed of a semiconductor material having piezoelectric properties.
    Type: Grant
    Filed: February 17, 2010
    Date of Patent: October 9, 2012
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Young-jun Park, Seung-nam Cha
  • Patent number: 8187924
    Abstract: A design method for a semiconductor integrated circuit, includes: a first calculating step; a second calculating step; and a setting step. The first step is a step of calculating a consumption current amount of a layout target circuit based on circuit information. The second calculating step is a step of calculating a suppliable current amount per unit area in a region where a power can be supplied from a power wiring line. The setting step is a step of setting a cell size of the layout target circuit based on the consumption current amount so that a consumption current amount per unit area of the layout target circuit is smaller than the suppliable current amount per unit area.
    Type: Grant
    Filed: June 29, 2010
    Date of Patent: May 29, 2012
    Assignee: Renesas Electronics Corporation
    Inventors: Yohei Nakajima, Makoto Nonaka
  • Patent number: 8173246
    Abstract: The transparent conductive laminate of the present invention is a transparent conductive laminate, comprising: a transparent film substrate; a transparent conductive thin film provided on one side of the transparent film substrate with a dielectric thin film interposed therebetween; and a transparent substrate bonded to another side of the transparent film substrate with a transparent pressure-sensitive adhesive layer interposed therebetween, wherein the transparent substrate comprises at least two transparent base films laminated with the transparent pressure-sensitive adhesive layer interposed therebetween, and the dielectric thin film comprises a first transparent dielectric thin film consisting of a SiOx (x is from 1.5 to less than 2) film having a relative refractive index of 1.6 to 1.9, and a second transparent dielectric thin film consisting of a SiO2 film. This feature can improve the surface contact pressure durability.
    Type: Grant
    Filed: May 20, 2011
    Date of Patent: May 8, 2012
    Assignee: Nitto Denko Corporation
    Inventors: Tomotake Nashiki, Hideo Sugawara, Hidetoshi Yoshitake
  • Patent number: 8164124
    Abstract: The present disclosure provides an image sensor semiconductor device. The semiconductor device includes a semiconductor substrate; a first epitaxy semiconductor layer disposed on the semiconductor substrate and having a first type of dopant and a first doping concentration; a second epitaxy semiconductor layer disposed over the first epitaxy semiconductor layer and having the first type of dopant and a second doping concentration less than the first doping concentration; and an image sensor on the second epitaxy semiconductor layer.
    Type: Grant
    Filed: May 22, 2007
    Date of Patent: April 24, 2012
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jen-Cheng Liu, Dun-Nian Yaung, Jyh-Ming Hung, Wen-De Wang, Chun-Chieh Chuang
  • Patent number: 8154073
    Abstract: A semiconductor device includes: a semiconductor substrate; a vertical type trench gate MOS transistor; a Schottky barrier diode; multiple trenches having a stripe pattern to divide an inner region into first and second separation regions; and a poly silicon film in each trench. The first separation region includes a first conductive type region for providing a source and a second conductive type layer for providing a channel region. The first conductive type region is adjacent to a first trench. The poly silicon film in the first trench is coupled with a gate wiring. A second trench is not adjacent to the first conductive type region. The poly silicon film in the second trench is coupled with a source or gate wiring. The substrate in the second separation region is coupled with the source wiring for providing a Schottky barrier.
    Type: Grant
    Filed: July 12, 2007
    Date of Patent: April 10, 2012
    Assignee: DENSO CORPORATION
    Inventors: Takaaki Aoki, Tetsuo Fujii, Tomofusa Shiga
  • Patent number: 8148796
    Abstract: Disclosed are a solar cell and a manufacturing method thereof. The solar cell in accordance with an embodiment of the present invention includes: a substrate having a plurality of holes formed on one surface thereof; a metal layer formed on an inner wall of the hole and on one surface of the substrate; a p-type semiconductor coated on the metal layer; an n-type semiconductor formed inside the hole and on one surface of the substrate; a transparent conductive oxide formed on the n-type semiconductor; and an electrode terminal formed on the p-type semiconductor and on the transparent conductive oxide.
    Type: Grant
    Filed: May 28, 2009
    Date of Patent: April 3, 2012
    Assignee: Samsung Electro-Mechanics Co., Ltd.
    Inventors: Ro-Woon Lee, Jae-Woo Joung, Shang-Hoon Seo, Tae-Gu Kim
  • Patent number: 8143688
    Abstract: A device with increased photo-sensitivity using laser treated semiconductor as detection material is disclosed. In some embodiments, the laser treated semiconductor may be placed between and an n-type and a p-type contact or two Schottky metals. The field within the p-n junction or the Schottky metal junction may aid in depleting the laser treated semiconductor section and may be capable of separating electron hole pairs. Multiple device configurations are presented, including lateral and vertical configurations.
    Type: Grant
    Filed: May 18, 2010
    Date of Patent: March 27, 2012
    Assignee: SiOnys, Inc.
    Inventors: Nathaniel J. McCaffrey, James E. Carey
  • Publication number: 20120012967
    Abstract: A black silicon based metal-semiconductor-metal photodetector includes a silicon substrate and a black silicon layer formed on the silicon substrate. An interdigitated electrode pattern structure is formed on the black silicon layer, which can be a planar or U-shaped structure. A thin potential barrier layer is deposited at the interdigitated electrode pattern structure. An Al or transparent conductive ITO thin film is deposited on the thin potential barrier layer. A passivation layer is provided on the black silicon layer. In the black silicon based metal-semiconductor-metal photodetector, the black silicon layer, as a light-sensitive area, can respond to ultraviolet, visible and near infrared light.
    Type: Application
    Filed: July 13, 2010
    Publication date: January 19, 2012
    Inventors: Yadong Jiang, Guodong Zhao, Zhiming Wu, Wei Li, Jing Jiang, Anyuan Zhang, Zhengyu Guo
  • Patent number: 8048512
    Abstract: The transparent conductive laminate of the present invention is a transparent conductive laminate, comprising: a transparent film substrate; a transparent conductive thin film provided on one side of the transparent film substrate with a dielectric thin film interposed therebetween; and a transparent substrate bonded to another side of the transparent film substrate with a transparent pressure-sensitive adhesive layer interposed therebetween, wherein the transparent substrate comprises at least two transparent base films laminated with the transparent pressure-sensitive adhesive layer interposed therebetween, and the dielectric thin film comprises a first transparent dielectric thin film consisting of a SiOx (x is from 1.5 to less than 2) film having a relative refractive index of 1.6 to 1.9, and a second transparent dielectric thin film consisting of a SiO2 film. This feature can improve the surface contact pressure durability.
    Type: Grant
    Filed: June 7, 2007
    Date of Patent: November 1, 2011
    Assignee: Nitto Denko Corporation
    Inventors: Tomotake Nashiki, Hideo Sugawara, Hidetoshi Yoshitake
  • Publication number: 20110233382
    Abstract: The inventors disclose a new high performance optical sensor, preferably of nanoscale dimensions, that functions at room temperature based on an extraordinary optoconductance (EOC) phenomenon, and preferably an inverse EOC (I-EOC) phenomenon, in a metal-semiconductor hybrid (MSH) structure having a semiconductor/metal interface. Such a design shows efficient photon sensing not exhibited by bare semiconductors. In experimentation with an exemplary embodiment, ultrahigh spatial resolution 4-point optoconductance measurements using Helium-Neon laser radiation reveal a strikingly large optoconductance property, an observed maximum measurement of 9460% EOC, for a 250 nm device. Such an exemplary EOC device also demonstrates specific detectivity higher than 5.06×1011 cm?Hz/W for 632 nm illumination and a high dynamic response of 40 dB making such sensors technologically competitive for a wide range of practical applications.
    Type: Application
    Filed: January 7, 2011
    Publication date: September 29, 2011
    Inventors: Stuart A. Solin, Samuel A. Wickline, AKM Shah Newaz, Kirk D. Wallace
  • Patent number: 8022494
    Abstract: A lateral photodiode, with improved response speed, includes a semiconductor substrate having active regions, and a p-type region and an n-type region arranged parallel to the surface of the substrate. The active regions are an n-layer and a p-layer respectively, and stacked in the thickness direction of the substrate to form a p-n junction. In addition, a barrier layer, for preventing movement of carriers from the substrate toward the active region, is provided on the side of the active regions toward the substrate.
    Type: Grant
    Filed: January 31, 2007
    Date of Patent: September 20, 2011
    Assignees: FUJIFILM Corporation, Massachusetts Institute of Technology
    Inventors: Yukiya Miyachi, Wojciech P. Giziewicz, Jurgen Michel, Lionel C. Kimerling
  • Patent number: 8003200
    Abstract: A transparent electrically-conductive film of the present invention comprises a transparent film substrate, a hard coat layer formed on one side of the transparent film substrate, a SiOx layer with a thickness of 10 nm to 300 nm that is formed on the hard coat layer by a dry process, and a transparent electrically-conductive thin layer with a thickness of 20 nm to 35 nm that is formed on another side of the transparent film substrate. The transparent electrically-conductive film has good resistance to moisture and heat and high durability against pen-based input and can be prevented from cracking during a punching process and also prevented from waving or curling even in a high-temperature, high-humidity environment.
    Type: Grant
    Filed: September 27, 2005
    Date of Patent: August 23, 2011
    Assignee: Nitto Denko Corporation
    Inventors: Tomotake Nashiki, Hideo Sugawara, Hidehiko Andou, Hidetoshi Yoshitake