Pin Detector, Including Combinations With Non-light Responsive Active Devices Patents (Class 257/458)
  • Patent number: 10529753
    Abstract: A photodiode has an absorption layer and a cap layer operatively connected to the absorption layer. A pixel is formed in the cap layer and extends into the absorption layer to receive charge generated from photons therefrom. The pixel defines an annular diffused area to reduce dark current and capacitance. A photodetector includes the photodiode. The photodiode includes an array of pixels formed in the cap layer. At least one of the pixels extends into the absorption layer to receive charge generated from photons therefrom. At least one of the pixels defines an annular diffused area to reduce dark current and capacitance.
    Type: Grant
    Filed: November 3, 2015
    Date of Patent: January 7, 2020
    Assignee: Sensors Unlimited, Inc.
    Inventors: Prabhu Mushini, Wei Huang
  • Patent number: 10510916
    Abstract: A component for detecting UV radiation and a method for producing a component are disclosed. In an embodiment a component includes a semiconductor body including a first semiconductor layer, a second semiconductor layer and an intermediate active layer located therebetween, wherein the semiconductor body is based on AlmGa1-n-mInnN with 0?n?1, 0?m?1 and n+m<1, wherein the first semiconductor layer is n-doped, wherein the second semiconductor layer is p-doped, wherein the active layer is formed with respect to its material composition in such a way that during operation of the component, arriving ultraviolet radiation is absorbed by the active layer for generating charge carrier pairs, wherein the active layer is relaxed with respect to its lattice constant, and wherein the first semiconductor layer is strained with respect to its lattice constant.
    Type: Grant
    Filed: May 26, 2017
    Date of Patent: December 17, 2019
    Assignee: OSRAM OPTO SEMICONDUCTORS GMBH
    Inventors: Mohammad Tollabi Mazraehno, Peter Stauß, Alvaro Gomez-Iglesias
  • Patent number: 10396066
    Abstract: The present application discloses an electro-static discharge (ESD) transistor array apparatus, and relates to the field of semiconductor technologies.
    Type: Grant
    Filed: May 15, 2018
    Date of Patent: August 27, 2019
    Assignees: SEMICONDUCTOR MFG. INTL. (SHANGHAI) CORP., SEMICONDUCTOR MFG. INTL. (BEIJING) CORP.
    Inventor: JunHong Feng
  • Patent number: 10374107
    Abstract: An optical waveguide integrated light receiving element includes an optical waveguide (105) arranged on a side of a second contact layer (102) opposite to a side where a light absorption layer (103) is arranged, having a waveguide direction parallel to a plane of the light absorption layer (103), and optically coupled with the second contact layer (102). The second contact layer (102) has, in a planar view, a size of an area smaller than that of the light absorption layer (103) and arranged inside the light absorption layer (103).
    Type: Grant
    Filed: April 14, 2017
    Date of Patent: August 6, 2019
    Assignee: NIPPON TELEGRAPH AND TELEPHONE CORPORATION
    Inventors: Masahiro Nada, Yoshifumi Muramoto, Hideaki Matsuzaki
  • Patent number: 10366842
    Abstract: A dye-sensitized solar cell formed by layering a conductive layer; a photoelectric conversion layer in which a dye is adsorbed in a porous semiconductor layer and the layer is filled with a carrier transporting material; and a counter electrode including only a counter electrode conductive layer or including a catalyst layer and a counter electrode conductive layer on a support made of a light transmitting material, in which the photoelectric conversion layer is brought into contact with the counter electrode; the porous semiconductor layer forming the photoelectric conversion layer has two or more layers with different light scattering properties; and the two or more porous semiconductor layers are layered in an order of from a layer with lower light scattering property to a layer with higher light scattering property from a light receiving face side of the dye-sensitized solar cell.
    Type: Grant
    Filed: July 13, 2016
    Date of Patent: July 30, 2019
    Assignee: SHARP KABUSHIKI KAISHA
    Inventors: Ryohsuke Yamanaka, Nobuhiro Fuke, Atsushi Fukui
  • Patent number: 10367055
    Abstract: The disclosure relates to an epitaxial structure. The epitaxial structure includes a substrate, an epitaxial layer, and a nanotube film. The substrate has an epitaxial growth surface. The epitaxial layer is located on the epitaxial growth surface of the substrate. The nanotube film is located between the substrate and the epitaxial layer. The nanotube film includes a number of nanotubes orderly arranged and combined with each other by ionic bonds.
    Type: Grant
    Filed: December 9, 2014
    Date of Patent: July 30, 2019
    Assignees: Tsinghua University, HON HAI PRECISION INDUSTRY CO., LTD.
    Inventors: Yang Wei, Shou-Shan Fan
  • Patent number: 10326048
    Abstract: A semiconductor device comprises a layer sequence formed by a plurality of polar single crystalline semiconductor material layers that each has a crystal axis pointing in a direction of crystalline polarity and a stacking direction of the layer sequence. A core layer sequence is formed by an active region made of an active layer stack or a plurality of repetitions of the active layer stack. The active layer stack has an active layer having a first material composition associated with a first band gap energy, and carrier-confinement layers embedding the active layer on at least two opposite sides thereof, having a second material composition associated with a second band gap energy larger than the first band gap energy. A pair of polarization guard layers is arranged adjacent to the active region and embedding the active region on opposite sides thereof.
    Type: Grant
    Filed: March 2, 2018
    Date of Patent: June 18, 2019
    Assignee: TECHNISCHE UNIVERSITAT BERLIN
    Inventors: Gerald Pahn, Gordon Callsen, Steffen Westerkamp
  • Patent number: 10283654
    Abstract: A method of manufacturing a CIGS-based solar cell including a transparent rear electrode, the method comprising forming a rear electrode layer including a transparent oxide material; forming rear electrode patterns including a metal material on the rear electrode layer; forming a CIGS-based light absorption layer on the rear electrode layer on which the rear electrode patterns are formed; forming a buffer layer on the light absorption layer; and forming a front electrode including a transparent material on the buffer layer, wherein the rear electrode patterns are provided with a transmissive portion, through which light is transmitted, formed between patterns of the metal material.
    Type: Grant
    Filed: November 29, 2016
    Date of Patent: May 7, 2019
    Assignee: KOREA INSTITUTE OF ENERGY RESEARCH
    Inventors: Kihwan Kim, Jae-ho Yun, Jihye Gwak, Seung-kyu Ahn, Jun-Sik Cho, Joo-hyung Park, Young-Joo Eo, Jin-su Yoo, Se-jin Ahn, Ara Cho
  • Patent number: 10217898
    Abstract: A semiconductor device comprises a layer sequence formed by a plurality of polar single crystalline semiconductor material layers that each have a crystal axis pointing in a direction of crystalline polarity and a stacking direction of the layer sequence. A core layer sequence is formed by an active region made of an active layer stack or a plurality of repetitions of the active layer stack. The active layer stack has an active layer having a first material composition associated with a first band gap energy, and carrier-confinement layers embedding the active layer on at least two opposite sides thereof, having a second material composition associated with a second band gap energy larger than the first band gap energy. A pair of polarization guard layers is arranged adjacent to the active region and embedding the active region on opposite sides thereof. Both polarization guard layers have the first material composition.
    Type: Grant
    Filed: September 9, 2016
    Date of Patent: February 26, 2019
    Assignee: TECHNISCHE UNIVERSITÄT BERLIN
    Inventors: Gerald Pahn, Gordon Callsen, Axel Hoffmann
  • Patent number: 10199524
    Abstract: Photovoltaic devices such as solar cells having one or more field-effect hole or electron inversion/accumulation layers as contact regions are configured such that the electric field required for charge inversion and/or accumulation is provided by the output voltage of the photovoltaic device or that of an integrated solar cell unit. In some embodiments, a power source may be connected between a gate electrode and a contact region on the opposite side of photovoltaic device. In other embodiments, the photovoltaic device or integrated unit is self-powering.
    Type: Grant
    Filed: January 13, 2012
    Date of Patent: February 5, 2019
    Assignee: International Business Machines Corporation
    Inventors: Bahman Hekmatshoartabari, Devendra K. Sadana, Wilfried E. Haensch, Ghavam G. Shahidi, Davood Shahrjerdi
  • Patent number: 10170641
    Abstract: A vertical positive-intrinsic-negative (pin) diode includes a semiconductor substrate in which a P-type region, an intrinsic region, and an N-type region are sequentially disposed in a vertical direction to be formed therein, a first electrode formed on one surface of the semiconductor substrate to be in electrical contact with the P-type region, and a second electrode formed on the other surface of the semiconductor substrate to be in electrical contact with the N-type region, wherein the P-type region and the N-type region are respectively disposed in an upper portion and a lower portion of the semiconductor substrate to be opposite to each other.
    Type: Grant
    Filed: February 14, 2017
    Date of Patent: January 1, 2019
    Assignee: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE
    Inventors: Chulho Kim, Dong Seung Kwon, Bonghyuk Park, Young-Kyun Cho
  • Patent number: 10103280
    Abstract: Photodetector including: a waveguide of a waveguide material extending over a substrate; an insulating layer formed over the waveguide and having an opening exposing the waveguide; a photodetector layer formed over the insulating layer and into the opening so as to make contact with the waveguide, the photodetector layer having a first end at the opening and a second end distal from the opening, the photodetector layer being a gradient material of the waveguide material and germanium wherein a waveguide material portion of the gradient material varies from a maximum at the first end to a minimum at the second end and wherein a germanium portion of the gradient material varies from a minimum at the first end to a maximum at the second end; a photodetector region at the second end; and a photodetector layer extension extending at an angle from the photodetector layer at the second end.
    Type: Grant
    Filed: April 13, 2017
    Date of Patent: October 16, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: John J. Ellis-Monaghan, Edward W. Kiewra, Jason S. Orcutt
  • Patent number: 10032814
    Abstract: An image sensor array is disclosed. The image sensor array includes: a semiconductor substrate; a lateral photo detector structure over the semiconductor substrate, wherein the lateral photo detector structure has a dislocation trapping region protruding to the semiconductor substrate; and an insulating layer disposed over the lateral photo detector structure and further extending to a space between the lateral photo detector structure and the semiconductor substrate; wherein the lateral photo detector structure includes a first type region and a second type region having a polarity opposite to a polarity of the first type region, and the first type region extends at least along a portion of a boundary between an upside of the intrinsic region and the insulating layer. An associated manufacturing method is also disclosed.
    Type: Grant
    Filed: November 18, 2016
    Date of Patent: July 24, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventor: Yuichiro Yamashita
  • Patent number: 9929725
    Abstract: Van der Waals heterojunctions are extended to semiconducting p-type single-walled carbon nanotube (s-SWCNT) and n-type film that can be solution-processed with high spatial uniformity at the wafer scale. The resulting large-area, low-voltage p-n heterojunctions can exhibit anti-ambipolar transfer characteristics with high on/off ratios. The charge transport can be efficiently utilized in analog circuits such as frequency doublers and keying circuits that are widely used, for example, in telecommunication and wireless data transmission technologies.
    Type: Grant
    Filed: December 28, 2015
    Date of Patent: March 27, 2018
    Assignees: Northwestern University, Regents of the University of Minnesota
    Inventors: Deep M. Jariwala, Vinod K. Sangwan, Weichao Xu, Hyungil Kim, Tobin J. Marks, Mark C. Hersam
  • Patent number: 9893171
    Abstract: A method of forming a fin field effect transistor (finFET), including forming a temporary gate structure having a sacrificial gate layer and a dummy gate layer on the sacrificial gate layer, forming a gate spacer layer on each sidewall of the temporary gate structure, forming a source/drain spacer layer on the outward-facing sidewall of each gate spacer layer, removing the dummy gate layer to expose the sacrificial gate layer, removing the sacrificial gate layer to form a plurality of recessed cavities, and forming a gate structure, where the gate structure occupies at least a portion of the plurality of recessed cavities.
    Type: Grant
    Filed: June 3, 2016
    Date of Patent: February 13, 2018
    Assignee: International Business Machines Corporation
    Inventors: Veeraraghavan S. Basker, Zuoguang Liu, Tenko Yamashita, Chun-Chen Yeh
  • Patent number: 9887307
    Abstract: Diode barrier infrared detector devices and superlattice barrier structures are disclosed. In one embodiment, a diode barrier infrared detector device includes a first contact layer, an absorber layer adjacent to the first contact layer, and a barrier layer adjacent to the absorber layer, and a second contact layer adjacent to the barrier layer. The barrier layer includes a diode structure formed by a p-n junction formed within the barrier layer. The barrier layer may be such that there is substantially no barrier to minority carrier holes. In another embodiment, a diode barrier infrared detector device includes a first contact layer, an absorber layer adjacent to the first contact layer, a barrier layer adjacent to the absorber layer, and a diode structure adjacent to the barrier layer. The diode structure includes a second contact layer.
    Type: Grant
    Filed: October 26, 2016
    Date of Patent: February 6, 2018
    Assignee: L-3 COMMUNICATIONS CINCINNATI ELECTRONICS CORPORATION
    Inventor: Yajun Wei
  • Patent number: 9882037
    Abstract: A semiconductor device includes a middle field stop layer having a first conductivity type impurity concentration higher than a drift layer and arranged at a position in the drift layer. A ratio of a depth of the position of the middle field stop layer from a front surface of a semiconductor substrate to a thickness of the semiconductor substrate is equal to or greater than fifteen percent and equal to or less than thirty-five percent. When an IGBT is arranged in the semiconductor device, vibration of a collector voltage waveform in a switching off of the IGBT is restricted. When a diode is arranged in the semiconductor device, vibration of a recovery waveform in a recovery operation of the diode is restricted. Accordingly, at least one of the vibrations of the recovery waveform and the collector voltage waveform in the switching is restricted.
    Type: Grant
    Filed: January 26, 2017
    Date of Patent: January 30, 2018
    Assignee: DENSO CORPORATION
    Inventor: Kenji Kono
  • Patent number: 9825086
    Abstract: An image pickup apparatus includes a first pixel electrode connected to a pixel circuit, a second pixel electrode adjoining the first pixel electrode and connected to the pixel circuit, a photoelectric conversion film continuously covering the first and second pixel electrodes, and an opposite electrode facing the first and second pixel electrodes via the film. The film includes a recessed portion recessed toward a portion between the first and second pixel electrodes on a surface opposite to the first and second pixel electrodes. The depth of the recessed portion is greater than the first pixel electrode's thickness, and a distance from the first pixel electrode to the recessed portion is greater than a distance from the first pixel electrode to the second pixel electrode. The opposite electrode is provided continuously along the surface via the film, and the recessed portion surrounds a part of the opposite electrode.
    Type: Grant
    Filed: July 27, 2015
    Date of Patent: November 21, 2017
    Assignee: Canon Kabushiki Kaisha
    Inventors: Yuki Kawahara, Hiroaki Kobayashi
  • Patent number: 9728666
    Abstract: A semiconductor device includes a substrate, a first insulation layer formed on the substrate in a first region, a photon absorption seed layer formed on the first insulation layer in the first region and on the substrate in a second region separate from the first region, and a photon absorption layer formed on the photon absorption seed layer in the first region. The photon absorption seed layer has a particular structure that may assist in reducing dislocation density in a region that includes a photon absorption layer.
    Type: Grant
    Filed: December 27, 2013
    Date of Patent: August 8, 2017
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Bongjin Kuh, Kichul Kim, JeongMeung Kim, Joonghan Shin, Jongsung Lim, Hanmei Choi
  • Patent number: 9673757
    Abstract: Tunneling field effect transistors and fabrication methods thereof are provided, which include: obtaining a gate structure disposed over a substrate structure; and providing a source region and a drain region within the substrate structure separated by a channel region, the channel region underlying, at least partially, the gate structure, and the providing including: modifying the source region to attain a narrowed source region bandgap; and modifying the drain region to attain a narrowed drain region bandgap, the narrowed source region bandgap and the narrowed drain region bandgap facilitating quantum tunneling of charge carriers from the source region or the drain region to the channel region. Devices including digital modulation circuits with one or more tunneling field effect transistor(s) are also provided.
    Type: Grant
    Filed: January 16, 2014
    Date of Patent: June 6, 2017
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Yanxiang Liu, Min-hwa Chi
  • Patent number: 9620600
    Abstract: A semiconductor device according to an embodiment includes a semiconductor substrate having a first surface and a second surface. The semiconductor substrate includes an element region and a termination region provided around the element region. The termination region has a first semiconductor region of a first conductivity type provided at the first surface of the semiconductor substrate and a second semiconductor region of a second conductivity type provided between the first semiconductor region and the second surface. The semiconductor device further includes a first insulating film provided on the first semiconductor region, a second insulating film provided on the first semiconductor region and having a portion interposed between the first insulating films, a first electrode provided on the first surface of the element region and electrically connected to the first semiconductor region, and a second electrode provided at the second surface of the semiconductor substrate.
    Type: Grant
    Filed: September 15, 2015
    Date of Patent: April 11, 2017
    Assignee: Kabushiki kaisha Toshiba
    Inventors: Ryoichi Ohara, Takao Noda
  • Patent number: 9515210
    Abstract: Diode barrier infrared detector devices and superlattice barrier structures are disclosed. In one embodiment, a diode barrier infrared detector device includes a first contact layer, an absorber layer adjacent to the first contact layer, and a barrier layer adjacent to the absorber layer, and a second contact layer adjacent to the barrier layer. The barrier layer includes a diode structure formed by a p-n junction formed within the barrier layer. The barrier layer may be such that there is substantially no barrier to minority carrier holes. In another embodiment, a diode barrier infrared detector device includes a first contact layer, an absorber layer adjacent to the first contact layer, a barrier layer adjacent to the absorber layer, and a diode structure adjacent to the barrier layer. The diode structure includes a second contact layer.
    Type: Grant
    Filed: May 7, 2014
    Date of Patent: December 6, 2016
    Assignee: L-3 Communications Cincinnati Electronics Corporation
    Inventor: Yajun Wei
  • Patent number: 9472694
    Abstract: An up-converting electrode and a solar cell that combines the up-converting electrode are disclosed. The up-converting electrode comprises a material that up-converts light from longer wavelengths to shorter wavelengths and an electrically conductive material. The electrically conductive material increases the efficiency of the up-converting material such that more light is up-converted. The up-converting electrode can also serve as an electrical contact for the solar cell.
    Type: Grant
    Filed: March 12, 2013
    Date of Patent: October 18, 2016
    Assignee: The Board of Trustees of the Leland Stanford Junior University
    Inventors: Jennifer Anne Dionne, Alberto Salleo, Di Meng Wu
  • Patent number: 9472535
    Abstract: Tunable p-i-n diodes comprising Ge heterojunction structures are provided. Also provided are methods for making and using the tunable p-i-n diodes. Tunability is provided by adjusting the tensile strain in the p-i-n heterojunction structure, which enables the diodes to emit radiation over a range of wavelengths.
    Type: Grant
    Filed: November 8, 2013
    Date of Patent: October 18, 2016
    Assignee: Wisconsin Alumni Research Foundation
    Inventors: Max G. Lagally, José Roberto Sänchez Pérez
  • Patent number: 9402548
    Abstract: The invention relates to a radiation detector (10), in particular for detecting x-ray radiation, comprising a carrier substrate (11), a detector layer (12) which comprises GaN, is arranged on the carrier substrate (11) and has a thickness less than 50 ?m, and contact electrodes (13) which form ohmic contacts with the detector layer (12). The invention also relates to a measurement device which is equipped with at least one such radiation detector (10).
    Type: Grant
    Filed: March 2, 2012
    Date of Patent: August 2, 2016
    Inventors: Stefan Thalhammer, Markus Hofstetter, John Howgate, Martin Stutzmann
  • Patent number: 9397248
    Abstract: A solar cell includes a first electrode; a lower light absorption layer disposed on the first electrode; an upper light absorption layer disposed on the lower light absorption layer; and an intermediate reflector layer provided between the lower light absorption layer and the upper light absorption layer, the intermediate reflector layer being comprised of copper oxide. The intermediate reflector layer includes a plurality of copper oxide layers including a lower copper oxide layer making contact with the lower light absorption layer, an upper copper oxide layer making contact with the upper light absorption layer, and an intermediate copper oxide layer provided between the lower copper oxide layer and the upper copper oxide layer. The plurality of copper oxide layers have respective oxygen amounts that gradually increase from the upper copper oxide layer to the lower copper oxide layer.
    Type: Grant
    Filed: May 30, 2014
    Date of Patent: July 19, 2016
    Assignee: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE
    Inventors: JungWook Lim, Sun Jin Yun, Seong Hyun Lee
  • Patent number: 9343644
    Abstract: Provided is a light emitting diode (LED) in which a side surface of a reflective metal layer has a predetermined angle, and occurrence of cracks in a conductive barrier layer formed on the reflective metal layer can be prevented. Also, an LED module using LEDs is disclosed. A reflection pattern electrically connected to a second semiconductor layer is partially exposed by patterning a first insulating layer. Accordingly, a first pad is formed through the partially opened first pad region. Also, a conductive reflection layer electrically connected to a first semiconductor layer forms a second pad region formed by patterning a second insulating layer. A second pad is formed on the second pad region.
    Type: Grant
    Filed: January 2, 2015
    Date of Patent: May 17, 2016
    Assignee: Seoul Viosys Co., Ltd.
    Inventors: Jong Hyeon Chae, Jong Min Jang, Won Young Roh, Dae Woong Suh, Min Woo Kang, Joon Sub Lee, Hyun A Kim
  • Patent number: 9281334
    Abstract: A device includes a device isolation region formed into a semiconductor substrate, a doped pickup region formed into the device isolation region, a dummy gate structure that includes at least one structure that partially surrounds the doped pickup region, and a via connected to the doped pickup region.
    Type: Grant
    Filed: October 22, 2014
    Date of Patent: March 8, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Min-Feng Kao, Dun-Nian Yaung, Jen-Cheng Liu, Tzu-Hsuan Hsu, Szu-Ying Chen, Wei-Cheng Hsu, Hsiao-Hui Tseng
  • Patent number: 9274164
    Abstract: A detection apparatus for light-emitting diode chips comprises a transparent chuck with the light-concentration capability, a probing device and a light-sensing device. The transparent chuck comprises a light-incident plane and a light-emitting plane. The light-incident plane is used to bear a plurality of light-emitting diode chips under detection. The probing device comprises two probe pins and a power supply. The two ends of each probe pin is electrically connected to one of the light-emitting diode chips and the power supply, respectively, to make the light-emitting diode chip emit a plurality of light beams. The light beams penetrate through the transparent chuck by emitting into the incident plane of the transparent chuck. The light-sensing device is disposed on one side of the light-emitting plane of the transparent chuck to receive the light beams which penetrate through the transparent chuck.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: March 1, 2016
    Assignee: GENESIS PHOTONICS INC.
    Inventors: Tai-Wei Wu, Tai-Cheng Tsai, Gwo-Jiun Sheu, Shou-Wen Hsu, Yun-Li Li
  • Patent number: 9276158
    Abstract: A photodiode that can provide a THz operation with a stable output. A photodiode having a pin-type semiconductor structure includes a semiconductor layer structure and n and p electrodes. The semiconductor layer structure is obtained by sequentially layering an n-type contact layer, a low concentration layer, and a p-type contact layer. The low concentration layer is obtained by layering an electron drift layer, a light absorption layer, and a hole drift layer while being abutted to the n-type contact layer. The n electrode and the p electrode are connected to the n-type contact layer and the p-type contact layer, respectively. During operation, the low concentration layer is depleted.
    Type: Grant
    Filed: October 4, 2013
    Date of Patent: March 1, 2016
    Assignee: NTT Electronics Corporation
    Inventors: Tadao Ishibashi, Hiroki Itoh, Makoto Shimizu
  • Patent number: 9153715
    Abstract: A silicon photonic photodetector structure, a method for fabricating the silicon photonic photodetector structure and a method for operating a silicon photonic photodetector device that results from the photonic photodetector structure each use a strip waveguide optically coupled with a polysilicon material photodetector layer that may be contiguous with a semiconductor material slab to which is located and formed a pair of electrical contacts separated by the polysilicon material photodetector layer. Alternatively, the pair of electrical contacts may be located and formed upon separated locations of the polysilicon photodetector layer.
    Type: Grant
    Filed: October 13, 2014
    Date of Patent: October 6, 2015
    Assignee: CORNELL UNIVERSITY
    Inventors: Michal Lipson, Kyle Preston
  • Patent number: 9136323
    Abstract: A method of fabricating a transistor includes forming a field isolation region in a substrate. After forming the field isolation region, dopant is implanted in a first region of a substrate for formation of a drift region. A drain region is formed in a second region of the substrate. The first and second regions laterally overlap to define a conduction path for the transistor. The first region does not extend laterally across the second region.
    Type: Grant
    Filed: September 15, 2014
    Date of Patent: September 15, 2015
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Hongning Yang, Daniel J. Blomberg, Xu Cheng, Xin Lin, Won Gi Min, Zhihong Zhang, Jiang-Kai Zuo
  • Patent number: 9123861
    Abstract: A solar battery includes a transparent electrode and a collector electrode in this order on the surface of a light incident surface side of a photoelectric conversion layer. The collector electrode is formed in a predetermined region on the photoelectric conversion layer and a first transparent electrode of the transparent electrode is formed only in a region right under the collector electrode in contact with the photoelectric conversion layer and the collector electrode. A second transparent electrode of the transparent electrode is formed in a region on the photoelectric conversion layer where the collector electrode is not formed and on the collector electrode in contact with the photoelectric conversion layer or the collector electrode. The carrier concentration of the first transparent electrode is higher than the carrier concentration of the second transparent electrode.
    Type: Grant
    Filed: May 7, 2012
    Date of Patent: September 1, 2015
    Assignee: Mitsubishi Electric Corporation
    Inventors: Yuki Tsuda, Hirofumi Konishi, Tsutomu Matsuura
  • Patent number: 9093284
    Abstract: A semiconductor structure includes a III-nitride substrate with a first side and a second side opposing the first side. The III-nitride substrate is characterized by a first conductivity type and a first dopant concentration. The semiconductor structure also includes a III-nitride epitaxial layer of the first conductivity type coupled to the first surface of the III-nitride substrate, and a first metallic structure electrically coupled to the second surface of the III-nitride substrate. The semiconductor structure further includes an AlGaN epitaxial layer coupled to the III-nitride epitaxial layer of the first conductivity type, and a III-nitride epitaxial structure of a second conductivity type coupled to the AlGaN epitaxial layer. The III-nitride epitaxial structure comprises at least one edge termination structure.
    Type: Grant
    Filed: July 1, 2013
    Date of Patent: July 28, 2015
    Assignee: AVOGY, INC.
    Inventors: Linda Romano, Andrew P. Edwards, Richard J. Brown, David P. Bour, Hui Nie, Isik C. Kizilyalli, Thomas R. Prunty, Mahdan Raj
  • Patent number: 9059268
    Abstract: A tunneling field effect transistor and a method for fabricating the same are provided. The tunneling field effect transistor comprises: a semiconductor substrate; a channel region formed in the semiconductor substrate, with one or more isolation structures formed in the channel region; a first buried layer and a second buried layer formed in the semiconductor substrate and located at both sides of the channel region respectively, the first buried layer being first type non-heavily-doped, and the second buried layer being second type non-heavily-doped; a source region and a drain region formed in the semiconductor substrate and located on the first buried layer and the second buried layer respectively; and a gate dielectric layer formed on the one or more isolation structures, and a gate formed on the gate dielectric layer.
    Type: Grant
    Filed: August 21, 2012
    Date of Patent: June 16, 2015
    Assignee: Tsinghua University
    Inventors: Ning Cui, Renrong Liang, Jing Wang, Jun Xu
  • Patent number: 9048371
    Abstract: Semiconductor devices and methods for fabricating semiconductor devices are provided. In one example, a method for fabricating a semiconductor device includes etching a trench into a waveguide layer in a detector region of a semiconductor substrate. An avalanche photodetector diode is formed about the trench. Forming the avalanche photodetector diode includes forming a multiplication region in the waveguide layer laterally adjacent to the trench. An absorption region is formed at least partially disposed in the trench.
    Type: Grant
    Filed: October 3, 2013
    Date of Patent: June 2, 2015
    Assignee: GLOBALFOUNDRIES SINGAPORE PTE. LTD.
    Inventors: Kah-Wee Ang, Purakh Raj Verma
  • Patent number: 9035336
    Abstract: A semiconductor device has an active layer, a first semiconductor layer of first conductive type, an overflow prevention layer disposed between the active layer and the first semiconductor layer, which is doped with impurities of first conductive type and which prevents overflow of electrons or holes, a second semiconductor layer of first conductive type disposed at least one of between the active layer and the overflow prevention layer and between the overflow prevention layer and the first semiconductor layer, and an impurity diffusion prevention layer disposed between the first semiconductor layer and the active layer, which has a band gap smaller than those of the overflow prevention layer, the first semiconductor layer and the second semiconductor layer and which prevents diffusion of impurities of first conductive type.
    Type: Grant
    Filed: March 20, 2014
    Date of Patent: May 19, 2015
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Koichi Tachibana, Chie Hongo, Hajime Nago, Shinya Nunoue
  • Patent number: 9013002
    Abstract: An iridium interfacial stack (“IrIS”) and a method for producing the same are provided. The IrIS may include ordered layers of TaSi2, platinum, iridium, and platinum, and may be placed on top of a titanium layer and a silicon carbide layer. The IrIS may prevent, reduce, or mitigate against diffusion of elements such as oxygen, platinum, and gold through at least some of its layers.
    Type: Grant
    Filed: June 27, 2012
    Date of Patent: April 21, 2015
    Assignee: The United States of America as Represented by the Administrator of National Aeronautics and Space Administration
    Inventor: David James Spry
  • Patent number: 9013021
    Abstract: Optical absorbers, solar cells comprising the absorbers, and methods for making the absorbers are disclosed. The optical absorber comprises a semiconductor layer having a bandgap of between about 1.0 eV and about 1.6 eV disposed on a substrate, wherein the semiconductor comprises two or more earth abundant elements. The bandgap of the optical absorber is graded through the thickness of the layer by partial substitution of at least one grading element from the same group in the periodic table as the at least one of the two or more earth abundant elements.
    Type: Grant
    Filed: September 23, 2013
    Date of Patent: April 21, 2015
    Assignee: Intermolecular, Inc.
    Inventors: Jeroen Van Duren, Haifan Liang
  • Patent number: 9006785
    Abstract: Semiconductor trilayer structures that are doped and strained are provided. Also provided are mechanically flexible transistors, including radiofrequency transistors, incorporating the trilayer structures and methods for fabricating the trilayer structures and transistors. The trilayer structures comprise a first layer of single-crystalline semiconductor material, a second layer of single-crystalline semiconductor material and a third layer of single-crystalline semiconductor material. In the structures, the second layer is in contact with and sandwiched between the first and third layers and the first layer is selectively doped to provide one or more doped regions in the layer.
    Type: Grant
    Filed: January 28, 2013
    Date of Patent: April 14, 2015
    Assignee: Wisconsin Alumni Research Foundation
    Inventors: Zhenqiang Ma, Jung-Hun Seo, Max G. Lagally
  • Patent number: 8987738
    Abstract: A photoelectric conversion device with improved electric characteristics is provided. The photoelectric conversion device has a structure in which a window layer is formed by a stack of a first silicon semiconductor layer and a second silicon semiconductor layer, and the second silicon semiconductor layer has high carrier concentration than the first silicon semiconductor layer and has an opening. Light irradiation is performed on the first silicon semiconductor layer through the opening without passing through the second silicon semiconductor layer; thus, light absorption loss in the window layer can be reduced.
    Type: Grant
    Filed: September 27, 2012
    Date of Patent: March 24, 2015
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Takashi Hirose, Naoto Kusumoto
  • Patent number: 8987856
    Abstract: A photodiode, a light sensor and a fabricating method thereof are disclosed. An n-type semiconductor layer and an intrinsic semiconductor layer of the photodiode respectively comprise n-type amorphous indium gallium zinc oxide (IGZO) and intrinsic IGZO. The oxygen content of the intrinsic amorphous IGZO is greater than the oxygen content of the n-type amorphous IGZO. A light sensor comprise the photodiode is also disclosed.
    Type: Grant
    Filed: March 29, 2012
    Date of Patent: March 24, 2015
    Assignee: E Ink Holdings Inc.
    Inventors: Fang-An Shu, Yao-Chou Tsai, Ted-Hong Shinn
  • Publication number: 20150069566
    Abstract: According to one embodiment, a photodiode includes a first semiconductor layer of a first conductivity type, a second semiconductor layer of a second conductivity type, a third semiconductor layer of the first conductivity type, and a film. The second semiconductor layer is provided in the first semiconductor layer. The third semiconductor layer is provided in the first semiconductor layer so as to surround the second semiconductor layer. Each of one ends of the second and third semiconductor layers is located at an upper surface of the first semiconductor layer. The first to third semiconductor layers include first to third impurity concentrations respectively. The second and third impurity concentrations are higher than the first impurity concentration. The film is provided above the third semiconductor layer, and blocks light to enter into a neighborhood of the third semiconductor layer.
    Type: Application
    Filed: January 28, 2014
    Publication date: March 12, 2015
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Yuichi Tagami, Shigeyuki Sakura
  • Patent number: 8952477
    Abstract: A photoelectric conversion element includes a first semiconductor layer that exhibits a first conductivity type and is provided in a selective area over a substrate, a second semiconductor layer that exhibits a second conductivity type and is disposed opposed to the first semiconductor layer, and a third semiconductor layer that is provided between the first and second semiconductor layers and exhibits a substantially intrinsic conductivity type. The third semiconductor layer has at least one corner part that is not in contact with the first semiconductor layer.
    Type: Grant
    Filed: August 2, 2011
    Date of Patent: February 10, 2015
    Assignee: Sony Corporation
    Inventors: Yasuhiro Yamada, Tsutomu Tanaka, Makoto Takatoku, Ryoichi Ito
  • Patent number: 8946725
    Abstract: A semiconductor structure includes a GaN substrate with a first surface and a second surface. The GaN substrate is characterized by a first conductivity type and a first dopant concentration. A first electrode is electrically coupled to the second surface of the GaN substrate. The semiconductor structure further includes a first GaN epitaxial layer of the first conductivity type coupled to the first surface of the GaN substrate and a second GaN layer of a second conductivity type coupled to the first GaN epitaxial layer. The first GaN epitaxial layer comprises a channel region. The second GaN epitaxial layer comprises a gate region and an edge termination structure. A second electrode coupled to the gate region and a third electrode coupled to the channel region are both disposed within the edge termination structure.
    Type: Grant
    Filed: February 27, 2014
    Date of Patent: February 3, 2015
    Assignee: Avogy, Inc.
    Inventors: Donald R. Disney, Hui Nie, Isik C. Kizilyalli, Richard J. Brown
  • Patent number: 8946877
    Abstract: A semiconductor package comprises: a substrate comprising a semiconductor device; a cap comprising a seal ring disposed over a surface of the cap; and a gap between the substrate and the surface of the cap. The seal ring comprises a tread comprising at least two columns.
    Type: Grant
    Filed: September 29, 2010
    Date of Patent: February 3, 2015
    Assignee: Avago Technologies General IP (Singapore) Pte. Ltd.
    Inventors: Rick Snyder, Joel Philliber
  • Patent number: 8933530
    Abstract: An image sensor includes a substrate having a front side and a back side, an insulating structure containing circuits on the front side of the substrate, contact holes extending through the substrate to the circuits, respectively, and a plurality of pads disposed on the backside of the substrate, electrically connected to the circuits along conductive paths extending through the contact holes, and located directly over the circuits, respectively. The image sensor is fabricated by a process in which a conductive layer is formed on the back side of the substrate and patterned to form the pads directly over the circuits.
    Type: Grant
    Filed: November 8, 2012
    Date of Patent: January 13, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jin-Ho Kim, Young-Hoon Park
  • Patent number: 8933529
    Abstract: Disclosed is a vertical PIN diode having: an N-type layer; a cathode contact formed on a first portion of the N-type layer defining a cathode region; an intrinsic layer formed on a second portion of the N-type layer; a portion of a P-type layer formed on a first portion of the intrinsic layer and defining an anode region; an anode contact formed on the portion of the P-type layer defining the anode region; and a protection structure formed on a second portion of the intrinsic layer to laterally protect the portion of the P-type layer defining the anode region from an etching intended to expose the first portion of the N-type layer defining the cathode region, wherein the protection structure is formed by implanting ions in a further portion of the P-type layer, which laterally surrounds the portion of the P-type layer defining the anode region.
    Type: Grant
    Filed: November 6, 2013
    Date of Patent: January 13, 2015
    Assignee: Selex Sistemi Integrati S.p.A.
    Inventors: Marco Peroni, Alessio Pantellini
  • Patent number: 8916451
    Abstract: A method for wafer transfer includes forming a spreading layer, including graphene, on a single crystalline SiC substrate. A semiconductor layer including one or more layers is formed on and is lattice matched to the crystalline SiC layer. The semiconductor layer is transferred to a handle substrate, and the spreading layer is split to remove the single crystalline SiC substrate.
    Type: Grant
    Filed: February 5, 2013
    Date of Patent: December 23, 2014
    Assignee: International Business Machines Corporation
    Inventors: Can Bayram, Jack O. Chu, Christos Dimitrakopoulos, Jeehwan Kim, Hongsik Park, Devendra K. Sadana
  • Patent number: 8912618
    Abstract: In particular embodiments, a method is described for depositing thin films, such as those used in forming a photovoltaic cell or device. In a particular embodiment, the method includes providing a substrate suitable for use in a photovoltaic device and plasma spraying one or more layers over the substrate, the grain size of the grains in each of the one or more layers being at least approximately two times greater than the thickness of the respective layer.
    Type: Grant
    Filed: February 25, 2013
    Date of Patent: December 16, 2014
    Assignee: AQT Solar, Inc.
    Inventors: Brian Josef Bartholomeusz, Michael Bartholomeusz