Pin Detector, Including Combinations With Non-light Responsive Active Devices Patents (Class 257/458)
  • Patent number: 9515210
    Abstract: Diode barrier infrared detector devices and superlattice barrier structures are disclosed. In one embodiment, a diode barrier infrared detector device includes a first contact layer, an absorber layer adjacent to the first contact layer, and a barrier layer adjacent to the absorber layer, and a second contact layer adjacent to the barrier layer. The barrier layer includes a diode structure formed by a p-n junction formed within the barrier layer. The barrier layer may be such that there is substantially no barrier to minority carrier holes. In another embodiment, a diode barrier infrared detector device includes a first contact layer, an absorber layer adjacent to the first contact layer, a barrier layer adjacent to the absorber layer, and a diode structure adjacent to the barrier layer. The diode structure includes a second contact layer.
    Type: Grant
    Filed: May 7, 2014
    Date of Patent: December 6, 2016
    Assignee: L-3 Communications Cincinnati Electronics Corporation
    Inventor: Yajun Wei
  • Patent number: 9472535
    Abstract: Tunable p-i-n diodes comprising Ge heterojunction structures are provided. Also provided are methods for making and using the tunable p-i-n diodes. Tunability is provided by adjusting the tensile strain in the p-i-n heterojunction structure, which enables the diodes to emit radiation over a range of wavelengths.
    Type: Grant
    Filed: November 8, 2013
    Date of Patent: October 18, 2016
    Assignee: Wisconsin Alumni Research Foundation
    Inventors: Max G. Lagally, José Roberto Sänchez Pérez
  • Patent number: 9472694
    Abstract: An up-converting electrode and a solar cell that combines the up-converting electrode are disclosed. The up-converting electrode comprises a material that up-converts light from longer wavelengths to shorter wavelengths and an electrically conductive material. The electrically conductive material increases the efficiency of the up-converting material such that more light is up-converted. The up-converting electrode can also serve as an electrical contact for the solar cell.
    Type: Grant
    Filed: March 12, 2013
    Date of Patent: October 18, 2016
    Assignee: The Board of Trustees of the Leland Stanford Junior University
    Inventors: Jennifer Anne Dionne, Alberto Salleo, Di Meng Wu
  • Patent number: 9402548
    Abstract: The invention relates to a radiation detector (10), in particular for detecting x-ray radiation, comprising a carrier substrate (11), a detector layer (12) which comprises GaN, is arranged on the carrier substrate (11) and has a thickness less than 50 ?m, and contact electrodes (13) which form ohmic contacts with the detector layer (12). The invention also relates to a measurement device which is equipped with at least one such radiation detector (10).
    Type: Grant
    Filed: March 2, 2012
    Date of Patent: August 2, 2016
    Inventors: Stefan Thalhammer, Markus Hofstetter, John Howgate, Martin Stutzmann
  • Patent number: 9397248
    Abstract: A solar cell includes a first electrode; a lower light absorption layer disposed on the first electrode; an upper light absorption layer disposed on the lower light absorption layer; and an intermediate reflector layer provided between the lower light absorption layer and the upper light absorption layer, the intermediate reflector layer being comprised of copper oxide. The intermediate reflector layer includes a plurality of copper oxide layers including a lower copper oxide layer making contact with the lower light absorption layer, an upper copper oxide layer making contact with the upper light absorption layer, and an intermediate copper oxide layer provided between the lower copper oxide layer and the upper copper oxide layer. The plurality of copper oxide layers have respective oxygen amounts that gradually increase from the upper copper oxide layer to the lower copper oxide layer.
    Type: Grant
    Filed: May 30, 2014
    Date of Patent: July 19, 2016
    Assignee: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE
    Inventors: JungWook Lim, Sun Jin Yun, Seong Hyun Lee
  • Patent number: 9343644
    Abstract: Provided is a light emitting diode (LED) in which a side surface of a reflective metal layer has a predetermined angle, and occurrence of cracks in a conductive barrier layer formed on the reflective metal layer can be prevented. Also, an LED module using LEDs is disclosed. A reflection pattern electrically connected to a second semiconductor layer is partially exposed by patterning a first insulating layer. Accordingly, a first pad is formed through the partially opened first pad region. Also, a conductive reflection layer electrically connected to a first semiconductor layer forms a second pad region formed by patterning a second insulating layer. A second pad is formed on the second pad region.
    Type: Grant
    Filed: January 2, 2015
    Date of Patent: May 17, 2016
    Assignee: Seoul Viosys Co., Ltd.
    Inventors: Jong Hyeon Chae, Jong Min Jang, Won Young Roh, Dae Woong Suh, Min Woo Kang, Joon Sub Lee, Hyun A Kim
  • Patent number: 9281334
    Abstract: A device includes a device isolation region formed into a semiconductor substrate, a doped pickup region formed into the device isolation region, a dummy gate structure that includes at least one structure that partially surrounds the doped pickup region, and a via connected to the doped pickup region.
    Type: Grant
    Filed: October 22, 2014
    Date of Patent: March 8, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Min-Feng Kao, Dun-Nian Yaung, Jen-Cheng Liu, Tzu-Hsuan Hsu, Szu-Ying Chen, Wei-Cheng Hsu, Hsiao-Hui Tseng
  • Patent number: 9276158
    Abstract: A photodiode that can provide a THz operation with a stable output. A photodiode having a pin-type semiconductor structure includes a semiconductor layer structure and n and p electrodes. The semiconductor layer structure is obtained by sequentially layering an n-type contact layer, a low concentration layer, and a p-type contact layer. The low concentration layer is obtained by layering an electron drift layer, a light absorption layer, and a hole drift layer while being abutted to the n-type contact layer. The n electrode and the p electrode are connected to the n-type contact layer and the p-type contact layer, respectively. During operation, the low concentration layer is depleted.
    Type: Grant
    Filed: October 4, 2013
    Date of Patent: March 1, 2016
    Assignee: NTT Electronics Corporation
    Inventors: Tadao Ishibashi, Hiroki Itoh, Makoto Shimizu
  • Patent number: 9274164
    Abstract: A detection apparatus for light-emitting diode chips comprises a transparent chuck with the light-concentration capability, a probing device and a light-sensing device. The transparent chuck comprises a light-incident plane and a light-emitting plane. The light-incident plane is used to bear a plurality of light-emitting diode chips under detection. The probing device comprises two probe pins and a power supply. The two ends of each probe pin is electrically connected to one of the light-emitting diode chips and the power supply, respectively, to make the light-emitting diode chip emit a plurality of light beams. The light beams penetrate through the transparent chuck by emitting into the incident plane of the transparent chuck. The light-sensing device is disposed on one side of the light-emitting plane of the transparent chuck to receive the light beams which penetrate through the transparent chuck.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: March 1, 2016
    Assignee: GENESIS PHOTONICS INC.
    Inventors: Tai-Wei Wu, Tai-Cheng Tsai, Gwo-Jiun Sheu, Shou-Wen Hsu, Yun-Li Li
  • Patent number: 9153715
    Abstract: A silicon photonic photodetector structure, a method for fabricating the silicon photonic photodetector structure and a method for operating a silicon photonic photodetector device that results from the photonic photodetector structure each use a strip waveguide optically coupled with a polysilicon material photodetector layer that may be contiguous with a semiconductor material slab to which is located and formed a pair of electrical contacts separated by the polysilicon material photodetector layer. Alternatively, the pair of electrical contacts may be located and formed upon separated locations of the polysilicon photodetector layer.
    Type: Grant
    Filed: October 13, 2014
    Date of Patent: October 6, 2015
    Assignee: CORNELL UNIVERSITY
    Inventors: Michal Lipson, Kyle Preston
  • Patent number: 9136323
    Abstract: A method of fabricating a transistor includes forming a field isolation region in a substrate. After forming the field isolation region, dopant is implanted in a first region of a substrate for formation of a drift region. A drain region is formed in a second region of the substrate. The first and second regions laterally overlap to define a conduction path for the transistor. The first region does not extend laterally across the second region.
    Type: Grant
    Filed: September 15, 2014
    Date of Patent: September 15, 2015
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Hongning Yang, Daniel J. Blomberg, Xu Cheng, Xin Lin, Won Gi Min, Zhihong Zhang, Jiang-Kai Zuo
  • Patent number: 9123861
    Abstract: A solar battery includes a transparent electrode and a collector electrode in this order on the surface of a light incident surface side of a photoelectric conversion layer. The collector electrode is formed in a predetermined region on the photoelectric conversion layer and a first transparent electrode of the transparent electrode is formed only in a region right under the collector electrode in contact with the photoelectric conversion layer and the collector electrode. A second transparent electrode of the transparent electrode is formed in a region on the photoelectric conversion layer where the collector electrode is not formed and on the collector electrode in contact with the photoelectric conversion layer or the collector electrode. The carrier concentration of the first transparent electrode is higher than the carrier concentration of the second transparent electrode.
    Type: Grant
    Filed: May 7, 2012
    Date of Patent: September 1, 2015
    Assignee: Mitsubishi Electric Corporation
    Inventors: Yuki Tsuda, Hirofumi Konishi, Tsutomu Matsuura
  • Patent number: 9093284
    Abstract: A semiconductor structure includes a III-nitride substrate with a first side and a second side opposing the first side. The III-nitride substrate is characterized by a first conductivity type and a first dopant concentration. The semiconductor structure also includes a III-nitride epitaxial layer of the first conductivity type coupled to the first surface of the III-nitride substrate, and a first metallic structure electrically coupled to the second surface of the III-nitride substrate. The semiconductor structure further includes an AlGaN epitaxial layer coupled to the III-nitride epitaxial layer of the first conductivity type, and a III-nitride epitaxial structure of a second conductivity type coupled to the AlGaN epitaxial layer. The III-nitride epitaxial structure comprises at least one edge termination structure.
    Type: Grant
    Filed: July 1, 2013
    Date of Patent: July 28, 2015
    Assignee: AVOGY, INC.
    Inventors: Linda Romano, Andrew P. Edwards, Richard J. Brown, David P. Bour, Hui Nie, Isik C. Kizilyalli, Thomas R. Prunty, Mahdan Raj
  • Patent number: 9059268
    Abstract: A tunneling field effect transistor and a method for fabricating the same are provided. The tunneling field effect transistor comprises: a semiconductor substrate; a channel region formed in the semiconductor substrate, with one or more isolation structures formed in the channel region; a first buried layer and a second buried layer formed in the semiconductor substrate and located at both sides of the channel region respectively, the first buried layer being first type non-heavily-doped, and the second buried layer being second type non-heavily-doped; a source region and a drain region formed in the semiconductor substrate and located on the first buried layer and the second buried layer respectively; and a gate dielectric layer formed on the one or more isolation structures, and a gate formed on the gate dielectric layer.
    Type: Grant
    Filed: August 21, 2012
    Date of Patent: June 16, 2015
    Assignee: Tsinghua University
    Inventors: Ning Cui, Renrong Liang, Jing Wang, Jun Xu
  • Patent number: 9048371
    Abstract: Semiconductor devices and methods for fabricating semiconductor devices are provided. In one example, a method for fabricating a semiconductor device includes etching a trench into a waveguide layer in a detector region of a semiconductor substrate. An avalanche photodetector diode is formed about the trench. Forming the avalanche photodetector diode includes forming a multiplication region in the waveguide layer laterally adjacent to the trench. An absorption region is formed at least partially disposed in the trench.
    Type: Grant
    Filed: October 3, 2013
    Date of Patent: June 2, 2015
    Assignee: GLOBALFOUNDRIES SINGAPORE PTE. LTD.
    Inventors: Kah-Wee Ang, Purakh Raj Verma
  • Patent number: 9035336
    Abstract: A semiconductor device has an active layer, a first semiconductor layer of first conductive type, an overflow prevention layer disposed between the active layer and the first semiconductor layer, which is doped with impurities of first conductive type and which prevents overflow of electrons or holes, a second semiconductor layer of first conductive type disposed at least one of between the active layer and the overflow prevention layer and between the overflow prevention layer and the first semiconductor layer, and an impurity diffusion prevention layer disposed between the first semiconductor layer and the active layer, which has a band gap smaller than those of the overflow prevention layer, the first semiconductor layer and the second semiconductor layer and which prevents diffusion of impurities of first conductive type.
    Type: Grant
    Filed: March 20, 2014
    Date of Patent: May 19, 2015
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Koichi Tachibana, Chie Hongo, Hajime Nago, Shinya Nunoue
  • Patent number: 9013002
    Abstract: An iridium interfacial stack (“IrIS”) and a method for producing the same are provided. The IrIS may include ordered layers of TaSi2, platinum, iridium, and platinum, and may be placed on top of a titanium layer and a silicon carbide layer. The IrIS may prevent, reduce, or mitigate against diffusion of elements such as oxygen, platinum, and gold through at least some of its layers.
    Type: Grant
    Filed: June 27, 2012
    Date of Patent: April 21, 2015
    Assignee: The United States of America as Represented by the Administrator of National Aeronautics and Space Administration
    Inventor: David James Spry
  • Patent number: 9013021
    Abstract: Optical absorbers, solar cells comprising the absorbers, and methods for making the absorbers are disclosed. The optical absorber comprises a semiconductor layer having a bandgap of between about 1.0 eV and about 1.6 eV disposed on a substrate, wherein the semiconductor comprises two or more earth abundant elements. The bandgap of the optical absorber is graded through the thickness of the layer by partial substitution of at least one grading element from the same group in the periodic table as the at least one of the two or more earth abundant elements.
    Type: Grant
    Filed: September 23, 2013
    Date of Patent: April 21, 2015
    Assignee: Intermolecular, Inc.
    Inventors: Jeroen Van Duren, Haifan Liang
  • Patent number: 9006785
    Abstract: Semiconductor trilayer structures that are doped and strained are provided. Also provided are mechanically flexible transistors, including radiofrequency transistors, incorporating the trilayer structures and methods for fabricating the trilayer structures and transistors. The trilayer structures comprise a first layer of single-crystalline semiconductor material, a second layer of single-crystalline semiconductor material and a third layer of single-crystalline semiconductor material. In the structures, the second layer is in contact with and sandwiched between the first and third layers and the first layer is selectively doped to provide one or more doped regions in the layer.
    Type: Grant
    Filed: January 28, 2013
    Date of Patent: April 14, 2015
    Assignee: Wisconsin Alumni Research Foundation
    Inventors: Zhenqiang Ma, Jung-Hun Seo, Max G. Lagally
  • Patent number: 8987738
    Abstract: A photoelectric conversion device with improved electric characteristics is provided. The photoelectric conversion device has a structure in which a window layer is formed by a stack of a first silicon semiconductor layer and a second silicon semiconductor layer, and the second silicon semiconductor layer has high carrier concentration than the first silicon semiconductor layer and has an opening. Light irradiation is performed on the first silicon semiconductor layer through the opening without passing through the second silicon semiconductor layer; thus, light absorption loss in the window layer can be reduced.
    Type: Grant
    Filed: September 27, 2012
    Date of Patent: March 24, 2015
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Takashi Hirose, Naoto Kusumoto
  • Patent number: 8987856
    Abstract: A photodiode, a light sensor and a fabricating method thereof are disclosed. An n-type semiconductor layer and an intrinsic semiconductor layer of the photodiode respectively comprise n-type amorphous indium gallium zinc oxide (IGZO) and intrinsic IGZO. The oxygen content of the intrinsic amorphous IGZO is greater than the oxygen content of the n-type amorphous IGZO. A light sensor comprise the photodiode is also disclosed.
    Type: Grant
    Filed: March 29, 2012
    Date of Patent: March 24, 2015
    Assignee: E Ink Holdings Inc.
    Inventors: Fang-An Shu, Yao-Chou Tsai, Ted-Hong Shinn
  • Publication number: 20150069566
    Abstract: According to one embodiment, a photodiode includes a first semiconductor layer of a first conductivity type, a second semiconductor layer of a second conductivity type, a third semiconductor layer of the first conductivity type, and a film. The second semiconductor layer is provided in the first semiconductor layer. The third semiconductor layer is provided in the first semiconductor layer so as to surround the second semiconductor layer. Each of one ends of the second and third semiconductor layers is located at an upper surface of the first semiconductor layer. The first to third semiconductor layers include first to third impurity concentrations respectively. The second and third impurity concentrations are higher than the first impurity concentration. The film is provided above the third semiconductor layer, and blocks light to enter into a neighborhood of the third semiconductor layer.
    Type: Application
    Filed: January 28, 2014
    Publication date: March 12, 2015
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Yuichi Tagami, Shigeyuki Sakura
  • Patent number: 8952477
    Abstract: A photoelectric conversion element includes a first semiconductor layer that exhibits a first conductivity type and is provided in a selective area over a substrate, a second semiconductor layer that exhibits a second conductivity type and is disposed opposed to the first semiconductor layer, and a third semiconductor layer that is provided between the first and second semiconductor layers and exhibits a substantially intrinsic conductivity type. The third semiconductor layer has at least one corner part that is not in contact with the first semiconductor layer.
    Type: Grant
    Filed: August 2, 2011
    Date of Patent: February 10, 2015
    Assignee: Sony Corporation
    Inventors: Yasuhiro Yamada, Tsutomu Tanaka, Makoto Takatoku, Ryoichi Ito
  • Patent number: 8946877
    Abstract: A semiconductor package comprises: a substrate comprising a semiconductor device; a cap comprising a seal ring disposed over a surface of the cap; and a gap between the substrate and the surface of the cap. The seal ring comprises a tread comprising at least two columns.
    Type: Grant
    Filed: September 29, 2010
    Date of Patent: February 3, 2015
    Assignee: Avago Technologies General IP (Singapore) Pte. Ltd.
    Inventors: Rick Snyder, Joel Philliber
  • Patent number: 8946725
    Abstract: A semiconductor structure includes a GaN substrate with a first surface and a second surface. The GaN substrate is characterized by a first conductivity type and a first dopant concentration. A first electrode is electrically coupled to the second surface of the GaN substrate. The semiconductor structure further includes a first GaN epitaxial layer of the first conductivity type coupled to the first surface of the GaN substrate and a second GaN layer of a second conductivity type coupled to the first GaN epitaxial layer. The first GaN epitaxial layer comprises a channel region. The second GaN epitaxial layer comprises a gate region and an edge termination structure. A second electrode coupled to the gate region and a third electrode coupled to the channel region are both disposed within the edge termination structure.
    Type: Grant
    Filed: February 27, 2014
    Date of Patent: February 3, 2015
    Assignee: Avogy, Inc.
    Inventors: Donald R. Disney, Hui Nie, Isik C. Kizilyalli, Richard J. Brown
  • Patent number: 8933530
    Abstract: An image sensor includes a substrate having a front side and a back side, an insulating structure containing circuits on the front side of the substrate, contact holes extending through the substrate to the circuits, respectively, and a plurality of pads disposed on the backside of the substrate, electrically connected to the circuits along conductive paths extending through the contact holes, and located directly over the circuits, respectively. The image sensor is fabricated by a process in which a conductive layer is formed on the back side of the substrate and patterned to form the pads directly over the circuits.
    Type: Grant
    Filed: November 8, 2012
    Date of Patent: January 13, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jin-Ho Kim, Young-Hoon Park
  • Patent number: 8933529
    Abstract: Disclosed is a vertical PIN diode having: an N-type layer; a cathode contact formed on a first portion of the N-type layer defining a cathode region; an intrinsic layer formed on a second portion of the N-type layer; a portion of a P-type layer formed on a first portion of the intrinsic layer and defining an anode region; an anode contact formed on the portion of the P-type layer defining the anode region; and a protection structure formed on a second portion of the intrinsic layer to laterally protect the portion of the P-type layer defining the anode region from an etching intended to expose the first portion of the N-type layer defining the cathode region, wherein the protection structure is formed by implanting ions in a further portion of the P-type layer, which laterally surrounds the portion of the P-type layer defining the anode region.
    Type: Grant
    Filed: November 6, 2013
    Date of Patent: January 13, 2015
    Assignee: Selex Sistemi Integrati S.p.A.
    Inventors: Marco Peroni, Alessio Pantellini
  • Patent number: 8916451
    Abstract: A method for wafer transfer includes forming a spreading layer, including graphene, on a single crystalline SiC substrate. A semiconductor layer including one or more layers is formed on and is lattice matched to the crystalline SiC layer. The semiconductor layer is transferred to a handle substrate, and the spreading layer is split to remove the single crystalline SiC substrate.
    Type: Grant
    Filed: February 5, 2013
    Date of Patent: December 23, 2014
    Assignee: International Business Machines Corporation
    Inventors: Can Bayram, Jack O. Chu, Christos Dimitrakopoulos, Jeehwan Kim, Hongsik Park, Devendra K. Sadana
  • Patent number: 8912618
    Abstract: In particular embodiments, a method is described for depositing thin films, such as those used in forming a photovoltaic cell or device. In a particular embodiment, the method includes providing a substrate suitable for use in a photovoltaic device and plasma spraying one or more layers over the substrate, the grain size of the grains in each of the one or more layers being at least approximately two times greater than the thickness of the respective layer.
    Type: Grant
    Filed: February 25, 2013
    Date of Patent: December 16, 2014
    Assignee: AQT Solar, Inc.
    Inventors: Brian Josef Bartholomeusz, Michael Bartholomeusz
  • Publication number: 20140361396
    Abstract: The present invention provides a hot-carrier photoelectric conversion method. The method includes a hot-carrier photoelectric conversion device having a P-type semiconductor layer, an N-type semiconductor layer, and an inorganic conducting light-absorbing layer. The inorganic conducting light-absorbing layer is formed between the P-type semiconductor layer and the N-type semiconductor layer, and an electric field is formed between the P-type semiconductor layer and the N-type semiconductor layer. Moreover, photons are absorbed by the inorganic conducting light-absorbing layer to create electrons and holes. The electrons and holes are respectively shifted by the electric field or diffusion effect to the N-type semiconductor layer and the P-type semiconductor layer, so that the electrons and the holes are respectively conducted outside to create electric energy.
    Type: Application
    Filed: February 19, 2014
    Publication date: December 11, 2014
    Applicant: National Taiwan University
    Inventors: Ching-Fuh Lin, Hsin-Yi Chen, Jiun-Jie Chao, Hong-Jhang Syu
  • Patent number: 8901697
    Abstract: An integrated circuit having an insulated conductor or within a semiconductor substrate and extending perpendicular to a plane of a semiconductor wafer or substrate on which the integrated circuit is fabricated, the conductor comprising a first region of doped semiconductor extending between a first device or a first contact and a second device or a second contact.
    Type: Grant
    Filed: March 16, 2012
    Date of Patent: December 2, 2014
    Assignee: Analog Devices, Inc.
    Inventor: Bernard Patrick Stenson
  • Patent number: 8896076
    Abstract: A photoelectric conversion element of an embodiment is a photoelectric conversion element which performs photoelectric conversion by receiving illumination light having n light emission peaks having a peak energy Ap (eV) (where 1?p?n and 2?n) of 1.59?Ap?3.26 and a full width at half maximum Fp (eV) (where 1?p?n and 2?n), wherein the photoelectric conversion element includes m photoelectric conversion layers having a band gap energy Bq (eV) (where 1?q?m and 2?m?n), and the m photoelectric conversion layers each satisfy the relationship of Ap?Fp<Bq?Ap with respect to any one of the n light emission peaks.
    Type: Grant
    Filed: July 29, 2013
    Date of Patent: November 25, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Shinji Saito, Rei Hashimoto, Mizunori Ezaki, Shinya Nunoue, Hironori Asai
  • Patent number: 8890272
    Abstract: A photodetector is provided, comprising: a radiation-absorbing semiconductor region and a collection semiconductor region separated by and each in contact with a barrier semiconductor region; wherein, at least in the absence of an applied bias voltage, the band gap between the valence band energy and the conduction band energy of the barrier semiconductor region is offset from the band gap between the valence band energy and the conduction band energy of the radiation-absorbing semiconductor region so as to form an energy barrier between the radiation-absorbing semiconductor region and the collection semiconductor region which resists the flow of minority carriers from the radiation-absorbing semiconductor region to the collection semiconductor region. Also provided is a method of manufacturing a photodetector.
    Type: Grant
    Filed: August 10, 2011
    Date of Patent: November 18, 2014
    Assignee: BAH Holdings LLC
    Inventor: Michael Tkachuk
  • Patent number: 8890271
    Abstract: Various embodiments for etching of silicon nitride (SixNy) lightpipes, waveguides and pillars, fabricating photodiode elements, and integration of the silicon nitride elements with photodiode elements are described. The results show that the quantum efficiency of the photodetectors (PDs) can be increased using vertical silicon nitride vertical waveguides.
    Type: Grant
    Filed: December 13, 2010
    Date of Patent: November 18, 2014
    Assignees: Zena Technologies, Inc., President and Fellows of Harvard College
    Inventors: Turgut Tut, Peter Duane, Young-June Yu, Winnie N. Ye, Munib Wober, Kenneth B. Crozier
  • Publication number: 20140319640
    Abstract: A photodiode structure provides light sensitivity to both front side and backside illumination. The photodiode may include a deep N well (DNW) that extends over a Psub substrate. The DNW may be discontinuous, or may extend continuously over the Psub substrate. Additional DNW area under the diode area proportionally increases the sensitivity to backside illumination. In addition, the photodiode may use a lightly doped anode region to increase the depletion region between the anode region and the deep N well. The anode region may be lightly doped Psub, as opposed to Pwell, in order to increase the topside light sensitive area percentage of the total area. One highly sensitive implementation uses Psub doping in the anode region, and a deep N well under the entire diode. This provides maximum areal density of the diode intrinsic regions nearest the wafer backside.
    Type: Application
    Filed: April 29, 2013
    Publication date: October 30, 2014
    Applicant: Broadcom Corporation
    Inventors: Donald Edward Major, Chih-Chieh Shen
  • Patent number: 8872294
    Abstract: Photonic structures and methods of formation are disclosed in which a photo detector interface having crystalline misfit dislocations is displaced with respect to a waveguide core to reduce effects of dark current on a detected optical signal.
    Type: Grant
    Filed: August 21, 2012
    Date of Patent: October 28, 2014
    Assignee: Micron Technology, Inc.
    Inventors: Roy Meade, Zvi Sternberg, Ofer Tehar-Zahav
  • Patent number: 8866247
    Abstract: Described are embodiments of apparatuses and systems including photonic devices having a conductive shunt layer, and methods for making such apparatuses and systems. A photonic device may include a device substrate, a photo-active region disposed on a first region of the device substrate, an isolation region in the device substrate, a contact disposed on a second region of the substrate such that the isolation region is located between the contact and the photo-active region, and a conductive material overlying the isolation region to shunt the first region with the second region. Other embodiments may be described and/or claimed.
    Type: Grant
    Filed: March 29, 2012
    Date of Patent: October 21, 2014
    Assignee: Intel Corporation
    Inventors: Avi Feshali, Tao Sherry Yin, Ansheng Liu
  • Patent number: 8861909
    Abstract: A silicon photonic photodetector structure, a method for fabricating the silicon photonic photodetector structure and a method for operating a silicon photonic photodetector device that results from the photonic photodetector structure each use a strip waveguide optically coupled with a polysilicon material photodetector layer that may be contiguous with a semiconductor material slab to which is located and formed a pair of electrical contacts separated by the polysilicon material photodetector layer. Within the foregoing silicon photonic photodetector structure and related methods the polysilicon material photodetector layer includes defect states suitable for absorbing an optical signal from the strip waveguide and generating an electrical output signal using at least one of the electrical contacts when the optical signal includes a photon energy less than a band gap energy of a polysilicon material from which is comprised the polysilicon material photodetector layer.
    Type: Grant
    Filed: February 16, 2012
    Date of Patent: October 14, 2014
    Assignee: Cornell University
    Inventors: Michal Lipson, Kyle Preston
  • Patent number: 8853812
    Abstract: The present invention provides a photodetector which solves the problem of low sensitivity of a photodetector, an optical communication device equipped with the same, and a method for making the photodetector, and a method for making the optical communication device. The photodetector includes a substrate, a lower cladding layer arranged on the substrate, an optical waveguide arranged on the lower cladding layer, an intermediate layer arranged on the optical waveguide, a optical absorption layer arranged on the intermediate layer, a pair of electrodes arranged on the optical absorption layer, and wherein the optical absorption layer includes a IV-group or III-V-group single-crystal semiconductor, and the optical absorption layer absorbs an optical signal propagating through the optical waveguide.
    Type: Grant
    Filed: June 15, 2011
    Date of Patent: October 7, 2014
    Assignee: NEC Corporation
    Inventors: Daisuke Okamoto, Junichi Fujikata
  • Patent number: 8852982
    Abstract: A photoelectric device is disclosed. The photoelectric device includes a semiconductor substrate, first and second semiconductor stacks having opposite conductive types and alternately arranged on a first surface of the semiconductor substrate, and a gap insulation layer formed between the first and second semiconductor stacks. An undercut may be formed in the gap insulation layer. A method of manufacturing a photoelectric device is also disclosed.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: October 7, 2014
    Assignee: Samsung SDI Co., Ltd.
    Inventors: June-Hyuk Jung, Young-Soo Kim, Sung-Chul Lee, Jae-Ho Shin, Dong-Hun Lee
  • Patent number: 8846437
    Abstract: Embodiments of the invention provide a method of forming a doped gallium arsenide based (GaAs) layer from a solution based precursor. The doped gallium arsenide based (GaAs) layer formed from the solution based precursor may assist solar cell devices to improve light absorption and conversion efficiency. In one embodiment, a method of forming a solar cell device includes forming a first layer with a first type of dopants doped therein over a surface of a substrate, forming a GaAs based layer on the first layer, and forming a second layer with a second type of dopants doped therein on the GaAs based layer.
    Type: Grant
    Filed: September 30, 2011
    Date of Patent: September 30, 2014
    Assignee: Applied Materials, Inc.
    Inventors: Kaushal K. Singh, Robert Jan Visser, Srikant Rao, Bhaskar Kumar, Claire J. Carmalt, Ranga Rao Arnepalli, Omkaram Nalamasu, Gaurav Saraf, Sanjayan Sathasivam, Christopher Stuart Blackman
  • Patent number: 8841742
    Abstract: Methods of transferring a layer of semiconductor material from a first donor structure to a second structure include forming recesses in the donor structure, implanting ions into the donor structure to form a generally planar, inhomogeneous weakened zone therein, and providing material within the recesses. The first donor structure may be bonded to a second structure, and the first donor structure may be fractured along the generally planar weakened zone, leaving the layer of semiconductor material bonded to the second structure. Semiconductor devices may be fabricated by forming active device structures on the transferred layer of semiconductor material. Semiconductor structures are fabricated using the described methods.
    Type: Grant
    Filed: February 26, 2013
    Date of Patent: September 23, 2014
    Assignee: Soitec
    Inventors: Mariam Sadaka, Ionut Radu
  • Patent number: 8841741
    Abstract: A high breakdown voltage diode of the present embodiment includes a first conductive semiconductor substrate, a drift layer formed on the first conductive semiconductor substrate and formed of a first conductive semiconductor, a buffer layer formed on the drift layer and formed of a second conductive semiconductor, a second conductive high concentration semiconductor region formed at an upper portion of the buffer layer, a mesa termination unit formed on an end region of a semiconductor apparatus to relax an electric field of the end region when reverse bias is applied between the semiconductor substrate and the buffer layer, and an electric field relaxation region formed at the mesa termination unit and formed of a second conductive semiconductor. A breakdown voltage of a high breakdown voltage diode, in which a pn junction is provided to a semiconductor layer, is increased, and a process yield is improved.
    Type: Grant
    Filed: September 7, 2011
    Date of Patent: September 23, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Masamu Kamaga, Makoto Mizukami, Takashi Shinohe
  • Publication number: 20140264708
    Abstract: Optical absorbers, solar cells comprising the absorbers, and methods for making the absorbers are disclosed. The optical absorber comprises a semiconductor layer having a bandgap of between about 1.0 eV and about 1.6 eV disposed on a substrate, wherein the semiconductor comprises two or more earth abundant elements. The bandgap of the optical absorber is graded through the thickness of the layer by partial substitution of at least one grading element from the same group in the periodic table as the at least one of the two or more earth abundant elements.
    Type: Application
    Filed: September 23, 2013
    Publication date: September 18, 2014
    Applicant: Intermolecular, Inc.
    Inventors: Jeroen Van Duren, Haifan Liang
  • Patent number: 8836070
    Abstract: A photo diode includes an intrinsic region on a substrate, a P+ doping region in a first portion of the intrinsic region, and an oxide semiconductor region. The oxide semiconductor region is spaced apart from the P+ doping region on a second portion of the intrinsic region and the second portion of the intrinsic region is different from the first portion of the intrinsic region.
    Type: Grant
    Filed: September 8, 2011
    Date of Patent: September 16, 2014
    Assignee: Samsung Display Co., Ltd.
    Inventors: Won-Kyu Lee, Jae-Beom Choi, Jae-Hwan Oh, Young-Jin Chang, Seong-Hyun Jin
  • Patent number: 8835950
    Abstract: A semiconductor device has an active layer, a first semiconductor layer of first conductive type, an overflow prevention layer disposed between the active layer and the first semiconductor layer, which is doped with impurities of first conductive type and which prevents overflow of electrons or holes, a second semiconductor layer of first conductive type disposed at least one of between the active layer and the overflow prevention layer and between the overflow prevention layer and the first semiconductor layer, and an impurity diffusion prevention layer disposed between the first semiconductor layer and the active layer, which has a band gap smaller than those of the overflow prevention layer, the first semiconductor layer and the second semiconductor layer and which prevents diffusion of impurities of first conductive type.
    Type: Grant
    Filed: February 16, 2012
    Date of Patent: September 16, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Koichi Tachibana, Chie Hongo, Hajime Nago, Shinya Nunoue
  • Patent number: 8829636
    Abstract: A solid-state image pickup device has photodiodes, each of which includes an N-type region formed in a semiconductor substrate, a first silicon carbide layer formed above the N-type region, and a P-type region including a first silicon layer formed above the first silicon carbide layer and doped with boron. A fabrication process of such a solid-state image pickup device is also disclosed.
    Type: Grant
    Filed: August 20, 2010
    Date of Patent: September 9, 2014
    Assignee: Sony Corporation
    Inventors: Tomokazu Ohchi, Yuki Miyanami, Shinichi Arakawa
  • Patent number: 8829638
    Abstract: Electrical pumping of photonic crystal (PC) nanocavities using a lateral p-i-n junction is described. Ion implantation doping can be used to form the junction, which under forward bias pumps a gallium arsenide photonic crystal nanocavity with indium arsenide quantum dots. Efficient cavity-coupled electroluminescence is demonstrated in a first experimental device. Electrically pumped lasing is demonstrated in a second experimental device. High speed modulation of a single mode LED is demonstrated in a third experimental device. This approach provides several significant advantages. Ease of fabrication is improved because difficult timed etch steps are not required. Any kind of PC design can be employed. Current flow can be lithographically controlled to focus current flow to the active region of the device, thereby improving efficiency, reducing resistance, improving speed, and reducing threshold.
    Type: Grant
    Filed: November 15, 2012
    Date of Patent: September 9, 2014
    Assignee: The Board of Trustees of the Leland Stanford Junior University
    Inventors: Gary Shambat, Bryan Ellis, Jelena Vuckovic
  • Patent number: 8828786
    Abstract: A light-absorbing layer is composed of a compound-semiconductor film of chalcopyrite structure, a surface layer is disposed on the light-absorbing layer, the surface layer having a higher band gap energy than the compound-semiconductor film, an upper electrode layer is disposed on the surface layer, and a lower electrode layer is disposed on a backside of the light-absorbing layer in opposition to the upper electrode layer, the upper electrode layer and the lower electrode layer having a reverse bias voltage applied in between to detect electric charges produced by photoelectric conversion in the compound-semiconductor film, as electric charges due to photoelectric conversion are multiplied by impact ionization, while the multiplication by impact ionization of electric charges is induced by application of a high-intensity electric field to a semiconductor of chalcopyrite structure, allowing for an improved dark-current property, and an enhanced efficiency even in detection of low illumination intensities, wit
    Type: Grant
    Filed: January 15, 2013
    Date of Patent: September 9, 2014
    Assignee: Rohm Co., Ltd.
    Inventors: Kenichi Miyazaki, Osamu Matsushima
  • Patent number: 8829566
    Abstract: A semiconductor waveguide based optical receiver is disclosed. An apparatus according to aspects of the present invention includes an absorption region including a first type of semiconductor region proximate to a second type of semiconductor region. The first type of semiconductor is to absorb light in a first range of wavelengths and the second type of semiconductor to absorb light in a second range of wavelengths. A multiplication region is defined proximate to and separate from the absorption region. The multiplication region includes an intrinsic semiconductor region in which there is an electric field to multiply the electrons created in the absorption region.
    Type: Grant
    Filed: March 15, 2007
    Date of Patent: September 9, 2014
    Assignee: Intel Corporation
    Inventors: Michael T. Morse, Olufemi I. Dosunmu, Ansheng Liu, Mario J. Paniccia