Pin Detector, Including Combinations With Non-light Responsive Active Devices Patents (Class 257/458)
  • Publication number: 20070278607
    Abstract: A shallow semiconductor sensor with a fluorescent molecule layer that eliminates optical and electronic crosstalk.
    Type: Application
    Filed: May 31, 2006
    Publication date: December 6, 2007
    Inventors: Russell W. Gruhlke, Mark D. Crook, Thomas E. Dungan
  • Patent number: 7301215
    Abstract: A photovoltaic device includes at least a first electrode, a first-conductivity-type layer composed of non-single-crystalline silicon, a second-conductivity-type layer composed of polycrystalline silicon, a third-conductivity-type layer composed of non-single-crystalline silicon, and a second electrode, wherein the contact surface of the first electrode with respect to the first-conductivity-type layer has a shape interspersed with a plurality of projections, and the lower limit and the upper limit of the density of the projections interspersed on the surface of the first electrode satisfy the following equations, provided that the thickness of the second-conductivity-type layer is t ?m: Lower limit=0.312 exp(?0.60t) pieces/?m2 Upper limit=0.387 exp(?0.39t) pieces/?m2.
    Type: Grant
    Filed: August 14, 2006
    Date of Patent: November 27, 2007
    Assignee: Canon Kabushiki Kaisha
    Inventor: Toshimitsu Kariya
  • Patent number: 7294522
    Abstract: A CMOS image sensor and a method for fabricating the same are disclosed, in which a dead zone and a dark current are simultaneously reduced by selective epitaxial growth. The CMOS image sensor includes a first conductive type semiconductor substrate, a second conductive type impurity ion area, a gate electrode, an insulating film formed on an entire surface of the semiconductor substrate including the gate electrode and excluding the second conductive type impurity ion area, and a silicon epitaxial layer formed on the second conductive type impurity ion area and doped with first conductive type impurity ions.
    Type: Grant
    Filed: December 28, 2005
    Date of Patent: November 13, 2007
    Assignee: Donogbu Electronics Co., Ltd.
    Inventor: Hee Sung Shim
  • Patent number: 7288429
    Abstract: An image sensor with a vertically integrated thin-film photodiode includes a bottom doped layer of a PIN photodiode imbedded in a dielectric layer, wherein a bottom surface of the bottom doped layer completely contacts its corresponding underlying pixel electrode. The bottom doped layers of the PIN photodiodes are formed by a self-aligned and damascene method, therefore the pixel electrodes are not exposed to the I-type amorphous silicon layer of the PIN photodiodes. Moreover, the transparent electrode connects the PIN photodiodes to an external ground voltage power through a ground pad which is a portion of a top metal layer.
    Type: Grant
    Filed: November 18, 2005
    Date of Patent: October 30, 2007
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Dun-Nian Yaung, Sou-Kuo Wu, Ho-Ching Chien
  • Patent number: 7262498
    Abstract: An assembly includes a substrate, a device coupled to the substrate; a ring formed on the substrate; and one or more bonding pads formed on the substrate, wherein the ring and bonding pads are formed of a same material.
    Type: Grant
    Filed: January 18, 2005
    Date of Patent: August 28, 2007
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: David M. Craig, Chien-Hua Chen, Charles C. Haluzak, Ronnie J. Yenchik
  • Patent number: 7259444
    Abstract: In one embodiment, an optoelectronic device is provided having a pin photo diode including a semi-insulating substrate or layer, with a patterned implant region of a first dopant type. The pin photo diode includes an upper layer having semiconductor material with a second dopant type. An intermediate layer is provided having a substantially intrinsic semiconductor material. An upper layer contact is provided having a portion with a generally circular interior facing edge. The implant region has a first portion having an outer periphery substantially nonoverlapping with the interior facing edge of the upper layer contact. The implant region includes a contact portion located beyond the upper layer contact. A connecting portion couples the first portion and the contact portion of the implant region. In one embodiment, the device includes a heterojunction bipolar transistor coupled to the pin photo diode.
    Type: Grant
    Filed: July 20, 2004
    Date of Patent: August 21, 2007
    Assignee: HRL Laboratories, LLC
    Inventors: Mary Y. Chen, Donald A. Hitko
  • Publication number: 20070176252
    Abstract: A structure and method of fabricating lateral diodes. The diodes include Schottky diodes and PIN diodes. The method of fabrication includes forming one or more doped regions and more trenches in a silicon substrate and forming metal silicides on the sidewalls of the trenches. The fabrication of lateral diodes may be integrated with the fabrication of field effect, bipolar and SiGe bipolar transistors.
    Type: Application
    Filed: January 30, 2006
    Publication date: August 2, 2007
    Inventors: Douglas Duane Coolbaugh, Jeffrey Bowman Johnson, Xuefeng Liu, Bradley Alan Orner, Robert Mark Rassel, David Charles Sheridan
  • Patent number: 7235832
    Abstract: A PIN active pixel sensor array including self aligned encapsulated electrodes and a method for forming the same the method including forming an electrically conductive layer over a substrate; forming a first doped semiconducting layer over the conductive layer; photolithographically patterning and etching through a thickness portion of the first doped semiconducting layer and conductive layer to expose the substrate to form a plurality of spaced apart electrodes having an upper portion comprising the first doped semiconducting layer; blanket depositing a second doped semiconducting layer to cover the spaced apart electrodes including the exposed substrate; and, etching through at least a thickness portion of the second doped semiconducting layer.
    Type: Grant
    Filed: February 7, 2005
    Date of Patent: June 26, 2007
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventor: Dun-Nian Yaung
  • Patent number: 7235852
    Abstract: A variable optical attenuator. A PIN structure is integrated with an optical detector such as a PIN diode or an APD diode. When the PIN structure is forward biased, the light signal is not affected and is detected by the optical detector. When the PIN structure is reverse biased, the light signal is attenuated and the dynamic range of the optical detector can be increased.
    Type: Grant
    Filed: January 22, 2004
    Date of Patent: June 26, 2007
    Assignee: Finisar Corporation
    Inventors: Steve Wang, Xuejun Lu, Frank Levinson
  • Patent number: 7227237
    Abstract: A high fill-factor photosensor array is formed comprising a P-layer, an I-layer, one or more semiconductor structures adjacent to the I-layer and each coupled to a N-layer, an electrically conductive electrode formed on top of the P-layer, and an additional semiconductor structure, adjacent to the N-layer and which is electrically connected to a voltage bias source. The bias voltage applied to the additional semiconductor structure charges the additional semiconductor structure, thereby creating a tunneling effect between the N-layer and the P-layer, wherein electrons leave the N-layer and reach the P-layer and the electrically conductive layer. The electrons then migrate and distribute uniformly throughout the electrically conductive layer, which ensures a uniform bias voltage across to the entire photosensor array. The biasing scheme in this invention allows to achieve mass production of photosensors without the use of wire bonding.
    Type: Grant
    Filed: December 22, 2003
    Date of Patent: June 5, 2007
    Assignee: Palo Alto Research Center Incorporated
    Inventors: JengPing Lu, Kathleen Dore Boyce, legal representative, James B. Boyce, deceased
  • Patent number: 7209623
    Abstract: A semiconductor waveguide based optical receiver is disclosed. An apparatus according to aspects of the present invention includes an absorption region defined along an optical waveguide. The absorption region includes a first type of semiconductor material having a first refractive index. The apparatus also includes a multiplication region defined along the optical waveguide. The multiplication region is proximate to and separate from the absorption region. The multiplication region includes a second type of semiconductor material having a second refractive index. The first refractive index greater than the second refractive index such that an optical beam directed through the optical waveguide is pulled towards the absorption region from the multiplication region and absorbed in the absorption region to create electron-hole pairs from the optical beam. The multiplication region includes first and second doped regions defined along the optical waveguide.
    Type: Grant
    Filed: May 3, 2005
    Date of Patent: April 24, 2007
    Assignee: Intel Corporation
    Inventor: Michael T. Morse
  • Patent number: 7205624
    Abstract: A method of fabricating a detector, the method including forming an island of detector core material on a substrate, the island having a horizontally oriented top end, a vertically oriented first sidewall, and a vertically oriented second sidewall that is opposite said first sidewall; implanting a first dopant into the first sidewall to form a first conductive region that has a top end that is part of the top end of the island; implanting a second dopant into the second sidewall to form a second conductive region that has a top end that is part of the top end of the island; fabricating a first electrical connection to the top end of the first conductive region; and fabricating a second electrical connection to the top end of the second conductive region.
    Type: Grant
    Filed: October 6, 2004
    Date of Patent: April 17, 2007
    Assignee: Applied Materials, Inc.
    Inventors: Francisco A. Leon, Lawrence C. West
  • Patent number: 7199437
    Abstract: A method for embedding optical band gap (OBG) devices in a ceramic substrate (100). The method includes the step (320) of pre-forming an OBG structure (105). The OBG structure can be a micro optical electromechanical systems (MOEMS) device. Further, the OBG structure can be preformed from indium phosphide and/or indium gallium arsenide. The method also includes the step (325) of coating the OBG structure with a surface binding material (230). The surface binding material can be comprised of calcium and hexane. The ratio of the calcium to hexane can be from about 1% to 2%. At a next step (330), the OBG structure can be inserted into the ceramic substrate. A pre-fire step (335) and a sintering step (340) then can be performed on the substrate.
    Type: Grant
    Filed: January 20, 2004
    Date of Patent: April 3, 2007
    Assignee: Harris Corporation
    Inventor: Randy T. Pike
  • Patent number: 7199303
    Abstract: An optical energy conversion apparatus 10 includes a first impurity doped semiconductor layer 5, formed on a substrate, and which is of a semiconductor material admixed with a first impurity, an optically active layer 6, formed on the first impurity doped semiconductor layer 5, and which is of a hydrogen-containing amorphous semiconductor material, and a second impurity doped semiconductor layer 7, admixed with a second impurity and formed on the optically active semiconductor layer 6. The second impurity doped semiconductor layer is of a polycrystallized semiconductor material lower in hydrogen concentration than the material of the optically active semiconductor layer 6. The average crystal grain size in the depth-wise direction in an interfacing structure between the optically active semiconductor layer 6 and the second impurity doped semiconductor layer 7 is decreased stepwise in a direction proceeding from the surface of the second impurity doped semiconductor layer towards the substrate 1.
    Type: Grant
    Filed: March 13, 2001
    Date of Patent: April 3, 2007
    Assignee: Sony Corporation
    Inventors: Akio Machida, Setsuo Usui, Kazumasa Nomoto
  • Patent number: 7196390
    Abstract: A method for encoding information that is encoded in spatial variations of the intensity of light (24) of a first wave-length into light of a second wavelength, the method comprising: generating a first density distribution of electrons homologous with the spatial variations in intensity of the first wavelength light; generating a second additional electron density homologous with the first electron density distribution; trapping electrons from the first and second electron density distributions in a trapping region (34) to generate an electric field homologous with the density distributions in a material (36) that modulates a characteristic of light (22) that passes therethrough responsive to an electric field (46) therein; and transmitting the second wavelength light (22) through the modulating material (36) thereby modulating the second wavelength light in response to the electric field and encoding it with the information.
    Type: Grant
    Filed: June 26, 1999
    Date of Patent: March 27, 2007
    Assignee: 3DV Systems Ltd.
    Inventors: Amnon Manassen, Giora Yahav
  • Patent number: 7192847
    Abstract: A method of forming an ultra-thin wafer level stack package and structure thereof are provided. The method includes providing a first wafer having a plurality of base chips thereon, selectively binding the first wafer to a second substrate, lapping the first wafer to reduce its thickness, dicing the lapped first wafer, bonding a plurality stack chips to each base chip and packaging the base chip with the bonded stack chips to form an IC package. Thus, each IC package comprises at least a base chip and a stack chip. The IC package has a size almost identical to the base chip and a thickness a little larger than the combined thickness of the base chip and the stack chip. If a known good die inspection of the base chips and stack chips are carried out prior to wafer level packaging, overall yield of the IC package is increased.
    Type: Grant
    Filed: February 4, 2005
    Date of Patent: March 20, 2007
    Assignee: United Microelectronics Corp.
    Inventor: Min-Chih Hsuan
  • Patent number: 7180147
    Abstract: A method of forming a high germanium concentration, low defect density silicon germanium film and its associated structures is described, comprising forming a dielectric layer on a substrate, patterning the dielectric layer to form a silicon region and at least one dielectric region, and forming a low defect silicon germanium layer on at least one dielectric region.
    Type: Grant
    Filed: January 12, 2005
    Date of Patent: February 20, 2007
    Assignee: Intel Corporation
    Inventor: Mike Morse
  • Patent number: 7180379
    Abstract: A synchronous clock signal is generated in a large number of local clock circuits at the same time by exposing photoconductive regions in each local clock circuit to a pulsed light source that operates at a fixed frequency. The photoconductive regions generate photoconductive currents which are sufficient to cause a logic inverter to switch states.
    Type: Grant
    Filed: May 3, 2004
    Date of Patent: February 20, 2007
    Assignee: National Semiconductor Corporation
    Inventors: Peter J. Hopper, Philipp Lindorfer, Vladislav Vashchenko, Yuri Mirgorodski
  • Patent number: 7180148
    Abstract: A method of forming a high germanium concentration, low defect density silicon germanium film and its associated structures is described, comprising forming a dielectric layer on a substrate, patterning the dielectric layer to form a silicon region and at least one dielectric region, and forming a low defect silicon germanium layer on at least one dielectric region.
    Type: Grant
    Filed: January 12, 2005
    Date of Patent: February 20, 2007
    Assignee: Intel Corporation
    Inventor: Mike Morse
  • Patent number: 7179527
    Abstract: A substrate with a transparent conductive oxide film (especially a substrate with a transparent conductive oxide film useful as a substrate for a thin-film silicon-based solar cell) being excellent in mass production efficiency and being characterized by having a low resistance, a high transparency and a good light scattering performance over a full wavelength region (300 nm to 3 ?m) of solar ray, a process for its production, and a photoelectric conversion element (especially, solar cell) employing the substrate, are presented. A substrate with a transparent conductive oxide film, comprising a substrate and a transparent conductive oxide layer formed on the substrate and constituted by a plurality of ridges is and a plurality of flat portions, wherein the surfaces of the ridges and the flat portions, have many continuous micron-size protrusions.
    Type: Grant
    Filed: April 19, 2004
    Date of Patent: February 20, 2007
    Assignee: Asahi Glass Company, Limited
    Inventors: Kazuo Sato, Naoki Taneda, Makoto Fukawa, Nobutaka Aomine, Mika Kambe
  • Patent number: 7176547
    Abstract: A four-division photodetector where a formation process of an element isolation structure is simplified is provided. On a P-sub layer that is a common anode of PIN photodiodes (PIN-PD) for every partition, a high resistivity epitaxial layer that is an i layer of the PIN-PD is grown. At a boundary of the partitions, ion implantation is applied from a substrate surface to form an isolation region that is a P+ region. When a cathode region formed for every partition and the P-sub layer are reverse-biased to operate the PIN-PD, the isolation region is set at a ground potential together with the P-sub layer to operate as an anode. As a result, in the epitaxial layer at a position sandwiched between the isolation region and the P-sub layer, a potential barrier to electrons is formed. As a result, electrons generated owing to light absorption in the respective partitions can be inhibited from moving to adjacent partitions and element isolation can thus be realized.
    Type: Grant
    Filed: May 22, 2006
    Date of Patent: February 13, 2007
    Assignee: Sanyo Electric Co., Ltd.
    Inventor: Akihiro Hasegawa
  • Patent number: 7176546
    Abstract: A diode circuit includes a pin diode structure, wherein the n-semiconductor layer is a buried layer, on which the i-area is deposited by an epitaxy method, and wherein a p-semiconductor layer is introduced into the epitaxy layer. A contacting of the p-semiconductor layer and a contacting of the n-semiconductor layer are arranged on the same main surface of the semiconductor substrate so that an integration with an integrated capacitor, an integrated resistor and/or an integrated inductor is possible.
    Type: Grant
    Filed: June 10, 2004
    Date of Patent: February 13, 2007
    Assignee: Infineon Technologies AG
    Inventors: Carsten Ahrens, Wolfgang Hartung, Holger Heuermann, Reinhard Losehand, Josef-Paul Schaffer
  • Patent number: 7145142
    Abstract: A sensor device includes a sensor array in which infrared sensors are arrayed and a detection circuit connected to the output signal line of the sensor array. The detection circuit includes a capacitor having a charging circuit which is selectively driven, a sense amplifier circuit which detects and amplifies a change in sensor current flowing to the output signal line, a current-to-voltage conversion circuit which converts the output current from the sense amplifier circuit into a voltage, a discharging circuit which is controlled by the output voltage of the current-to-voltage conversion circuit to discharge the capacitor, and an output circuit which outputs the terminal voltage of the capacitor.
    Type: Grant
    Filed: November 29, 2002
    Date of Patent: December 5, 2006
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hideyuki Funaki, Keitaro Shigenaka, Yujiro Naruse, Ikuo Fujiwara, Naoya Mashio
  • Patent number: 7138697
    Abstract: The invention addresses the problem of creating a high-speed, high-efficiency photodetector that is compatible with Si CMOS technology. The structure consists of a Ge absorbing layer on a thin SOI substrate, and utilizes isolation regions, alternating n- and p-type contacts, and low-resistance surface electrodes. The device achieves high bandwidth by utilizing a buried insulating layer to isolate carriers generated in the underlying substrate, high quantum efficiency over a broad spectrum by utilizing a Ge absorbing layer, low voltage operation by utilizing thin a absorbing layer and narrow electrode spacings, and compatibility with CMOS devices by virtue of its planar structure and use of a group IV absorbing material. The method for fabricating the photodetector uses direct growth of Ge on thin SOI or an epitaxial oxide, and subsequent thermal annealing to achieve a high-quality absorbing layer.
    Type: Grant
    Filed: February 24, 2004
    Date of Patent: November 21, 2006
    Assignee: International Business Machines Corporation
    Inventors: Jack O. Chu, Gabriel K. Dehlinger, Alfred Grill, Steven J. Koester, Qiging Ouyang, Jeremy D. Schaub
  • Patent number: 7122736
    Abstract: A thin-film solar cell is provided. The thin-film solar cell comprises an a-SiGe:H (1.6 eV) n-i-p solar cell having a deposition rate of at least ten (10) ?/second for the a-SiGe:H intrinsic layer by hot wire chemical vapor deposition. A method for fabricating a thin film solar cell is also provided. The method comprises depositing a n-i-p layer at a deposition rate of at least ten (10) ?/second for the a-SiGe:H intrinsic layer.
    Type: Grant
    Filed: August 16, 2001
    Date of Patent: October 17, 2006
    Assignee: Midwest Research Institute
    Inventors: Qi Wang, Eugene Iwaniczko
  • Patent number: 7095006
    Abstract: A structure and method of fabrication for a Si based material p-i-n photodetector is disclosed. The light is absorbed in an undoped layer containing SiGe or Ge in such a manner that the absorption length is not limited by a critical thickness of the SiGe or Ge layer. The result is achieved by growing the SiGe or Ge layer from the walls of a trench in monocrystalline Si using lateral epitaxial. A second, doped material is disposed over the undoped layer for biasing and photocarrier collection in the p-i-n diode.
    Type: Grant
    Filed: December 16, 2003
    Date of Patent: August 22, 2006
    Assignee: International Business Machines Corporation
    Inventor: Min Yang
  • Patent number: 7095090
    Abstract: A photoelectric conversion device taking the form of a thin film and having a substrate exhibiting poor thermal resistance. The device prevents thermal deformation which would normally be caused by local application of excessive heat to the substrate. The device has output terminals permitting the output from the device to be taken out. The output terminals are formed on the surface of the substrate opposite to the photoelectric conversion device. The device further includes electrical connector portions for electrically connecting the electrodes of the device with the output terminals. The present invention also provides a method of treating a substrate having poor thermal resistance with a plasma with a high throughput. The substrate is continuously supplied into a reaction chamber and treated with a plasma. This supply operation is carried out in such a way that the total length of the substrate existing in a plasma processing region formed by electrodes is longer than the length of the electrodes.
    Type: Grant
    Filed: April 12, 2004
    Date of Patent: August 22, 2006
    Assignees: Semiconductor Energy Laboratory Co., Ltd., TDK Corporation
    Inventors: Setsuo Nakajima, Yasuyuki Arai, Hisato Shinohara, Masayoshi Abe
  • Patent number: 7075165
    Abstract: A method of fabricating a detector that involves: forming a trench in a substrate, the substrate having an upper surface; forming a first doped semiconductor layer on the substrate and in the trench; forming a second semiconductor layer on the first doped semiconductor layer and extending into the trench, the second semiconductor layer having a conductivity that is less than the conductivity of the first doped semiconductor layer; forming a third doped semiconductor layer on the second semiconductor layer and extending into the trench; removing portions of the first, second and third layers that are above a plane defined by the surface of the substrate to produce an upper, substantially planar surface and expose an upper end of the first doped semiconductor layer in the trench; forming a first electrical contact to the first semiconductor doped layer; and forming a second electrical contact to the third semiconductor doped layer.
    Type: Grant
    Filed: May 28, 2004
    Date of Patent: July 11, 2006
    Assignee: Applied Material, Inc.
    Inventors: Francisco A. Leon, Lawrence C. West, Yuichi Wada, Gregory L. Wojcik, Stephen Moffatt
  • Patent number: 7076124
    Abstract: An integrated circuit cast on a single die having a plurality of receivers in a receiver region, a plurality of transmitters in a transmitter region, and a spatial separation region having a plurality of n-type and p-type subregions disposed on the single die to separate the transmitter region from the receiver region. The pn-junctions between the n-type and p-type subregions are reverse-biased thereby reducing or eliminating coupling of noise and crosstalk between the transmitter and receiver is reduced.
    Type: Grant
    Filed: December 20, 2002
    Date of Patent: July 11, 2006
    Assignee: Avago Technologies, Ltd.
    Inventors: Matthew Scott Abrams, Young Gon Kim, Myunghee Lee, Stefano Therisod, Robert Elsheimer
  • Patent number: 7064263
    Abstract: A stacked photovoltaic device comprises at least three p-i-n junction constituent devices superposed in layers, each having a p-type layer, an i-type layer and an n-type layer which are formed of silicon non-single crystal semiconductors. An amorphous silicon layer is used as the i-type layer of a first p-i-n junction, a microcrystalline silicon layer is used as the i-type layer of a second p-i-n junction and a microcrystalline silicon layer is used as the i-type layer of a third p-i-n junction, the first to third layers being in order from the light incident side. In this way, a stacked photovoltaic device can be provided which is practical and low-cost and yet has high reliability and high photoelectric conversion efficiency.
    Type: Grant
    Filed: September 8, 2004
    Date of Patent: June 20, 2006
    Assignee: Canon Kabushiki Kaisha
    Inventors: Masafumi Sano, Tetsuro Nakamura
  • Patent number: 7061019
    Abstract: A circuit array substrate is provided with thin-film transistors 4 and 5 and PIN diode 6 formed on insulation substrate 3. Active layer 11 and photo-electric sensor portion 21 are made of poly-silicon films. Impurities are doped into active layer 11 and photo-electric sensor portion 21 in the same process chamber, if necessary, to make their impurity concentrations different from each other. Thin-film transistors 4 and 5 with prescribed characteristics and PIN diode 6 with improved photosensitivity can be simultaneously, easily manufactured on insulation substrate 3 with a lesser number of processes.
    Type: Grant
    Filed: July 12, 2004
    Date of Patent: June 13, 2006
    Assignee: Toshiba Matsushita Display Technology Co., Ltd.
    Inventors: Arichika Ishida, Masayoshi Fuchi, Yuki Matsuura, Norio Tada
  • Patent number: 7049673
    Abstract: This photoelectric detection device comprises a matrix of elementary detectors on an insulating substrate. Each of the elementary detectors has a stack consisting of a lower electrode, a layer of a photosensitive material and a phototransparent upper electrode. The upper electrode is common to all the elementary detectors. Each of the lower electrodes is connected independently of one another to a sense circuit. The lower electrodes are each positioned on an individualized insulating zone, which is raised with respect to the insulating substrate. Furthermore, the upper electrode is not flat and is inserted between two adjacent zones until it reaches a level below that of the lower electrodes.
    Type: Grant
    Filed: November 20, 2003
    Date of Patent: May 23, 2006
    Assignee: Commissariat A l'Energie Atomique
    Inventors: Norbert Moussy, Cyril Guedj
  • Patent number: 7042059
    Abstract: An optical semiconductor device includes: a photo detector section which includes: a first semiconductor layer of a first conductivity type formed on a surface of a semiconductor substrate of the first conductivity type, a second semiconductor layer of a second conductivity type formed on a surface of the first semiconductor layer, and an antireflection film formed on a surface of the second semiconductor layer and preventing reflection of incident light; and a circuit element section which includes: a circuit element formed on the second semiconductor layer on the semiconductor substrate, and a passivation film covering an uppermost electrode layer among electrode layers constituting the circuit element and formed out of a same material as a material of the antireflection film.
    Type: Grant
    Filed: August 11, 2004
    Date of Patent: May 9, 2006
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Yukiko Kashiura
  • Patent number: 7038238
    Abstract: A semiconductor device including a conductive substrate or a first conductive layer formed on the substrate, a non-single-crystal semiconductor layer member is disposed on the conductive substrate or the conductive layer, the non-single-crystal semiconductor layer member having at least one intrinsic, non-single-crystal semiconductor layer, and a second conductive layer disposed on the non-single-crystal semiconductor layer. The intrinsic non-single-crystal semiconductor layer contains sodium and oxygen in very low concentrations where each concentration is 5Ɨ1018 atoms/cm3 or less.
    Type: Grant
    Filed: April 18, 1996
    Date of Patent: May 2, 2006
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Shunpei Yamazaki
  • Patent number: 7015560
    Abstract: A light-receiving device, a method for manufacturing the same, and an optoelectronic integrated circuit including the same are provided. The light-receiving device includes a substrate; an intrinsic region formed on the substrate; a first region formed to a shallow depth in the intrinsic region; and a second region formed to a deep depth in the intrinsic region and distanced from the first region, wherein the first and second regions are doped with different conductivity types. The light-receiving device can shorten the transit time of holes with slow mobility. Therefore, no response delay occurs, and thus, a high response speed can be accomplished.
    Type: Grant
    Filed: February 18, 2004
    Date of Patent: March 21, 2006
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jun-young Kim, Byoung-lyong Choi, Eun-kyung Lee
  • Patent number: 7012314
    Abstract: A method of making a semiconductor device having a predetermined epitaxial region, such as an active region, with reduced defect density includes the steps of: (a) forming a dielectric cladding region on a major surface of a single crystal body of a first material; (b) forming a first opening that extends to a first depth into the cladding region; (c) forming a smaller second opening, within the first opening, that extends to a second depth greater than the first depth and that exposes an underlying portion of the major surface of the single crystal body; (d) epitaxially growing regions of a second semiconductor material in each of the openings and on the top of the cladding region; (e) controlling the dimensions of the second opening so that defects are confined to the epitaxial regions grown within the second opening and on top of the cladding region, a first predetermined region being located within the first opening and being essentially free of defects; (D planarizing the top of the device to remove all
    Type: Grant
    Filed: June 3, 2003
    Date of Patent: March 14, 2006
    Assignee: Agere Systems Inc.
    Inventors: Jeffrey Devin Bude, Malcolm Carroll, Clifford Alan King
  • Patent number: 7009210
    Abstract: A method and apparatus for a tunable optical spectrum analyzer that can measure the optical spectrum of a demultiplexed DWDM signal are presented. The signal level and Optical Signal to Noise Ratio (OSNR) of an individual channel of the DWDM signal can be obtained from the measured optical spectrum. The device employs a rapid tuning and detection technique to obtain the optical spectrum of the incoming signal. In a preferred embodiment the apparatus is fabricated on a single chip resulting in a compact measurement device. Using the device of the preferred embodiment, single channel OSNR can be determined in as small a time interval as approximately 225 microseconds. Using an array of these devices an entire DWDM mixed signal can be monitored as to OP and OSNR in the same time interval.
    Type: Grant
    Filed: May 9, 2001
    Date of Patent: March 7, 2006
    Assignee: Alphion Corporation
    Inventors: Jithamithra Sarathy, Chinnabbu Ekambaram, David Lidsky, Bharat Dave, Boris Stefanov, Tan B. Thai, Ronald Simprini, Julio Martinez, Gaurav Naik
  • Patent number: 7005690
    Abstract: The solid-state image sensor includes a pixel part 10, an analog circuit part 12, a digital circuit part 14 and an input/output circuit part 16. The digital circuit part 14 includes a first well 42c of a second conduction type formed in a second region of a semiconductor substrate 20 of a first conduction type surrounding a first region thereof; a first buried diffused layer 40c of the second conduction type buried in the first region: a second well 44b of the first conduction type formed near a surface of the semiconductor substrate 20 in the first region; and a first transistor 38e formed on the second well 44b.
    Type: Grant
    Filed: December 6, 2004
    Date of Patent: February 28, 2006
    Assignee: Fujitsu Limited
    Inventors: Masahiro Chijiiwa, Shigetoshi Takeda, Masaya Katayama
  • Patent number: 7005687
    Abstract: The present invention provides the photodetector comprising a lower cladding layer including a n-type doped region, an absorbing layer, an upper cladding layer including a p-type doped region, and ohmic electrodes connected to said lower cladding layer and said upper cladding layer, wherein said p-type doped region extends to be formed into said absorbing layer by a predetermined length. In accordance with present invention, by reducing effect of the hetero junction barrier where holes move in the intrinsic region, the operating voltage can be decreased and the bandwidth can be improved.
    Type: Grant
    Filed: October 8, 2003
    Date of Patent: February 28, 2006
    Assignee: Electronics and Telecommunications Research Institute
    Inventors: Joong Seon Choe, Yong Hwan Kwon
  • Patent number: 6995411
    Abstract: An image sensor has a vertically integrated thin-film photodiode.
    Type: Grant
    Filed: February 18, 2004
    Date of Patent: February 7, 2006
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Dun-Nian Yaung, Sou-Kuo Wu, Ho-Ching Chien
  • Patent number: 6989522
    Abstract: A light-receiving device has a high-concentration impurity layer of a first conductivity type and a high-concentration impurity layer of a second conductivity type surrounding it formed on a substrate of the first conductivity type having a low impurity concentration so as to function as a light-receiving portion. The high-concentration impurity layers of the first and second conductivity types are arranged in the same direction as the top surface of the substrate. A layer having a short carrier life time is formed on the bottom surface of the substrate. Thus, carriers ascribable to unnecessary light components that have reached the layer having a short carrier life time have a shorter life time, making it possible to sufficiently cut unnecessary long-wavelength light components.
    Type: Grant
    Filed: July 6, 2001
    Date of Patent: January 24, 2006
    Assignees: Sanyo Electric Co., Ltd., Tottori Sanyo Electric Co., Ltd.
    Inventor: Susumu Nishimura
  • Patent number: 6975012
    Abstract: Disclosed is a semiconductor radiation detector element of Schottky barrier type, comprising: a compound semiconductor crystal including cadmium and tellurium as main components; and voltage application means for applying voltage to the compound semiconductor crystal. According to the present invention, said voltage application means includes a compound of indium, cadmium and tellurium: InxCdyTez formed on one surface of the compound semiconductor crystal. Preferably, the rate ā€œzā€ of occupation of tellurium in the compound InxCdyTez is in the range of not less than 42.9%, but not greater than 50% by ratio of number of atoms. Furthermore, preferably, the rate ā€œyā€ of occupation of cadmium in the compound InxCdyTez is in the range of not less than 0%, but not greater than 10% by ratio of number of atoms.
    Type: Grant
    Filed: October 29, 2003
    Date of Patent: December 13, 2005
    Assignee: Acrorad Co., Ltd.
    Inventors: Miki Moriyama, Masaki Murakami, Atsushi Kyan, Ryoichi Ohno
  • Patent number: 6972469
    Abstract: A PIN diode includes a first p-area, an n-area, and in between an intermediate area on a first surface of a substrate, wherein a doping concentration of the intermediate area is lower than a doping concentration of the p-area and lower than a doping concentration of the n-area. Further, the PIN diode includes a first electrically conductive member, which is arranged on a side of the p-area, which faces away from the intermediate area, and a second electrically conductive member, which is arranged on a side of the n-area, which faces away from the intermediate area. The PIN diode is preferably separated from the substrate by an insulating layer, covered by a further insulating layer on the surface, which faces away from the substrate, and laterally surrounded by a trench filled with an insulating material, such that it is essentially fully insulated and encapsulated.
    Type: Grant
    Filed: December 8, 2003
    Date of Patent: December 6, 2005
    Assignee: Infineon Technologies AG
    Inventors: Raimund Peichl, Philipp Seng
  • Patent number: 6963120
    Abstract: A photovoltaic element is provided which has a high conversion efficiency, a low-cost producibility, a light weight and good overall characteristics in a final product form with a transparent protective member. The photovoltaic element comprises a first pin junction comprising an i-type amorphous semiconductor, a second pin junction comprising an i-type microcrystalline semiconductor, and a third pin junction comprising an i-type microcrystalline semiconductor provided in the mentioned order from a light incidence side, wherein at least a transparent protective member and a transparent electrode layer are provided on the light incidence side of the first pin junction, and wherein of the photocurrents generated at the plurality of pin junctions, the photocurrent generated at the third pin junction is the smallest.
    Type: Grant
    Filed: November 12, 2003
    Date of Patent: November 8, 2005
    Assignee: Canon Kabushiki Kaisha
    Inventors: Atsushi Shiozaki, Shuichiro Sugiyama
  • Patent number: 6960718
    Abstract: In a photovoltaic element according to the present invention, a first transparent conductive film, a second transparent conductive film, a p-type semiconductor film, an intrinsic semiconductor layer, a n-type semiconductor layer and a backside electrode are stacked in turn on a transparent substrate. Then, an intermediate layer is provided between the second transparent conductive film and the p-type semiconductor layer so as to cover the first transparent conductive film and the second transparent conductive film.
    Type: Grant
    Filed: March 28, 2003
    Date of Patent: November 1, 2005
    Assignees: TDK Corporation, Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Tatsuji Sano, Hisao Morooka, Kazuo Nishi
  • Patent number: 6956273
    Abstract: In a photoelectric conversion element which is formed by alternately stacking a region of a first conductivity type and a region of a second conductivity type as a conductivity type opposite to the first conductivity type to form a multi-layered structure, in which junction surfaces between the neighboring regions of the first and second conductivity types are formed to have depths suited to photoelectrically convert light in a plurality of different wavelength ranges, and which outputs signals for respective wavelength ranges, a region of a conductivity type opposite to the conductivity type of a surface-side region of the junction surface closest to a surface is formed in the surface of the surface-side region. Thus, highly color-separable signals which suffer less color mixture upon reading out signals from a plurality of photodiode layers is read out.
    Type: Grant
    Filed: April 4, 2003
    Date of Patent: October 18, 2005
    Assignee: Canon Kabushiki Kaisha
    Inventor: Toru Koizumi
  • Patent number: 6956251
    Abstract: A blue-ultraviolet on-p-GaAs substrate pin Zn1-xMgxSySe1-y photodiode with high quantum efficiency, small dark current, high reliability and a long lifetime. The ZnMgSSe photodiode has a metallic p-electrode, a p-GaAs single crystal substrate, a p-(ZnSe/ZnTe)m superlattice (m: integer number of sets of thin films), an optionally formed p-ZnSe buffer layer, a p-Zn1-xMgxSySe1-y layer, an i-Zn1-xMgxSySe1-y layer, an n-Zn1-xMgxSySe1-y layer, an n-electrode and an optionally provided antireflection film. Incidence light arrives at the i-layer without passing ZnTe layers. Since the incidence light is not absorbed by ZnTe layers, high quantum efficiency and high sensitivity are obtained.
    Type: Grant
    Filed: January 20, 2005
    Date of Patent: October 18, 2005
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Koshi Ando, Tomoki Abe, Takao Nakamura
  • Patent number: 6952003
    Abstract: An apparatus for detecting a centroid of a spot produced by electromagnetic radiation, e.g., optic radiation, using an array of PIN photodiodes serving as photodetectors and being organized in columns and in rows. Vertical connections are used to interconnect the PIN photodiodes in the columns in accordance with a first pattern that interconnects two or more adjacent columns. Horizontal connections are used to interconnect PIN photodiodes in the rows in accordance with a second pattern that interconnects two or more adjacent rows. The first and second patterns of interconnections can include just two adjacent columns and two adjacent rows, respectively and form a checkerboard interconnect pattern. The interconnections are made such that there are no anode connections between the PIN photodiodes in the rows and columns.
    Type: Grant
    Filed: August 5, 2004
    Date of Patent: October 4, 2005
    Assignee: Intel Corporation
    Inventors: David Skurnik, Randall Brian Sprague, Geoffrey Hugh Jones, Eric Charles Abbott, Waisiu Law
  • Patent number: 6946717
    Abstract: A compound semiconductor device is comprising a compound semiconductor substrate (219) having a ground plane (205); an active element (201) disposed on the substrate; a passive element (211) disposed on the substrate and electrically coupled to the active element; and an insulating layer (202) adjacent the substrate and interposed between the passive device and ground surface such that there is no resistive ground path from the passive device to the ground surface.
    Type: Grant
    Filed: January 30, 2002
    Date of Patent: September 20, 2005
    Assignee: M/A-Com, Inc.
    Inventors: David Russell Hoag, Timothy Edward Boles, Daniel G. Curcio
  • Patent number: 6924546
    Abstract: The invention concerns a low-capacity vertical diode designed to be mounted by a front surface made in a semiconductor substrate (1), comprising a first zone projecting relative to the surface of the substrate including at least a semiconductor layer (3) doped with a type of conductivity opposite to that of the substrate, the upper surface of the semiconductor layer bearing a first solder bump (23). The diode comprises a second zone including on the substrate a thick strip conductor (16) bearing at least second solder bumps (24), said first and second solder bumps defining a plane parallel to the substrate plane.
    Type: Grant
    Filed: September 10, 2002
    Date of Patent: August 2, 2005
    Assignee: STMicroelectronics S.A.
    Inventors: Emmanuel Collard, Patrick Poveda