Abstract: A photoelectric conversion element according to an embodiment of the present disclosure includes: a first electrode including a plurality of electrodes independent from each other; a second electrode disposed to be opposed to the first electrode; an n-type photoelectric conversion layer including a semiconductor nanoparticle, the n-type photoelectric conversion layer being provided between the first electrode and the second electrode; and a semiconductor layer including an oxide semiconductor material, the semiconductor layer being provided between the first electrode and the n-type photoelectric conversion layer.

Abstract: The present disclosure provides a touch panel, electronic device and information processing method, the touch panel comprising: a substrate, and an electrode layer formed in or on the substrate, wherein the electrode layer and the touch panel have corresponding shapes, and the electrode layer comprises a plurality of hexagonal electrodes which are connected to form the electrode layer. The embodiments of the present disclosure have a simple structure and a better adaptability.

Abstract: A semiconductor device includes a semiconductor body, an electrically conductive via which extends through at least a part of the semiconductor body, and where the via has a top side and a bottom side that faces away from the top side, an electrically conductive etch-stop layer arranged at the bottom side of the via in a plane which is parallel to a lateral direction, where the lateral direction is perpendicular to a vertical direction given by the main axis of extension of the via, and at least one electrically conductive contact layer at the bottom side of the via in a plane which is parallel to the lateral direction. The etch-stop layer is arranged between the electrically conductive via and the contact layer in the vertical direction, the lateral extent in the lateral direction of the etch-stop layer amounts to at least 2.

Abstract: This invention provides a nitride semiconductor light emitting device in which current concentration is suppressed without excessively increasing resistance at a low cost without increasing a manufacturing process. The planar shape of a mesa portion configuring a nitride semiconductor light emitting device is a shape containing a convex-shaped tip portion 352b formed by a curved line or a plurality of straight lines and abase portion 352a continuous to the convex-shaped tip portion 352b, in which an obtuse angle is formed by adjacent two straight lines in the convex-shaped tip portion formed by the plurality of straight lines. The first electrode layer 4 has visible outlines 411 and 412 along a visible outline 302 of the mesa portion through a gap 9 in planar view. The relationship between a gap W1 in the convex-shaped tip portion 352b and a gap W2 in the base portion 352a is W1>W2.

Abstract: To suppress generation of flare and ghosts. A solid state image sensor includes: a pixel array configured to generate a pixel signal according to an amount of incident light by photoelectric conversion in units of pixels arranged in an array manner; a glass substrate bonded with a light-receiving surface of the pixel array; and a light-shielding film formed on a peripheral portion that is an outside of an effective pixel region of the pixel array, in which the light-shielding film is formed at a front stage of the glass substrate. The present disclosure can be adapted to an imaging device.

Abstract: Various embodiments of the present disclosure are directed towards a semiconductor structure including a bond pad disposed within a semiconductor substrate. The semiconductor substrate has a back-side surface and a front-side surface opposite the back-side surface. An upper surface of the semiconductor substrate is vertically below the back-side surface. The bond pad extends through the semiconductor substrate. The bond pad includes a conductive body over the upper surface of the semiconductor substrate and conductive protrusions extending from above the upper surface to below the front-side surface of the semiconductor substrate. A vertical distance between a top surface of the bond pad and the back-side surface of the semiconductor substrate is less than a height of the conductive protrusions. A first bond pad isolation structure extends through the semiconductor substrate and laterally surrounds the conductive protrusions.

Abstract: A plurality of radiation-sensing doped regions are formed in a substrate. A trench is formed in the substrate between the radiation-sensing doped regions. A SiOCN layer is filled in the trench by reacting Bis(tertiary-butylamino)silane (BTBAS) and a gas mixture comprising N2O, N2 and O2 through a plasma enhanced atomic layer deposition (PEALD) method, to form an isolation structure between the radiation-sensing doped regions.

Abstract: A wafer structure, a method for manufacturing the wafer structure, and a chip structure are provided. In a case that two wafers are bonded together, an opening extending through a substrate of one of the wafers is formed at a back surface of the wafer, and a concave-convex structure is formed in the dielectric layer under the opening. At least one of concave portions of the concave-convex structure extends to expose the interconnection layer of the wafer structure. A pad is formed on the concave-convex structure by filling the concave-convex structure, and the pad has the same concave-convex arrangement as the concave-convex structure. In this way, the pad has a concave-convex surface, such that a contact surface area of the pad is effectively increased without increasing a floor space of the pad.

Abstract: In one example embodiment, a PCBA, an optoelectronic module, an electrical coupling, and/or a high speed interconnect may include a first contact pad, a second contact pad adjacent to and spaced apart from the first contact pad, a first wire coupled to the first contact pad via a first ball bump, and a second wire coupled to the second contact pad via a double ball bump.

Abstract: Embodiments of the invention are directed to a method of fabrication of an electro-optical device. A non-limiting example of the method relies on a waveguide. A trench is opened in the waveguide and a stack of optically active semiconductor materials is directly grown from a bottom wall of the trench and are stacked along a stacking direction that is perpendicular to a main plane of the waveguide. The stack is partly encapsulated in the waveguide, whereby a bottom layer of the stack is in direct contact with a waveguide core material, whereas upper portions of opposite, lateral sides of the stack are exposed. An insulating layer of material is deposited to cover exposed surfaces of the waveguide and structured to form a lateral growth template. Contact layers are laterally grown due to the lateral growth template formed. The contact layers can include an n-doped and p-doped contact layers.

Abstract: Array contacts for semiconductor memories may be formed using a first set of parallel stripe masks and subsequently a second set of parallel stripe masks transverse to the first set. For example, one set of masks may be utilized to etch a dielectric layer, to form parallel spaced trenches. Then the trenches may be filled with a sacrificial material. That sacrificial material may then be masked transversely to its length and etched, for example. The resulting openings may be filled with a metal to form array contacts.

Abstract: To simplify the interconnection of signal lines in an imaging element including two semiconductor chips. An imaging element includes a pixel chip and a circuit chip. The pixel chip includes a plurality of pixels each including a charge transfer section configured to transfer a charge generated in accordance with incident light to a charge retention section in accordance with a control signal, and a plurality of first control signal transmission sections each configured to transmit the control signal for each of the charge transfer sections. The circuit chip includes a control signal generation section configured to generate the control signal for each of the charge transfer sections of the plurality of pixels, and a plurality of second control signal transmission sections provided to individually correspond to the first control signal transmission sections and each configured to transmit the generated control signal.

Abstract: Various embodiments of the present disclosure are directed towards a semiconductor device structure including a bond pad isolation structure. A semiconductor substrate has a back-side surface and a front-side surface opposite the back-side surface. A bond pad extends through the semiconductor substrate. The bond pad isolation structure is disposed within the semiconductor substrate. The bond pad isolation structure extends from the front-side surface to the back-side surface of the semiconductor substrate and continuously extends around the bond pad.

Abstract: A backside illuminated image sensor includes pixel regions disposed in a substrate, an insulating layer disposed on a frontside surface of the substrate, a bonding pad disposed on a frontside surface of the insulating layer, and an anti-reflective layer disposed on a backside surface of the substrate. The substrate has a first opening for partially exposing a backside surface of the bonding pad, the insulating layer has a second opening for partially exposing the backside surface of the bonding pad, and the anti-reflective layer has a first portion extending along an inner side surface of the first opening.

Abstract: Embodiments of the present application provide a chip package structure, a chip package method and a terminal device. The chip package structure includes: an optical sensing chip, including a first surface and a second surface, where the first surface is provided with a first pad, the second surface is provided with a connecting end, the first pad is electrically connected to the connecting end, and the connecting end is configured to implement an electrical connection between the chip package structure and the exterior; and an optical path modulating structure, disposed above the first surface, and configured to perform an optical path modulation on an optical signal reflected from a human finger and make the signal incident on the first surface, or perform the optical path modulation on an optical signal emitted from the first surface and make the signal exit to the human finger.

Abstract: A complementary metal oxide semiconductor (CMOS) device embedded with micro-electro-mechanical system (MEMS) components in a MEMS region. The MEMS components, for example, are infrared (IR) thermosensors. The device is encapsulated with a CMOS compatible IR transparent cap to hermetically seal the MEMS sensors in the MEMS region. The CMOS cap includes a base cap with release openings and a seal cap which seals the release openings.

Abstract: A method to produce a light-emitting device package includes mounting junctions on pads of a metalized substrate, where the junctions are at least partially electrically insulated from each other, and forming wavelength converters, where each wavelength converter is located over a different junction and separated by a gap from neighboring wavelength converters.

Abstract: A photonic device can include an optical detector (e.g., a photodetector) coupled to silicon waveguides. Unlike silicon, germanium is an efficient detector at the wavelength of optical signals typically used for data communication. Instead of directly coupling the waveguide to the germanium, in one embodiment, the waveguide extends below the germanium but is spaced sufficiently away from the germanium so that the optical signal is not transferred. Instead, an optical transfer structure (e.g., a tapered waveguide or an optical grating) is disposed between the germanium and the waveguide. The waveguide first transfers the optical signal into the optical transfer structure which then transfers the optical signal into the germanium.

Abstract: A multilayer semiconductor device includes first wirings extending in a first direction and arranged adjacent to each other in a second direction. Dummy wirings are arranged between the first wirings and the second wiring at crossing points between first virtual linear lines extending in a third direction and second virtual linear lines extending in a fourth direction. The third and fourth directions are neither parallel nor orthogonal to the first and second directions. The dummy wirings have a first, a second, and a third dummy wiring. Centers of the second and third dummy wirings are nearest to a center of the first dummy wiring relative to others of the dummy wirings. The respective centers of the first, second, and third dummy wirings are aligned on a third virtual linear line extending in a fifth direction neither parallel to nor perpendicular to the first and second directions.

Abstract: A hybrid bonded structure including a first integrated circuit component and a second integrated circuit component is provided. The first integrated circuit component includes a first dielectric layer, first conductors and isolation structures. The first conductors and the isolation structures are embedded in the first dielectric layer. The isolation structures are electrically insulated from the first conductors and surround the first conductors. The second integrated circuit component includes a second dielectric layer and second conductors. The second conductors are embedded in the second dielectric layer. The first dielectric layer is bonded to the second dielectric layer and the first conductors are bonded to the second conductors.

Abstract: A semiconductor die has active circuits formed on its active surface. Contact pads are formed on the active surface of the semiconductor die and coupled to the active circuits. A die extension region is formed around a periphery of the semiconductor die. Conductive THVs are formed in the die extension region. A wafer level conductive plane or ring is formed on a center area of the active surface. The conductive plane or ring is connected to a first contact pad to provide a first power supply potential to the active circuits, and is electrically connected to a first conductive THV. A conductive ring is formed partially around a perimeter of the conductive plane or ring and connected to a second contact pad for providing a second power supply potential to the active circuits. The conductive ring is electrically connected to a second THV.

Abstract: A substrate that includes a first substrate portion, a second substrate portion and a second dielectric layer. The first substrate portion includes a core layer having a first core surface, and a plurality of core substrate interconnects, wherein the plurality of core substrate interconnects includes a plurality of surface core substrate interconnects formed over the first surface of core layer. The second substrate portion includes a first dielectric layer having a first dielectric surface, the first dielectric surface facing the first core surface of the core layer, and a plurality of substrate interconnects, wherein the plurality of substrate interconnects includes a plurality of interconnects formed over the first dielectric surface. The second dielectric layer is formed between the first substrate portion and the second substrate portion such that the plurality of surface core substrate interconnects and the plurality of substrate interconnects are located in the second dielectric layer.

Abstract: The present disclosure relates to an image sensor with a pad structure formed during a front-end-of-line process. The pad structure can be formed prior to formation of back side deep trench isolation structures and metal grid structures. An opening is formed on a back side of the image sensor device to expose the embedded pad structure and to form electrical connections.

Abstract: In some embodiments, 3-dimensional semiconductor memory device includes a semiconductor substrate extending horizontally in a first direction and a second direction crossing the first direction. A stacked memory cell array is formed on the semiconductor substrate. The memory device further includes a separation pattern including a plurality of separation lines extending in the first direction and arranged in the second direction, and dividing the stacked memory cell array into a plurality of memory cell structures extending in the first direction and arranged in the second direction. An upper insulating layer is formed above the plurality of memory cell structures and separation lines, and a passivation layer is formed above the upper insulating layer. The passivation layer includes a plurality of first regions having a first vertical thickness. A plurality of gap regions in the passivation layer are formed between the plurality of first regions.

Abstract: A semiconductor device includes a substrate, a conductive layer, a transparent layer, a transparent hard mask layer, a carrier, and a device layer. The substrate has a first surface and a second surface opposite to each other. The conductive layer is disposed on the first surface of the substrate. The transparent layer is disposed on the conductive layer. The transparent hard mask layer is disposed on the transparent layer, in which the substrate has an etch selectivity with respect to the transparent hard mask layer. The device layer is disposed between the carrier and the second surface of the substrate, in which various portions of the device layer are respectively exposed by various through holes which pass through the transparent hard mask layer, the transparent layer, the conductive layer, and the substrate.

Abstract: A method includes placing a semiconductor substrate on a first curved surface of a first bending tool, using a second bending tool with a second surface to apply pressure to the semiconductor substrate, thereby pressing the semiconductor substrate onto the first curved surface and bending the semiconductor substrate, and removing the bended semiconductor substrate from the first bending tool.

Abstract: The present disclosure relates to a solid-state image sensing device, a manufacturing method, and an electronic apparatus, in which surface roughness on a wiring surface can be suppressed. In redistribution layer forming processing, a Ti/Cu film corresponds to a barrier layer and a seed layer is formed by Ti/Cu sputtering after opening a through-silicon via. At this point, actually, degassing heating, reverse sputtering, Ti deposition, and Seed-Cu deposition are sequentially performed. As a method of depositing a Seed-Cu film having high crystallinity in deposition of the Seed-Cu film, performing deposition by increasing a substrate temperature to a high temperature is one method, and the Seed-Cu film of Cu(111)/(200) is formed by performing deposition at the substrate temperature of 60 degrees or more, and Cu haze are suppressed. The present disclosure can be applied to a CMOS solid-state image sensing device used as an imaging device such as a camera.

Abstract: Disclosed herein are a semiconductor light emitting element and a backlight assembly including the same. The semiconductor light emitting element includes: a light emitting element chip including a first pad and a second pad and having an upper surface and a side surface; a wavelength conversion layer famed on the upper surface and the side surface of the light emitting element chip; a sidewall reflection part famed to be spaced apart from the side surface of the light emitting element chip; and a bottom surface reflection part famed to protrude at a lower portion of the sidewall reflection part. The sidewall reflection part and the bottom surface reflection part of the light emitting element are configured to reflect light in a direction in which the light penetrates through an upper surface of the wavelength conversion layer, the light being generated from the light emitting element chip.

Abstract: A solid-state imaging device includes: a first semiconductor substrate including a photoelectric conversion element; and a second semiconductor substrate including at least a part of a peripheral circuit arranged in a main face of the second semiconductor substrate, the peripheral circuit generating a signal based on the charge of the photoelectric conversion element, a main face of the first semiconductor substrate and the main face of the second semiconductor substrate being opposed to each other with sandwiching a wiring structure therebetween; a pad to be connected to an external terminal; and a protection circuit electrically connected to the pad and to the peripheral circuit, wherein the protection circuit is arranged in the main face of the second semiconductor substrate.

Abstract: The present invention relates to plasmonic components, more particularly plasmonic waveguides, and to plasmonic photodetectors that can be used in the field of microoptics and nanooptics, more particularly in highly integrated optical communications systems in the infrared range (IR range) as well as in power engineering, e.g. photovoltaics in the visible range. The present invention also specifies a method for producing a plasmonic component, more particularly for photodetection on the basis of internal photoemission.

Abstract: A backside illuminated image sensor includes a photodiode arranged in a substrate, a first insulating layer arranged on a front surface of the substrate, a bonding pad arranged on the first insulating layer, and a second insulating layer arranged on the first insulating layer and the bonding pad. The bonding pad is partially exposed by an opening passing through the substrate and the first insulating layer, and an edge portion of the bonding pad is supported by the first and second insulating layers.

Abstract: When a trench that penetrates a semiconductor substrate in a scribe region in a solid-state imaging element of a back side illumination type, occurrence of contamination of the solid-state imaging element caused by an etching step for foaming the trench or a dicing step for singulating a semiconductor chip is prevented. When a silicide layer that covers a surface and the like of an electrode of a transistor is formed, in order to prevent formation of the silicide layer that covers a main surface of the semiconductor substrate in the scribe region, the main surface of the semiconductor substrate is covered with an insulation film before a forming step for the silicide layer.

Abstract: An image sensor chip having a sidewall interconnect structure to bond and/or electrically couple the image sensor chip to a package substrate is provided. The image sensor chip includes a substrate supporting an integrated circuit (IC) configured to sense incident light. The sidewall interconnect structure is arranged along a sidewall of the substrate and electrically coupled with the IC. A method for manufacturing the image sensor chip and an image sensor package including the image sensor chip are also provided.

Abstract: Presented herein is a device including an image sensor having a plurality of pixels disposed in a substrate and configured to sense light through a back side of the substrate and an RDL disposed on a front side of the substrate and having a plurality of conductive elements disposed in one or more dielectric layers. A sensor shield is disposed over the back side of the substrate and extending over the image sensor. At least one via contacts the sensor shield and extends from the sensor shield through at least a portion of the RDL and contacts at least one of the plurality of conductive elements.

Abstract: Connector inserts and other structures that have a high signal integrity and low insertion loss, are reliable, and are readily manufactured. One example may provide a connector insert formed primarily using a printed circuit board. Contacts on the connector insert may be akin to contacts on a printed circuit board and they may connect to traces having matched impedances on the printed circuit board in order to improve signal integrity and reduce insertion loss. The printed circuit board may be manufactured in a manner for increased reliability. Plating, solder block, and other manufacturing steps that are native to printed circuit board manufacturing may be employed to improve manufacturability. Specialized tools that may provide a chamfered edge on the connector inserts may be employed.

Abstract: A micromachined apparatus includes micromachined thermistor having first and second ends physically and thermally coupled to a substrate via first and second anchor structures to enable a temperature-dependent resistance of the micromachined thermistor to vary according to a time-varying temperature of the substrate. The micromachined thermistor has a length, from the first end to the second end, greater than a linear distance between the first and second anchor structures.

Abstract: A method in which microelectronic devices are attached to a substrate surface, wherein spaces interpose neighboring ones of the microelectronic devices. Each microelectronic device has an outermost surface that is substantially parallel to the substrate surface. The substrate is closed in a transfer molding cavity of a transfer molding apparatus such that an internal surface of the transfer molding cavity contacts a substantial portion of each of the outermost surfaces of the microelectronic devices. A molding compound is subsequently injected into the transfer molding cavity, including into the spaces between ones of the plurality of microelectronic devices.

Abstract: An integrated circuit device including a semiconductor substrate, a first bonding pad structure, a second bonding pad structure, a third bonding pad structure, a first internal bonding wire, and a second internal bonding wire is provided. The first bonding pad structure is disposed on a surface of the semiconductor substrate and exposed outside of the semiconductor substrate. The second bonding pad structure is disposed on the surface of the semiconductor substrate and exposed outside of the semiconductor substrate. The third bonding pad structure is disposed on the surface of the semiconductor substrate and exposed outside of the semiconductor substrate. The first bonding pad structure is electrically coupled to the third bonding pad structure via the first internal bonding wire. The third bonding pad structure is electrically coupled to the second bonding pad structure via the second internal bonding wire.

Abstract: The interplay between chiral tunneling and spin-momentum locking of helical surface states leads to spin amplification and filtering in a 3D Topological Insulator (TI). Chiral tunneling across a TI pn junction allows normally incident electrons to transmit, while the rest are reflected with their spins flipped due to spin-momentum locking. The net result is that the spin current is enhanced while the dissipative charge current is simultaneously suppressed, leading to an extremely large, tunable longitudinal spin Hall angle (˜20) at the reflected end. At the transmitted end, the angle stays close to one and the electrons are completely spin polarized.

Abstract: A chip package includes a chip, an insulating layer and a conductive layer. The chip includes a substrate, an epitaxy layer, a device region and a conductive pad. The epitaxy layer is disposed on the substrate, and the device region and the conductive pad are disposed on the epitaxy layer. The conductive pad is at a side of the device region and connected to the device region. The conductive pad protrudes out of a side surface of the epitaxy layer. The insulating layer is disposed below the substrate and extended to cover the side surface of the epitaxy layer. The conductive layer is disposed below the insulating layer and extended to contact the conductive pad. The conductive layer and the side surface of the epitaxy layer are separated by a first distance.

Abstract: An image sensor is provided. The image sensor includes a substrate, a first interlayer insulating layer, a first metal line, and a shielding structure. The substrate includes a pixel array, a peripheral circuit area, and an interface area disposed between the pixel array and the peripheral circuit area. The first interlayer insulating layer is formed on a first surface of the substrate. The first metal line is disposed on the first interlayer insulating layer of the pixel array. The second interlayer insulating layer is disposed on the first interlayer insulating layer wherein the second interlayer insulating layer covers the first metal line. The shielding structure passes through the substrate in the interface area wherein the shielding structure electrically insulates the pixel array of the substrate and the peripheral circuit area.

Abstract: The invention relates to a microelectromechanical resonator device comprising a support structure and a semiconductor resonator plate doped to a doping concentration with an n-type doping agent and being capable of resonating in a width-extensional resonance mode. In addition, there is at least one anchor suspending the resonator plate to the support structure and an actuator for exciting the width-extensional resonance mode into the resonator plate. According to the invention, the resonator plate is doped to a doping concentration of 1.2*1020 cm?3 or more and has a shape which, in combination with said doping concentration and in said width-extensional resonance mode, provides the second order temperature coefficient of frequency (TCF2) to be 12 ppb/C2 or less at least at one temperature. Several practical implementations are presented.

Abstract: A semiconductor device includes a substrate, a circuit layer formed on a first surface of the substrate and including a via pad and an interlayer insulating layer covering the via pad, a via structure configured to fully pass through the substrate, partially pass through the interlayer insulating layer and be in contact with the via pad, a via isolation insulating layer configured to pass through the substrate and be spaced apart from outer side surfaces of the via structure in a horizontal direction and a pad structure buried in the substrate and exposed on a second surface of the substrate opposite the first surface of the substrate.

Abstract: The present invention provides a radiation detector UBM electrode structure body and a radiation detector which suppress the degradation of metal electrode layers at the time of formation of UBM layers and achieve sufficient electric characteristics, and a method of manufacturing the same. A radiation detector UBM electrode structure body according to the present invention includes a substrate made of CdTe or CdZnTe, comprising a Pt or Au electrode layer formed on the substrate by electroless plating, an Ni layer formed on the Pt or Au electrode layer by sputtering, and an Au layer formed on the Ni layer by sputtering.

Abstract: A hermetically-sealed universal pressure sensor comprises a MEMS disk, a compensate disk, and an optional interconnect ring. The MEMS disk has one or more MEMS dies that can convert ambient pressures to electrical signals, which is processed and compensated at an integrated circuit on the compensate disk. The interconnect ring can optionally provide electrical connections and hermetic seal properties between the MEMS disk and the compensate disk.

Abstract: The invention relates to a light-emitting device like an OLED comprising a light emission region between an anode (5) and a cathode (6). An alternating arrangement (9) of anode pads (11) for electrically connecting the anode and cathode pads (10) for electrically connecting the cathode and an encapsulation (8) are configured such that the anode and cathode pads are electrically connectable by straight anode and cathode electrical connectors (3, 4) through openings (12) of the encapsulation. The alternating arrangement of the anode and cathode pads can lead to a more homogenous electrical field between the anode and the cathode and therefore allows for an improved degree of homogeneity of light emission. More, since the alternating arrangement of the anode and cathode pads is connectable by corresponding straight connectors, the contacting of the pads can be performed technically relatively easily.

Abstract: Image sensor and method of manufacturing the same are provided. The image sensor includes a semiconductor substrate including a pixel area, a voltage connection area, and a pad area, a plurality of photoelectric conversion devices in the pixel area, an anti-reflective layer on a back side of the semiconductor substrate and on the plurality of photoelectric conversion devices, a device isolation structure between the plurality of photoelectric conversion devices, at least one voltage connection structure in the voltage connection area, and electrically connected to the device isolation structure, at least one voltage applying device electrically connected to the at least one voltage connection structure, an internal circuit including at least one conductive inner wire and at least one conductive inner via in an insulating layer, and a through via structure in the pad area.

Abstract: A semiconductor substrate includes: an alignment mark being formed of a material that reflects a detection light for detecting positions and having a detection edge portion; a light-shielding layer portion having a larger outer shape than the alignment mark, being formed of a material that shields the detection light, and being disposed at a position on a backside of the alignment mark when seen from an incidence side of the detection light; and one or more light-transmitting layer portions being laminated between the alignment mark and the light-shielding layer portion so as to transmit the detection light and not being patterned at least in a range that overlaps the light-shielding layer portion.

Abstract: A semiconductor package module may include a first substrate, and a second substrate disposed to face the first substrate. The semiconductor package module may include an interconnection member electrically connecting the first substrate to the second substrate and including a plurality of wires. Portions of the plurality of wires may be twisted and wound together and may be bent to extend in a predetermined direction.

Abstract: A semiconductor structure less affected by stress and a method for forming the same are provided. The semiconductor structure includes a semiconductor chip. Stress-sensitive circuits are substantially excluded out of an exclusion zone to reduce the effects of the stress to the stress-sensitive circuits. The stress-sensitive circuits include analog circuits. The exclusion zone preferably includes corner regions of the semiconductor chip, wherein the corner regions preferably have a diagonal length of less than about one percent of the diagonal length of the semiconductor chip. The stress-sensitive analog circuits preferably include devices having channel lengths less than about five times the minimum channel length.