With Particular Contact Geometry (e.g., Ring Or Grid, Or Bonding Pad Arrangement) Patents (Class 257/459)
  • Patent number: 10679979
    Abstract: A multilayer semiconductor device includes first wirings extending in a first direction and arranged adjacent to each other in a second direction. Dummy wirings are arranged between the first wirings and the second wiring at crossing points between first virtual linear lines extending in a third direction and second virtual linear lines extending in a fourth direction. The third and fourth directions are neither parallel nor orthogonal to the first and second directions. The dummy wirings have a first, a second, and a third dummy wiring. Centers of the second and third dummy wirings are nearest to a center of the first dummy wiring relative to others of the dummy wirings. The respective centers of the first, second, and third dummy wirings are aligned on a third virtual linear line extending in a fifth direction neither parallel to nor perpendicular to the first and second directions.
    Type: Grant
    Filed: October 3, 2018
    Date of Patent: June 9, 2020
    Assignee: Seiko Epson Corporation
    Inventors: Katsumi Mori, Kei Kawahara, Yoshikazu Kasuya
  • Patent number: 10672820
    Abstract: A hybrid bonded structure including a first integrated circuit component and a second integrated circuit component is provided. The first integrated circuit component includes a first dielectric layer, first conductors and isolation structures. The first conductors and the isolation structures are embedded in the first dielectric layer. The isolation structures are electrically insulated from the first conductors and surround the first conductors. The second integrated circuit component includes a second dielectric layer and second conductors. The second conductors are embedded in the second dielectric layer. The first dielectric layer is bonded to the second dielectric layer and the first conductors are bonded to the second conductors.
    Type: Grant
    Filed: May 18, 2018
    Date of Patent: June 2, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventor: Bo-Tsung Tsai
  • Patent number: 10651139
    Abstract: A semiconductor die has active circuits formed on its active surface. Contact pads are formed on the active surface of the semiconductor die and coupled to the active circuits. A die extension region is formed around a periphery of the semiconductor die. Conductive THVs are formed in the die extension region. A wafer level conductive plane or ring is formed on a center area of the active surface. The conductive plane or ring is connected to a first contact pad to provide a first power supply potential to the active circuits, and is electrically connected to a first conductive THV. A conductive ring is formed partially around a perimeter of the conductive plane or ring and connected to a second contact pad for providing a second power supply potential to the active circuits. The conductive ring is electrically connected to a second THV.
    Type: Grant
    Filed: June 8, 2016
    Date of Patent: May 12, 2020
    Assignee: JCET Semiconductor (Shaoxing) Co., Ltd.
    Inventors: Guruprasad G. Badakere, Zigmund R. Camacho, Lionel Chien Hui Tay
  • Patent number: 10622292
    Abstract: A substrate that includes a first substrate portion, a second substrate portion and a second dielectric layer. The first substrate portion includes a core layer having a first core surface, and a plurality of core substrate interconnects, wherein the plurality of core substrate interconnects includes a plurality of surface core substrate interconnects formed over the first surface of core layer. The second substrate portion includes a first dielectric layer having a first dielectric surface, the first dielectric surface facing the first core surface of the core layer, and a plurality of substrate interconnects, wherein the plurality of substrate interconnects includes a plurality of interconnects formed over the first dielectric surface. The second dielectric layer is formed between the first substrate portion and the second substrate portion such that the plurality of surface core substrate interconnects and the plurality of substrate interconnects are located in the second dielectric layer.
    Type: Grant
    Filed: November 13, 2018
    Date of Patent: April 14, 2020
    Assignee: QUALCOMM Incorporated
    Inventors: Kuiwon Kang, Houssam Jomaa
  • Patent number: 10535698
    Abstract: The present disclosure relates to an image sensor with a pad structure formed during a front-end-of-line process. The pad structure can be formed prior to formation of back side deep trench isolation structures and metal grid structures. An opening is formed on a back side of the image sensor device to expose the embedded pad structure and to form electrical connections.
    Type: Grant
    Filed: February 28, 2018
    Date of Patent: January 14, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yun-Wei Cheng, Chun-Hao Chou, Kuo-Cheng Lee, Hsun-Ying Huang, Yin-Chieh Huang
  • Patent number: 10529736
    Abstract: In some embodiments, 3-dimensional semiconductor memory device includes a semiconductor substrate extending horizontally in a first direction and a second direction crossing the first direction. A stacked memory cell array is formed on the semiconductor substrate. The memory device further includes a separation pattern including a plurality of separation lines extending in the first direction and arranged in the second direction, and dividing the stacked memory cell array into a plurality of memory cell structures extending in the first direction and arranged in the second direction. An upper insulating layer is formed above the plurality of memory cell structures and separation lines, and a passivation layer is formed above the upper insulating layer. The passivation layer includes a plurality of first regions having a first vertical thickness. A plurality of gap regions in the passivation layer are formed between the plurality of first regions.
    Type: Grant
    Filed: September 21, 2018
    Date of Patent: January 7, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Min Sung Song, Heung Jin Joo, Kwan Yong Kim, Jin Woo Park, Du Heon Song, He Jueng Lee, Myung Ho Jung
  • Patent number: 10522585
    Abstract: A semiconductor device includes a substrate, a conductive layer, a transparent layer, a transparent hard mask layer, a carrier, and a device layer. The substrate has a first surface and a second surface opposite to each other. The conductive layer is disposed on the first surface of the substrate. The transparent layer is disposed on the conductive layer. The transparent hard mask layer is disposed on the transparent layer, in which the substrate has an etch selectivity with respect to the transparent hard mask layer. The device layer is disposed between the carrier and the second surface of the substrate, in which various portions of the device layer are respectively exposed by various through holes which pass through the transparent hard mask layer, the transparent layer, the conductive layer, and the substrate.
    Type: Grant
    Filed: April 17, 2017
    Date of Patent: December 31, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yi-Fang Yang, Yi-Hung Chen, Keng-Ying Liao, Yi-Jie Chen, Shih-Hsun Hsu, Chun-Chi Lee
  • Patent number: 10475668
    Abstract: A method includes placing a semiconductor substrate on a first curved surface of a first bending tool, using a second bending tool with a second surface to apply pressure to the semiconductor substrate, thereby pressing the semiconductor substrate onto the first curved surface and bending the semiconductor substrate, and removing the bended semiconductor substrate from the first bending tool.
    Type: Grant
    Filed: June 28, 2018
    Date of Patent: November 12, 2019
    Assignee: Infineon Technologies AG
    Inventors: Andre Wedi, Guido Boenig, Niels Oeschler, Christian Stahlhut
  • Patent number: 10453887
    Abstract: The present disclosure relates to a solid-state image sensing device, a manufacturing method, and an electronic apparatus, in which surface roughness on a wiring surface can be suppressed. In redistribution layer forming processing, a Ti/Cu film corresponds to a barrier layer and a seed layer is formed by Ti/Cu sputtering after opening a through-silicon via. At this point, actually, degassing heating, reverse sputtering, Ti deposition, and Seed-Cu deposition are sequentially performed. As a method of depositing a Seed-Cu film having high crystallinity in deposition of the Seed-Cu film, performing deposition by increasing a substrate temperature to a high temperature is one method, and the Seed-Cu film of Cu(111)/(200) is formed by performing deposition at the substrate temperature of 60 degrees or more, and Cu haze are suppressed. The present disclosure can be applied to a CMOS solid-state image sensing device used as an imaging device such as a camera.
    Type: Grant
    Filed: June 24, 2016
    Date of Patent: October 22, 2019
    Assignee: SONY CORPORATION
    Inventor: Shingo Takahashi
  • Patent number: 10312424
    Abstract: Disclosed herein are a semiconductor light emitting element and a backlight assembly including the same. The semiconductor light emitting element includes: a light emitting element chip including a first pad and a second pad and having an upper surface and a side surface; a wavelength conversion layer famed on the upper surface and the side surface of the light emitting element chip; a sidewall reflection part famed to be spaced apart from the side surface of the light emitting element chip; and a bottom surface reflection part famed to protrude at a lower portion of the sidewall reflection part. The sidewall reflection part and the bottom surface reflection part of the light emitting element are configured to reflect light in a direction in which the light penetrates through an upper surface of the wavelength conversion layer, the light being generated from the light emitting element chip.
    Type: Grant
    Filed: March 7, 2017
    Date of Patent: June 4, 2019
    Assignee: LUMENS CO., LTD.
    Inventors: Seung Hyun Oh, Yun Geon Cho, Bo Gyun Kim, Suk Min Han, Jun Hyeok Han, In Woo Son
  • Patent number: 10304899
    Abstract: A solid-state imaging device includes: a first semiconductor substrate including a photoelectric conversion element; and a second semiconductor substrate including at least a part of a peripheral circuit arranged in a main face of the second semiconductor substrate, the peripheral circuit generating a signal based on the charge of the photoelectric conversion element, a main face of the first semiconductor substrate and the main face of the second semiconductor substrate being opposed to each other with sandwiching a wiring structure therebetween; a pad to be connected to an external terminal; and a protection circuit electrically connected to the pad and to the peripheral circuit, wherein the protection circuit is arranged in the main face of the second semiconductor substrate.
    Type: Grant
    Filed: January 11, 2018
    Date of Patent: May 28, 2019
    Assignee: CANON KABUSHIKI KAISHA
    Inventors: Masahiro Kobayashi, Mineo Shimotsusa
  • Patent number: 10276734
    Abstract: The present invention relates to plasmonic components, more particularly plasmonic waveguides, and to plasmonic photodetectors that can be used in the field of microoptics and nanooptics, more particularly in highly integrated optical communications systems in the infrared range (IR range) as well as in power engineering, e.g. photovoltaics in the visible range. The present invention also specifies a method for producing a plasmonic component, more particularly for photodetection on the basis of internal photoemission.
    Type: Grant
    Filed: May 27, 2015
    Date of Patent: April 30, 2019
    Assignee: Karlsruher Institut Für Technologie
    Inventors: Sascha Mühlbrandt, Jürg Leuthold, Manfred Kohl
  • Patent number: 10217787
    Abstract: A backside illuminated image sensor includes a photodiode arranged in a substrate, a first insulating layer arranged on a front surface of the substrate, a bonding pad arranged on the first insulating layer, and a second insulating layer arranged on the first insulating layer and the bonding pad. The bonding pad is partially exposed by an opening passing through the substrate and the first insulating layer, and an edge portion of the bonding pad is supported by the first and second insulating layers.
    Type: Grant
    Filed: September 7, 2017
    Date of Patent: February 26, 2019
    Assignee: DB Hitek Co., Ltd.
    Inventor: Chang Hun Han
  • Patent number: 10141363
    Abstract: When a trench that penetrates a semiconductor substrate in a scribe region in a solid-state imaging element of a back side illumination type, occurrence of contamination of the solid-state imaging element caused by an etching step for foaming the trench or a dicing step for singulating a semiconductor chip is prevented. When a silicide layer that covers a surface and the like of an electrode of a transistor is formed, in order to prevent formation of the silicide layer that covers a main surface of the semiconductor substrate in the scribe region, the main surface of the semiconductor substrate is covered with an insulation film before a forming step for the silicide layer.
    Type: Grant
    Filed: April 16, 2017
    Date of Patent: November 27, 2018
    Assignee: Renesas Electronics Corporation
    Inventor: Hiroaki Sekikawa
  • Patent number: 10134794
    Abstract: An image sensor chip having a sidewall interconnect structure to bond and/or electrically couple the image sensor chip to a package substrate is provided. The image sensor chip includes a substrate supporting an integrated circuit (IC) configured to sense incident light. The sidewall interconnect structure is arranged along a sidewall of the substrate and electrically coupled with the IC. A method for manufacturing the image sensor chip and an image sensor package including the image sensor chip are also provided.
    Type: Grant
    Filed: April 14, 2017
    Date of Patent: November 20, 2018
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Kuo-Chin Huang, Pao-Tung Chen, Wei-Chieh Chiang, Kazuaki Hashimoto, Jen-Cheng Liu
  • Patent number: 10121821
    Abstract: Presented herein is a device including an image sensor having a plurality of pixels disposed in a substrate and configured to sense light through a back side of the substrate and an RDL disposed on a front side of the substrate and having a plurality of conductive elements disposed in one or more dielectric layers. A sensor shield is disposed over the back side of the substrate and extending over the image sensor. At least one via contacts the sensor shield and extends from the sensor shield through at least a portion of the RDL and contacts at least one of the plurality of conductive elements.
    Type: Grant
    Filed: April 3, 2017
    Date of Patent: November 6, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shyh-Fann Ting, Feng-Chi Hung, Jhy-Jyi Sze, Ching-Chun Wang, Dun-Nian Yaung
  • Patent number: 9992863
    Abstract: Connector inserts and other structures that have a high signal integrity and low insertion loss, are reliable, and are readily manufactured. One example may provide a connector insert formed primarily using a printed circuit board. Contacts on the connector insert may be akin to contacts on a printed circuit board and they may connect to traces having matched impedances on the printed circuit board in order to improve signal integrity and reduce insertion loss. The printed circuit board may be manufactured in a manner for increased reliability. Plating, solder block, and other manufacturing steps that are native to printed circuit board manufacturing may be employed to improve manufacturability. Specialized tools that may provide a chamfered edge on the connector inserts may be employed.
    Type: Grant
    Filed: August 22, 2014
    Date of Patent: June 5, 2018
    Assignee: APPLE INC.
    Inventors: Mahmoud R. Amini, Zheng Gao, Dennis R. Pyper
  • Patent number: 9945734
    Abstract: A micromachined apparatus includes micromachined thermistor having first and second ends physically and thermally coupled to a substrate via first and second anchor structures to enable a temperature-dependent resistance of the micromachined thermistor to vary according to a time-varying temperature of the substrate. The micromachined thermistor has a length, from the first end to the second end, greater than a linear distance between the first and second anchor structures.
    Type: Grant
    Filed: May 22, 2017
    Date of Patent: April 17, 2018
    Assignee: SiTime Corporation
    Inventors: Carl Arft, Aaron Partridge, Paul M. Hagelin
  • Patent number: 9887162
    Abstract: A method in which microelectronic devices are attached to a substrate surface, wherein spaces interpose neighboring ones of the microelectronic devices. Each microelectronic device has an outermost surface that is substantially parallel to the substrate surface. The substrate is closed in a transfer molding cavity of a transfer molding apparatus such that an internal surface of the transfer molding cavity contacts a substantial portion of each of the outermost surfaces of the microelectronic devices. A molding compound is subsequently injected into the transfer molding cavity, including into the spaces between ones of the plurality of microelectronic devices.
    Type: Grant
    Filed: March 25, 2014
    Date of Patent: February 6, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Hua Yu, Chung-Shi Liu, Chih-Fan Huang, Hui-Min Huang, Wei-Hung Lin, Ming-Da Cheng
  • Patent number: 9881892
    Abstract: An integrated circuit device including a semiconductor substrate, a first bonding pad structure, a second bonding pad structure, a third bonding pad structure, a first internal bonding wire, and a second internal bonding wire is provided. The first bonding pad structure is disposed on a surface of the semiconductor substrate and exposed outside of the semiconductor substrate. The second bonding pad structure is disposed on the surface of the semiconductor substrate and exposed outside of the semiconductor substrate. The third bonding pad structure is disposed on the surface of the semiconductor substrate and exposed outside of the semiconductor substrate. The first bonding pad structure is electrically coupled to the third bonding pad structure via the first internal bonding wire. The third bonding pad structure is electrically coupled to the second bonding pad structure via the second internal bonding wire.
    Type: Grant
    Filed: January 23, 2017
    Date of Patent: January 30, 2018
    Assignee: Novatek Microelectronics Corp.
    Inventors: Jung-Fu Hsu, Tai-Hung Lin, Chang-Tien Tsai
  • Patent number: 9865713
    Abstract: The interplay between chiral tunneling and spin-momentum locking of helical surface states leads to spin amplification and filtering in a 3D Topological Insulator (TI). Chiral tunneling across a TI pn junction allows normally incident electrons to transmit, while the rest are reflected with their spins flipped due to spin-momentum locking. The net result is that the spin current is enhanced while the dissipative charge current is simultaneously suppressed, leading to an extremely large, tunable longitudinal spin Hall angle (˜20) at the reflected end. At the transmitted end, the angle stays close to one and the electrons are completely spin polarized.
    Type: Grant
    Filed: September 30, 2015
    Date of Patent: January 9, 2018
    Assignee: UNIVERSITY OF VIRGINIA PATENT FOUNDATION
    Inventors: K. M. Masum Habib, Redwan Noor Sajjad, Avik Ghosh
  • Patent number: 9859320
    Abstract: A chip package includes a chip, an insulating layer and a conductive layer. The chip includes a substrate, an epitaxy layer, a device region and a conductive pad. The epitaxy layer is disposed on the substrate, and the device region and the conductive pad are disposed on the epitaxy layer. The conductive pad is at a side of the device region and connected to the device region. The conductive pad protrudes out of a side surface of the epitaxy layer. The insulating layer is disposed below the substrate and extended to cover the side surface of the epitaxy layer. The conductive layer is disposed below the insulating layer and extended to contact the conductive pad. The conductive layer and the side surface of the epitaxy layer are separated by a first distance.
    Type: Grant
    Filed: December 28, 2016
    Date of Patent: January 2, 2018
    Assignee: XINTEC INC.
    Inventors: Shun-Wen Long, Guo-Jyun Chiou, Meng-Han Kuo, Ming-Chieh Huang, Hsi-Chien Lin, Chin-Kang Chen, Yi-Pin Chen
  • Patent number: 9853075
    Abstract: An image sensor is provided. The image sensor includes a substrate, a first interlayer insulating layer, a first metal line, and a shielding structure. The substrate includes a pixel array, a peripheral circuit area, and an interface area disposed between the pixel array and the peripheral circuit area. The first interlayer insulating layer is formed on a first surface of the substrate. The first metal line is disposed on the first interlayer insulating layer of the pixel array. The second interlayer insulating layer is disposed on the first interlayer insulating layer wherein the second interlayer insulating layer covers the first metal line. The shielding structure passes through the substrate in the interface area wherein the shielding structure electrically insulates the pixel array of the substrate and the peripheral circuit area.
    Type: Grant
    Filed: October 4, 2016
    Date of Patent: December 26, 2017
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Yun-Ki Lee, Chang-Rok Moon, Min-Wook Jung
  • Patent number: 9837981
    Abstract: The invention relates to a microelectromechanical resonator device comprising a support structure and a semiconductor resonator plate doped to a doping concentration with an n-type doping agent and being capable of resonating in a width-extensional resonance mode. In addition, there is at least one anchor suspending the resonator plate to the support structure and an actuator for exciting the width-extensional resonance mode into the resonator plate. According to the invention, the resonator plate is doped to a doping concentration of 1.2*1020 cm?3 or more and has a shape which, in combination with said doping concentration and in said width-extensional resonance mode, provides the second order temperature coefficient of frequency (TCF2) to be 12 ppb/C2 or less at least at one temperature. Several practical implementations are presented.
    Type: Grant
    Filed: October 5, 2015
    Date of Patent: December 5, 2017
    Assignee: Teknologian tutkimuskeskus VTT Oy
    Inventors: Antti Jaakkola, Panu Pekko, Mika Prunnila, Tuomas Pensala
  • Patent number: 9825081
    Abstract: A semiconductor device includes a substrate, a circuit layer formed on a first surface of the substrate and including a via pad and an interlayer insulating layer covering the via pad, a via structure configured to fully pass through the substrate, partially pass through the interlayer insulating layer and be in contact with the via pad, a via isolation insulating layer configured to pass through the substrate and be spaced apart from outer side surfaces of the via structure in a horizontal direction and a pad structure buried in the substrate and exposed on a second surface of the substrate opposite the first surface of the substrate.
    Type: Grant
    Filed: August 5, 2016
    Date of Patent: November 21, 2017
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Taeseok Oh, Junetaeg Lee, Seung-Hun Shin, Jaesang Yoo
  • Patent number: 9823362
    Abstract: The present invention provides a radiation detector UBM electrode structure body and a radiation detector which suppress the degradation of metal electrode layers at the time of formation of UBM layers and achieve sufficient electric characteristics, and a method of manufacturing the same. A radiation detector UBM electrode structure body according to the present invention includes a substrate made of CdTe or CdZnTe, comprising a Pt or Au electrode layer formed on the substrate by electroless plating, an Ni layer formed on the Pt or Au electrode layer by sputtering, and an Au layer formed on the Ni layer by sputtering.
    Type: Grant
    Filed: December 27, 2016
    Date of Patent: November 21, 2017
    Assignee: JX NIPPON MINING & METALS CORPORATION
    Inventors: Masaomi Murakami, Makoto Mikami, Kouji Murakami, Akira Noda, Toru Imori
  • Patent number: 9778129
    Abstract: A hermetically-sealed universal pressure sensor comprises a MEMS disk, a compensate disk, and an optional interconnect ring. The MEMS disk has one or more MEMS dies that can convert ambient pressures to electrical signals, which is processed and compensated at an integrated circuit on the compensate disk. The interconnect ring can optionally provide electrical connections and hermetic seal properties between the MEMS disk and the compensate disk.
    Type: Grant
    Filed: August 3, 2015
    Date of Patent: October 3, 2017
    Assignee: DUNAN SENSING, LLC
    Inventor: John She Bai
  • Patent number: 9748511
    Abstract: The invention relates to a light-emitting device like an OLED comprising a light emission region between an anode (5) and a cathode (6). An alternating arrangement (9) of anode pads (11) for electrically connecting the anode and cathode pads (10) for electrically connecting the cathode and an encapsulation (8) are configured such that the anode and cathode pads are electrically connectable by straight anode and cathode electrical connectors (3, 4) through openings (12) of the encapsulation. The alternating arrangement of the anode and cathode pads can lead to a more homogenous electrical field between the anode and the cathode and therefore allows for an improved degree of homogeneity of light emission. More, since the alternating arrangement of the anode and cathode pads is connectable by corresponding straight connectors, the contacting of the pads can be performed technically relatively easily.
    Type: Grant
    Filed: May 22, 2014
    Date of Patent: August 29, 2017
    Assignee: OLEDWORKS GMBH
    Inventor: Christoph Rickers
  • Patent number: 9741759
    Abstract: Image sensor and method of manufacturing the same are provided. The image sensor includes a semiconductor substrate including a pixel area, a voltage connection area, and a pad area, a plurality of photoelectric conversion devices in the pixel area, an anti-reflective layer on a back side of the semiconductor substrate and on the plurality of photoelectric conversion devices, a device isolation structure between the plurality of photoelectric conversion devices, at least one voltage connection structure in the voltage connection area, and electrically connected to the device isolation structure, at least one voltage applying device electrically connected to the at least one voltage connection structure, an internal circuit including at least one conductive inner wire and at least one conductive inner via in an insulating layer, and a through via structure in the pad area.
    Type: Grant
    Filed: June 1, 2016
    Date of Patent: August 22, 2017
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Jung-Ho Park
  • Patent number: 9716069
    Abstract: A semiconductor substrate includes: an alignment mark being formed of a material that reflects a detection light for detecting positions and having a detection edge portion; a light-shielding layer portion having a larger outer shape than the alignment mark, being formed of a material that shields the detection light, and being disposed at a position on a backside of the alignment mark when seen from an incidence side of the detection light; and one or more light-transmitting layer portions being laminated between the alignment mark and the light-shielding layer portion so as to transmit the detection light and not being patterned at least in a range that overlaps the light-shielding layer portion.
    Type: Grant
    Filed: August 10, 2015
    Date of Patent: July 25, 2017
    Assignee: OLYMPUS CORPORATION
    Inventors: Naohiro Takazawa, Yoshiaki Takemoto
  • Patent number: 9699907
    Abstract: A semiconductor package module may include a first substrate, and a second substrate disposed to face the first substrate. The semiconductor package module may include an interconnection member electrically connecting the first substrate to the second substrate and including a plurality of wires. Portions of the plurality of wires may be twisted and wound together and may be bent to extend in a predetermined direction.
    Type: Grant
    Filed: July 30, 2015
    Date of Patent: July 4, 2017
    Assignee: SK hynix Inc.
    Inventor: Jung Tae Jeong
  • Patent number: 9691749
    Abstract: A semiconductor structure less affected by stress and a method for forming the same are provided. The semiconductor structure includes a semiconductor chip. Stress-sensitive circuits are substantially excluded out of an exclusion zone to reduce the effects of the stress to the stress-sensitive circuits. The stress-sensitive circuits include analog circuits. The exclusion zone preferably includes corner regions of the semiconductor chip, wherein the corner regions preferably have a diagonal length of less than about one percent of the diagonal length of the semiconductor chip. The stress-sensitive analog circuits preferably include devices having channel lengths less than about five times the minimum channel length.
    Type: Grant
    Filed: August 12, 2014
    Date of Patent: June 27, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chao-Yuan Su, Chung-Yi Lin
  • Patent number: 9677948
    Abstract: A micromachined apparatus includes micromachined thermistor having first and second ends physically and thermally coupled to a substrate via first and second anchor structures to enable a temperature-dependent resistance of the micromachined thermistor to vary according to a time-varying temperature of the substrate. The micromachined thermistor has a length, from the first end to the second end, greater than a linear distance between the first and second anchor structures.
    Type: Grant
    Filed: April 8, 2015
    Date of Patent: June 13, 2017
    Assignee: SiTime Corporation
    Inventors: Carl Arft, Aaron Partridge, Paul M. Hagelin
  • Patent number: 9666630
    Abstract: Semiconductor devices, methods of manufacturing thereof, and image sensor devices are disclosed. In some embodiments, a semiconductor device comprises a semiconductor chip comprising an array region, a periphery region, and a through-via disposed therein. The semiconductor device comprises a guard structure disposed in the semiconductor chip between the array region and the through-via or between the through-via and a portion of the periphery region.
    Type: Grant
    Filed: March 10, 2016
    Date of Patent: May 30, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chun-Chieh Chuang, Dun-Nian Yaung, Jen-Cheng Liu, Tzu-Hsuan Hsu, Feng-Chi Hung, Min-Feng Kao
  • Patent number: 9659895
    Abstract: Disclosed is a semiconductor package structure comprising a body, a plurality of first-layer, second-layer, third-layer and fourth-layer electrical contacts, wherein the first-layer, the second-layer, the third-layer and the fourth-layer electrical contacts are arranged sequentially from outside to inside on a bottom surface of the body in a matrix manner. Adjacent first-layer electrical contacts have two different spacings therein, and adjacent third-layer electrical contacts have the two different spacings therein.
    Type: Grant
    Filed: June 28, 2016
    Date of Patent: May 23, 2017
    Assignee: Intel Corporation
    Inventor: Xinhua Wang
  • Patent number: 9635291
    Abstract: There is provided an image capturing apparatus capable of controlling focus detecting pixels independently of the remaining image capturing pixels while maintaining the sensitivity of an image sensor and obtaining high image quality. The image capturing apparatus includes a first semiconductor chip, and a second semiconductor chip stacked on the first semiconductor chip. On the first semiconductor chip, the light receiving sections of a first pixel group and second pixel group, and a first pixel driving circuit configured to drive the pixels of the first pixel group are arranged. On the second semiconductor chip, a second pixel driving circuit configured to drive the pixels of the second pixel group is arranged.
    Type: Grant
    Filed: November 25, 2014
    Date of Patent: April 25, 2017
    Assignee: Canon Kabushiki Kaisha
    Inventor: Mineo Uchida
  • Patent number: 9583526
    Abstract: A solid-state image pickup element is provided with a semiconductor substrate having a photosensitive region, a plurality of first electrode pads arrayed on a principal face of the semiconductor substrate, a plurality of second electrode pads arrayed in a direction along a direction in which the plurality of first electrode pads are arrayed, on the principal face of the semiconductor substrate, and a plurality of interconnections connecting the plurality of first electrode pads and the plurality of second electrode pads in one-to-one correspondence. The plurality of interconnections connect the first and second electrode pads so that each interconnection connects the first electrode pad and the second electrode pad in a positional relation of line symmetry with respect to a center line perpendicular to the array directions of the plurality of first and second electrode pads.
    Type: Grant
    Filed: June 19, 2012
    Date of Patent: February 28, 2017
    Assignee: HAMAMATSU PHOTONICS K.K.
    Inventors: Tomohiro Ikeya, Toshiyuki Fukui, Hisanori Suzuki, Masaharu Muramatsu
  • Patent number: 9484209
    Abstract: A material removal process referred to as spalling is used to provide flexible and stretchable sensors that can be used for healthcare monitoring, bio-medical devices, wearable electronic devices, artificial skin, large area sensing, etc. The flexible and stretchable sensors of the present application have high sensitivity that is comparable to that of a bulk silicon sensor. The flexible and stretchable sensors comprise single crystalline spring-like structures that couple various resistor structures together.
    Type: Grant
    Filed: November 20, 2015
    Date of Patent: November 1, 2016
    Assignee: International Business Machines Corporation
    Inventors: Stephen W. Bedell, Shu-Jen Han, Ning Li, Devendra K. Sadana
  • Patent number: 9409764
    Abstract: An MEMS component includes: a substrate into which a cavity is structured from a functional top side; a buried polysilicon layer in which a polysilicon diaphragm which at least partially spans the cavity is exposed as the first electrode; an epi-polysilicon layer in which a conductive structure, which is situated at a distance above the polysilicon diaphragm by a clearance, is exposed as the second electrode; and an access opening which fluidically connects the external surroundings of the MEMS component to the cavity. At least one access channel is formed in at least one of the buried polysilicon layer, the epi-polysilicon layer, and an inner wall of the cavity of the substrate which connects the access opening to the cavity, and whose channel width is not greater than 5 ?m.
    Type: Grant
    Filed: July 23, 2015
    Date of Patent: August 9, 2016
    Assignee: ROBERT BOSCH GMBH
    Inventor: Jochen Reinmuth
  • Patent number: 9390215
    Abstract: A rectangular interlevel connector array (RICA) is defined in a semiconductor chip. To define the RICA, a virtual grid for interlevel connector placement is defined to include a first set of parallel virtual lines that extend across the layout in a first direction, and a second set of parallel virtual lines that extend across the layout in a second direction perpendicular to the first direction. A first plurality of interlevel connector structures are placed at respective gridpoints in the virtual grid to form a first RICA. The first plurality of interlevel connector structures of the first RICA are placed to collaboratively connect a first conductor channel in a first chip level with a second conductor channel in a second chip level. A second RICA can be interleaved with the first RICA to collaboratively connect third and fourth conductor channels that are respectively interleaved with the first and second conductor channels.
    Type: Grant
    Filed: June 6, 2014
    Date of Patent: July 12, 2016
    Assignee: Tela Innovations, Inc.
    Inventors: Daryl Fox, Scott T. Becker
  • Patent number: 9373656
    Abstract: Image sensor and method of manufacturing the same are provided. The image sensor includes a semiconductor substrate including a pixel area, a voltage connection area, and a pad area, a plurality of photoelectric conversion devices in the pixel area, an anti-reflective layer on a back side of the semiconductor substrate and on the plurality of photoelectric conversion devices, a device isolation structure between the plurality of photoelectric conversion devices, at least one voltage connection structure in the voltage connection area, and electrically connected to the device isolation structure, at least one voltage applying device electrically connected to the at least one voltage connection structure, an internal circuit including at least one conductive inner wire and at least one conductive inner via in an insulating layer, and a through via structure in the pad area.
    Type: Grant
    Filed: December 22, 2014
    Date of Patent: June 21, 2016
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Jung-Ho Park
  • Patent number: 9362456
    Abstract: An optoelectronic semiconductor device includes a substrate, a semiconductor system having an active layer formed on the substrate and an electrode structure formed on the semiconductor system, wherein the layout of the electrode structure having at least a first conductivity type contact zone or a first conductivity type bonding pad, a second conductivity type bonding pad, a first conductivity type extension electrode, and a second conductivity type extension electrode wherein the first conductivity type extension electrode and the second conductivity type extension electrode have three-dimensional crossover, and partial of the first conductivity type extension electrode and the first conductivity type contact zone or the first conductivity type bonding pad are on the opposite sides of the active layer.
    Type: Grant
    Filed: September 24, 2012
    Date of Patent: June 7, 2016
    Assignee: EPISTAR CORPORATION
    Inventors: Wei-Yo Chen, Yen-Wen Chen, Chien-Yuan Wang, Min-Hsun Hsieh, Tzer-Perng Chen
  • Patent number: 9312292
    Abstract: A manufacturing method of a BSI image sensor includes providing a substrate having a plurality of photo-sensing elements and a plurality of multilevel interconnects formed on a first side of the substrate; forming a redistribution layer (RDL) and a first insulating layer covering the RDL on the front side of the substrate; providing a carrier wafer formed on the front side of the substrate; forming a color filter array (CFA) on a second side of the substrate, the second side being opposite to the first side; removing the carrier wafer; and forming a first opening in the first insulating layer for exposing the RDL.
    Type: Grant
    Filed: October 26, 2011
    Date of Patent: April 12, 2016
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventor: Ching-Hung Kao
  • Patent number: 9269723
    Abstract: A method of making a logic gate array includes providing a substrate; forming an array of first conductive lines with plurality of first pads disposed on each of the first conductive lines on the substrate wherein the array of first conductive lines is disposed in a first direction; forming an array of isolation lines over the first conductive lines wherein the isolation lines are not disposed on the first pads; forming an array of second conductive lines with plurality of second pads disposed on each of the second conductive lines on the substrate wherein the array of second conductive lines is disposed in a second direction and wherein orientation of the second direction is different than the orientation of the first direction; and printing one or more conductive ink dots at least one intersection of the first conductive lines and the second conductive lines by connecting the corresponding first pads and corresponding second pads.
    Type: Grant
    Filed: April 9, 2014
    Date of Patent: February 23, 2016
    Assignee: EASTMAN KODAK COMPANY
    Inventor: Gil Bellaiche
  • Patent number: 9265143
    Abstract: A logic gate array includes a substrate; an array of first conductive lines with plurality of first pads disposed on each of the first conductive lines on the substrate wherein the array of first conductive lines is disposed in a first direction; an array of isolation lines over the first conductive lines wherein the isolation lines are not disposed on the first pads; an array of second conductive lines with plurality of second pads disposed on each of the second conductive lines on the substrate wherein the array of first conductive lines is disposed in a second direction and wherein orientation of the second direction is oriented is different than the orientation of the first direction; and conductive ink dots printed on at least some of the intersection of the first conductive lines and the second conductive lines by connecting the corresponding first pads and corresponding second pads.
    Type: Grant
    Filed: April 9, 2014
    Date of Patent: February 16, 2016
    Assignee: EASTMAN KODAK COMPANY
    Inventor: Gil Bellaiche
  • Patent number: 9252180
    Abstract: A bonding pad structure for an image sensor device and a method of fabrication thereof. The image sensor device has a radiation-sensor region including a substrate and a radiation detection device, and a bonding pad region including the bonding pad structure. The bonding pad structure includes: an interconnect layer; an interlayer dielectric layer (IDL), both layers extending from under the substrate into the bonding pad region; an isolation layer formed on IDL; a conductive pad having a planar portion and one or more bridging portions extending perpendicularly from the planar portion, through the IDL and isolation layers, and to the interconnect layer; and a plurality of non-conducting stress-releasing structures disposed between the isolation layer and the conductive pad in such a way to adjoin its planar and the bridging portions together for releasing potential pulling stress applied thereon and preventing a conductive pad peeling.
    Type: Grant
    Filed: February 8, 2013
    Date of Patent: February 2, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Volume Chien, I-Chih Chen, Ying-Lang Wang, Hsin-Chi Chen, Ying-Hao Chen, Hung-Ta Huang
  • Patent number: 9224851
    Abstract: A device and method of fabricating a device in the form of an array of planarized particles of single crystal silicon or poly crystal silicon wherein the planar surfaces of the particles is used to fabricate an array of electronic devices. This is particularly useful in the manufacture of large displays where single crystal high speed devices are required. The planar surfaces of the array of devices are coplanar when the array is fabricated on a planar substrate.
    Type: Grant
    Filed: October 12, 2012
    Date of Patent: December 29, 2015
    Assignee: DIFTEK LASERS, INC.
    Inventor: Douglas R. Dykaar
  • Patent number: 9184207
    Abstract: An image sensor device includes a semiconductor substrate having a front side and a backside. A first dielectric layer is on the front side of the semiconductor substrate. A metal pad is in the first dielectric layer. A second dielectric layer is over the first dielectric layer and on the front side of the semiconductor substrate. An opening penetrates through the semiconductor substrate from the backside of the semiconductor substrate, wherein the opening includes a first portion extending to expose a portion of the metal pad and a second portion extending to expose a portion of the second dielectric layer. A metal layer is formed in the first portion and the second portion of the opening.
    Type: Grant
    Filed: March 23, 2015
    Date of Patent: November 10, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jeng-Shyan Lin, Dun-Nian Yaung, Jen-Cheng Liu, Wen-De Wang, Shuang-Ji Tsai, Yueh-Chiou Lin
  • Patent number: 9123839
    Abstract: Among other things, one or more image sensors and techniques for guiding light towards a photodiode are provided. An image sensor comprises a metal grid configured to direct light towards a corresponding photodiode and away from other photodiodes. The image sensor also comprises a dielectric grid and a filler grid over the metal grid to direct light towards the corresponding photodiode and away from other photodiodes, where the filler grid has a different refractive index than the dielectric grid. In this way, crosstalk, otherwise resulting from detection of light by incorrect photodiodes, is mitigated.
    Type: Grant
    Filed: March 13, 2013
    Date of Patent: September 1, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Yun-Wei Cheng, Volume Chien, Chao Chih-Kang, Chi-Cherng Jeng, Chen Hsin-Chi
  • Patent number: 9117880
    Abstract: A semiconductor wafer is subjected to a protection film formation step process as a process before evaluation of electrical characteristics. In this process, after an insulating film serving as a protection film is formed, a photolithography process and an etching process are performed so as to form a protection film having a plurality of openings exposing an emitter electrode. Then, electrical characteristics are evaluated by bringing a contact probe in contact with the exposed emitter electrode through each opening.
    Type: Grant
    Filed: February 24, 2014
    Date of Patent: August 25, 2015
    Assignee: Mitsubishi Electric Corporation
    Inventors: Hajime Akiyama, Akira Okada, Kinya Yamashita