Abstract: The present invention provides a radiation detector UBM electrode structure body and a radiation detector which suppress the degradation of metal electrode layers at the time of formation of UBM layers and achieve sufficient electric characteristics, and a method of manufacturing the same. A radiation detector UBM electrode structure body according to the present invention includes a substrate made of CdTe or CdZnTe, comprising a Pt or Au electrode layer formed on the substrate by electroless plating, an Ni layer formed on the Pt or Au electrode layer by sputtering, and an Au layer formed on the Ni layer by sputtering.

Abstract: A hermetically-sealed universal pressure sensor comprises a MEMS disk, a compensate disk, and an optional interconnect ring. The MEMS disk has one or more MEMS dies that can convert ambient pressures to electrical signals, which is processed and compensated at an integrated circuit on the compensate disk. The interconnect ring can optionally provide electrical connections and hermetic seal properties between the MEMS disk and the compensate disk.

Abstract: The invention relates to a light-emitting device like an OLED comprising a light emission region between an anode (5) and a cathode (6). An alternating arrangement (9) of anode pads (11) for electrically connecting the anode and cathode pads (10) for electrically connecting the cathode and an encapsulation (8) are configured such that the anode and cathode pads are electrically connectable by straight anode and cathode electrical connectors (3, 4) through openings (12) of the encapsulation. The alternating arrangement of the anode and cathode pads can lead to a more homogenous electrical field between the anode and the cathode and therefore allows for an improved degree of homogeneity of light emission. More, since the alternating arrangement of the anode and cathode pads is connectable by corresponding straight connectors, the contacting of the pads can be performed technically relatively easily.

Abstract: Image sensor and method of manufacturing the same are provided. The image sensor includes a semiconductor substrate including a pixel area, a voltage connection area, and a pad area, a plurality of photoelectric conversion devices in the pixel area, an anti-reflective layer on a back side of the semiconductor substrate and on the plurality of photoelectric conversion devices, a device isolation structure between the plurality of photoelectric conversion devices, at least one voltage connection structure in the voltage connection area, and electrically connected to the device isolation structure, at least one voltage applying device electrically connected to the at least one voltage connection structure, an internal circuit including at least one conductive inner wire and at least one conductive inner via in an insulating layer, and a through via structure in the pad area.

Abstract: A semiconductor substrate includes: an alignment mark being formed of a material that reflects a detection light for detecting positions and having a detection edge portion; a light-shielding layer portion having a larger outer shape than the alignment mark, being formed of a material that shields the detection light, and being disposed at a position on a backside of the alignment mark when seen from an incidence side of the detection light; and one or more light-transmitting layer portions being laminated between the alignment mark and the light-shielding layer portion so as to transmit the detection light and not being patterned at least in a range that overlaps the light-shielding layer portion.

Abstract: A semiconductor package module may include a first substrate, and a second substrate disposed to face the first substrate. The semiconductor package module may include an interconnection member electrically connecting the first substrate to the second substrate and including a plurality of wires. Portions of the plurality of wires may be twisted and wound together and may be bent to extend in a predetermined direction.

Abstract: A semiconductor structure less affected by stress and a method for forming the same are provided. The semiconductor structure includes a semiconductor chip. Stress-sensitive circuits are substantially excluded out of an exclusion zone to reduce the effects of the stress to the stress-sensitive circuits. The stress-sensitive circuits include analog circuits. The exclusion zone preferably includes corner regions of the semiconductor chip, wherein the corner regions preferably have a diagonal length of less than about one percent of the diagonal length of the semiconductor chip. The stress-sensitive analog circuits preferably include devices having channel lengths less than about five times the minimum channel length.

Abstract: A micromachined apparatus includes micromachined thermistor having first and second ends physically and thermally coupled to a substrate via first and second anchor structures to enable a temperature-dependent resistance of the micromachined thermistor to vary according to a time-varying temperature of the substrate. The micromachined thermistor has a length, from the first end to the second end, greater than a linear distance between the first and second anchor structures.

Abstract: Semiconductor devices, methods of manufacturing thereof, and image sensor devices are disclosed. In some embodiments, a semiconductor device comprises a semiconductor chip comprising an array region, a periphery region, and a through-via disposed therein. The semiconductor device comprises a guard structure disposed in the semiconductor chip between the array region and the through-via or between the through-via and a portion of the periphery region.

Abstract: Disclosed is a semiconductor package structure comprising a body, a plurality of first-layer, second-layer, third-layer and fourth-layer electrical contacts, wherein the first-layer, the second-layer, the third-layer and the fourth-layer electrical contacts are arranged sequentially from outside to inside on a bottom surface of the body in a matrix manner. Adjacent first-layer electrical contacts have two different spacings therein, and adjacent third-layer electrical contacts have the two different spacings therein.

Abstract: There is provided an image capturing apparatus capable of controlling focus detecting pixels independently of the remaining image capturing pixels while maintaining the sensitivity of an image sensor and obtaining high image quality. The image capturing apparatus includes a first semiconductor chip, and a second semiconductor chip stacked on the first semiconductor chip. On the first semiconductor chip, the light receiving sections of a first pixel group and second pixel group, and a first pixel driving circuit configured to drive the pixels of the first pixel group are arranged. On the second semiconductor chip, a second pixel driving circuit configured to drive the pixels of the second pixel group is arranged.

Abstract: A solid-state image pickup element is provided with a semiconductor substrate having a photosensitive region, a plurality of first electrode pads arrayed on a principal face of the semiconductor substrate, a plurality of second electrode pads arrayed in a direction along a direction in which the plurality of first electrode pads are arrayed, on the principal face of the semiconductor substrate, and a plurality of interconnections connecting the plurality of first electrode pads and the plurality of second electrode pads in one-to-one correspondence. The plurality of interconnections connect the first and second electrode pads so that each interconnection connects the first electrode pad and the second electrode pad in a positional relation of line symmetry with respect to a center line perpendicular to the array directions of the plurality of first and second electrode pads.

Abstract: A material removal process referred to as spalling is used to provide flexible and stretchable sensors that can be used for healthcare monitoring, bio-medical devices, wearable electronic devices, artificial skin, large area sensing, etc. The flexible and stretchable sensors of the present application have high sensitivity that is comparable to that of a bulk silicon sensor. The flexible and stretchable sensors comprise single crystalline spring-like structures that couple various resistor structures together.

Abstract: An MEMS component includes: a substrate into which a cavity is structured from a functional top side; a buried polysilicon layer in which a polysilicon diaphragm which at least partially spans the cavity is exposed as the first electrode; an epi-polysilicon layer in which a conductive structure, which is situated at a distance above the polysilicon diaphragm by a clearance, is exposed as the second electrode; and an access opening which fluidically connects the external surroundings of the MEMS component to the cavity. At least one access channel is formed in at least one of the buried polysilicon layer, the epi-polysilicon layer, and an inner wall of the cavity of the substrate which connects the access opening to the cavity, and whose channel width is not greater than 5 ?m.

Abstract: A rectangular interlevel connector array (RICA) is defined in a semiconductor chip. To define the RICA, a virtual grid for interlevel connector placement is defined to include a first set of parallel virtual lines that extend across the layout in a first direction, and a second set of parallel virtual lines that extend across the layout in a second direction perpendicular to the first direction. A first plurality of interlevel connector structures are placed at respective gridpoints in the virtual grid to form a first RICA. The first plurality of interlevel connector structures of the first RICA are placed to collaboratively connect a first conductor channel in a first chip level with a second conductor channel in a second chip level. A second RICA can be interleaved with the first RICA to collaboratively connect third and fourth conductor channels that are respectively interleaved with the first and second conductor channels.

Abstract: Image sensor and method of manufacturing the same are provided. The image sensor includes a semiconductor substrate including a pixel area, a voltage connection area, and a pad area, a plurality of photoelectric conversion devices in the pixel area, an anti-reflective layer on a back side of the semiconductor substrate and on the plurality of photoelectric conversion devices, a device isolation structure between the plurality of photoelectric conversion devices, at least one voltage connection structure in the voltage connection area, and electrically connected to the device isolation structure, at least one voltage applying device electrically connected to the at least one voltage connection structure, an internal circuit including at least one conductive inner wire and at least one conductive inner via in an insulating layer, and a through via structure in the pad area.

Abstract: An optoelectronic semiconductor device includes a substrate, a semiconductor system having an active layer formed on the substrate and an electrode structure formed on the semiconductor system, wherein the layout of the electrode structure having at least a first conductivity type contact zone or a first conductivity type bonding pad, a second conductivity type bonding pad, a first conductivity type extension electrode, and a second conductivity type extension electrode wherein the first conductivity type extension electrode and the second conductivity type extension electrode have three-dimensional crossover, and partial of the first conductivity type extension electrode and the first conductivity type contact zone or the first conductivity type bonding pad are on the opposite sides of the active layer.

Abstract: A manufacturing method of a BSI image sensor includes providing a substrate having a plurality of photo-sensing elements and a plurality of multilevel interconnects formed on a first side of the substrate; forming a redistribution layer (RDL) and a first insulating layer covering the RDL on the front side of the substrate; providing a carrier wafer formed on the front side of the substrate; forming a color filter array (CFA) on a second side of the substrate, the second side being opposite to the first side; removing the carrier wafer; and forming a first opening in the first insulating layer for exposing the RDL.

Abstract: A method of making a logic gate array includes providing a substrate; forming an array of first conductive lines with plurality of first pads disposed on each of the first conductive lines on the substrate wherein the array of first conductive lines is disposed in a first direction; forming an array of isolation lines over the first conductive lines wherein the isolation lines are not disposed on the first pads; forming an array of second conductive lines with plurality of second pads disposed on each of the second conductive lines on the substrate wherein the array of second conductive lines is disposed in a second direction and wherein orientation of the second direction is different than the orientation of the first direction; and printing one or more conductive ink dots at least one intersection of the first conductive lines and the second conductive lines by connecting the corresponding first pads and corresponding second pads.

Abstract: A logic gate array includes a substrate; an array of first conductive lines with plurality of first pads disposed on each of the first conductive lines on the substrate wherein the array of first conductive lines is disposed in a first direction; an array of isolation lines over the first conductive lines wherein the isolation lines are not disposed on the first pads; an array of second conductive lines with plurality of second pads disposed on each of the second conductive lines on the substrate wherein the array of first conductive lines is disposed in a second direction and wherein orientation of the second direction is oriented is different than the orientation of the first direction; and conductive ink dots printed on at least some of the intersection of the first conductive lines and the second conductive lines by connecting the corresponding first pads and corresponding second pads.

Abstract: A bonding pad structure for an image sensor device and a method of fabrication thereof. The image sensor device has a radiation-sensor region including a substrate and a radiation detection device, and a bonding pad region including the bonding pad structure. The bonding pad structure includes: an interconnect layer; an interlayer dielectric layer (IDL), both layers extending from under the substrate into the bonding pad region; an isolation layer formed on IDL; a conductive pad having a planar portion and one or more bridging portions extending perpendicularly from the planar portion, through the IDL and isolation layers, and to the interconnect layer; and a plurality of non-conducting stress-releasing structures disposed between the isolation layer and the conductive pad in such a way to adjoin its planar and the bridging portions together for releasing potential pulling stress applied thereon and preventing a conductive pad peeling.

Abstract: A device and method of fabricating a device in the form of an array of planarized particles of single crystal silicon or poly crystal silicon wherein the planar surfaces of the particles is used to fabricate an array of electronic devices. This is particularly useful in the manufacture of large displays where single crystal high speed devices are required. The planar surfaces of the array of devices are coplanar when the array is fabricated on a planar substrate.

Abstract: An image sensor device includes a semiconductor substrate having a front side and a backside. A first dielectric layer is on the front side of the semiconductor substrate. A metal pad is in the first dielectric layer. A second dielectric layer is over the first dielectric layer and on the front side of the semiconductor substrate. An opening penetrates through the semiconductor substrate from the backside of the semiconductor substrate, wherein the opening includes a first portion extending to expose a portion of the metal pad and a second portion extending to expose a portion of the second dielectric layer. A metal layer is formed in the first portion and the second portion of the opening.

Abstract: Among other things, one or more image sensors and techniques for guiding light towards a photodiode are provided. An image sensor comprises a metal grid configured to direct light towards a corresponding photodiode and away from other photodiodes. The image sensor also comprises a dielectric grid and a filler grid over the metal grid to direct light towards the corresponding photodiode and away from other photodiodes, where the filler grid has a different refractive index than the dielectric grid. In this way, crosstalk, otherwise resulting from detection of light by incorrect photodiodes, is mitigated.

Abstract: A semiconductor wafer is subjected to a protection film formation step process as a process before evaluation of electrical characteristics. In this process, after an insulating film serving as a protection film is formed, a photolithography process and an etching process are performed so as to form a protection film having a plurality of openings exposing an emitter electrode. Then, electrical characteristics are evaluated by bringing a contact probe in contact with the exposed emitter electrode through each opening.

Abstract: Various embodiments provide LDMOS devices and fabrication methods. An N-type buried isolation region is provided in a P-type substrate. A P-type epitaxial layer including a first region and a second region is formed over the P-type substrate. The first region is positioned above the N-type buried isolation region, and the second region surrounds the first region. An annular groove is formed in the second region to surround the first region and to expose a surface of the N-type buried isolation region. Isolation layers are formed on both sidewalls of the annular groove. An annular conductive plug is formed in the annular groove between the isolation layers. The annular conductive plug is in contact with the N-type buried isolation region at the bottom of the annular conductive plug. A gate structure of an LDMOS transistor is formed over the first region of the P-type epitaxial layer.

Abstract: A semiconductor optical emitting device comprises an at least partially transparent substrate, an active semiconductor structure, a dielectric layer and a metal layer. The substrate comprises a first surface, a second surface and at least one sidewall. The active semiconductor structure comprises a first surface, a second surface and at least one sidewall, the first surface of the active semiconductor structure facing the second surface of the substrate. The dielectric layer surrounds at least a portion of the at least one sidewall of the active semiconductor structure. The metal layer surrounds at least a portion of the dielectric layer. The at least one sidewall of the active semiconductor structure is tapered and a first portion of the at least one sidewall of the active semiconductor structure has a different tapering than a second portion of the at least one sidewall of the active semiconductor structure.

Abstract: Staggered bond ads and I/O cells are arranged on an integrated circuit. The integrated circuit includes at least a first I/O cell having a first bond pad and first opposing set of recesses, a second I/O cell having a second bond sad and second opposing set of recesses, and a third I/O cell having a third bond sad and third opposing set of recesses. Each set of opposing recesses can be arranged in a staggered formation to receive adjacent bond pads, which can also be configured in a staggered formation.

Abstract: A semiconductor device includes a metal pad formed over a semiconductor substrate; a dummy metal pad spaced apart from the metal pad by an open region; and a Polymide Isoindro Quirazorindione (PIQ) layer formed to cover the open region and to define a pad open region by exposing a center part of the metal pad. The semiconductor device forms an additional open region at a region spaced apart from an edge part of the pad open region, preventing short-circuiting between the metal pad and the adjacent circuit line which might be caused by a crack generated at the edge of the pad open region when a probe is connected to the metal pad, and further preventing a defective semiconductor device from being generated.

Abstract: A chip package including a first substrate is provided. A plurality of first conductive pads is disposed on a first side of the first substrate. A second substrate is attached onto a second side opposite to the first side of the first substrate. The second substrate includes a micro-electric element and has a plurality of second conductive pads corresponding to the plurality of first conductive pads, disposed on a first side of the second substrate and between the first substrate and the second substrate. A redistribution layer is disposed on a second side opposite to the first side of the second substrate. The redistribution layer penetrates the second substrate, second conductive pads and the first substrate and extends into the first conductive pads to electrically connect the first and second conductive pads.

Abstract: Devices having features deposited on two sides of a device substrate and methods for making the same. The devices are useful, for example, as the components in a macroelectronic system. In a preferred embodiment, the devices are photosensors having a plurality of electrodes patterned on a first side of the device and an electromagnetic interference filter patterned on a second side of the device. The method facilitates the fabrication of two-sided devices through the use of an immobilizing layer deposited on top of devices patterned on a first side of a device substrate; flipping the device substrate; processing the second side of the device substrate to produce patterned features on the second side of the device substrate; and releasing the devices having patterned elements on two sides of each device.

Abstract: Bias-switchable dual-band infrared detectors and methods of manufacturing such detectors are provided. The infrared detectors are based on a back-to-back heterojunction diode design, where the detector structure consists of, sequentially, a top contact layer, a unipolar hole barrier layer, an absorber layer, a unipolar electron barrier, a second absorber, a second unipolar hole barrier, and a bottom contact layer. In addition, by substantially reducing the width of one of the absorber layers, a single-band infrared detector can also be formed.

Abstract: A device includes a semiconductor substrate having a front side and a backside, a photo-sensitive device disposed on the front side of the semiconductor substrate, and a first and a second grid line parallel to each other. The first and the second grid lines are on the backside of, and overlying, the semiconductor substrate. The device further includes an adhesion layer, a metal oxide layer over the adhesion layer, and a high-refractive index layer over the metal layer. The adhesion layer, the metal oxide layer, and the high-refractive index layer are substantially conformal, and extend on top surfaces and sidewalls of the first and the second grid lines.

Abstract: Techniques for using electrodeposition to form absorber layers in diodes (e.g., solar cells) are provided. In one aspect, a method for fabricating a diode is provided. The method includes the following steps. A substrate is provided. A backside electrode is formed on the substrate. One or more layers are electrodeposited on the backside electrode, wherein at least one of the layers comprises copper, at least one of the layers comprises zinc and at least one of the layers comprises tin. The layers are annealed in an environment containing a sulfur source to form a p-type CZTS absorber layer on the backside electrode. An n-type semiconductor layer is formed on the CZTS absorber layer. A transparent conductive layer is formed on the n-type semiconductor layer. A diode is also provided.

Abstract: An optical sensor element is mounted in a package which includes a glass substrate having a cavity, and a glass lid substrate bonded to the other substrate to close the cavity. The glass substrate with the cavity has metalized wiring patterns on front and rear surfaces thereof, and a through hole filled with metal to form a through-electrode interconnecting the wiring patterns on the front and rear surfaces. A metalized wiring pattern on the rear surface of the glass lid substrate is electrically connected to the wiring pattern on the front surface of the other substrate with an adhesive containing conductive particles. The glass lid substrate is made either of glass having a filter function or glass having a light shielding property with an opening therethrough filled with glass having a filter function.

Abstract: A micro-fabricated atomic clock structure is thermally insulated so that the atomic clock structure can operate with very little power in an environment where the external temperature can drop to ?40° C., while at the same time maintaining the temperature required for the proper operation of the VCSEL and the gas within the vapor cell.

Abstract: A semiconductor apparatus includes: a first sheet-like member having a light receiving surface of an imaging device and a first connection terminal disposed thereon, the imaging device generating an image by receiving incident light from a light collecting section for collecting external light disposed thereon; a second sheet-like member having a second connection terminal to be connected to the first connection terminal provided thereon; a conductive bonding portion made of a conductive material and bonded with the first connection terminal; and a bonding wire connecting the conductive bonding portion and the second connection terminal, wherein the bonding wire is disposed along the plane of the first sheet-like member such that reflected light from the bonding wire does not impinge on the light receiving surface.

Abstract: An image capturing apparatus includes a solid-state image sensor, a support member for the sensor, and electrically conductive members. The conductive members are electrically connected to the sensor, attached to support member, and arranged in a direction along one side of the sensor. The sensor is configured to receive a power supply voltage via a first conductive member, receive a ground voltage via a second conductive member, and transmit a signal via a third conductive member. The first and second conductive members are located on one side in the direction with respect to the third conductive member. The conductive members do not include a conductive member configured to supply a power supply voltage or a ground voltage to the sensor on the other side of the direction with respect to the third conductive member.

Abstract: A pressure sensor package includes a pressure sensor having a first side with a pressure sensor port, a second side opposite the first side, and electrical contacts. A logic die stacked on the pressure sensor has a first side attached to the second side of the pressure sensor and a second side opposite the first side with electrical contacts. The logic die is laterally offset from the electrical contacts of the pressure sensor and operable to process signals from the pressure sensor. Electrical conductors connect the electrical contacts of the pressure sensor to the electrical contacts of the logic die. Molding compound encapsulates the pressure sensor, the logic die and the electrical conductors, and has an opening defining an open passage to the pressure sensor port. External electrical contacts are provided at a side of the pressure sensor package.

Abstract: An integrated circuit structure includes a semiconductor substrate, and a dielectric pad extending from a bottom surface of the semiconductor substrate up into the semiconductor substrate. A low-k dielectric layer is disposed underlying the semiconductor substrate. A first non-low-k dielectric layer is underlying the low-k dielectric layer. A metal pad is underlying the first non-low-k dielectric layer. A second non-low-k dielectric layer is underlying the metal pad. An opening extends from a top surface of the semiconductor substrate down to penetrate through the semiconductor substrate, the dielectric pad, and the low-k dielectric layer, wherein the opening lands on a top surface of the metal pad. A passivation layer includes a portion on a sidewall of the opening, wherein a portion of the passivation layer at a bottom of the opening is removed.

Abstract: A semiconductor integrated circuit has one or more integral nitride-type sensors. In one embodiment, an integral nitride-type sensor and a coplanar supplemental circuit are formed from a common silicon substrate base. In another embodiment, an integral nitride-type sensor and a supplemental circuit are integrated in a vertical orientation.

Abstract: Provided is a semiconductor device that can suppress a leakage current more than has been achieved before. A semiconductor device 22 includes a first carrier holding layer 48, which is arranged on a lower electrode 47, is in contact with a lower electrode 47 via a first interface 49, and includes majority carriers of one type, and a second carrier holding layer 57, which is arranged on the first carrier holding layer 48, defines a second interface 58 constituting a conduction path to the first carrier holding layer 48, and includes majority carriers of the other type. The first interface 49 has its outline within the outline of the first carrier holding layer 48 when seen in a plan view in a direction that is orthogonal to a surface of the substrate, and the second interface 58 has its outline within the outline of the first carrier holding layer 48 when seen in the plan view.

Abstract: A semiconductor device includes a wiring layer that includes at least one low-dielectric rate interlayer insulating film layer; a guard ring that is formed by placing in series a wire and a via so as to be in contact with a through electrode, in a portion in which the through electrode passing through the wiring layer is formed; and the through electrode that is formed by being buried inside the guard ring.

Abstract: A device includes two BSI image sensor elements and a third element. The third element is bonded in between the two BSI image sensor elements using element level stacking methods. Each of the BSI image sensor elements includes a substrate and a metal stack disposed over a first side of the substrate. The substrate of the BSI image sensor element includes a photodiode region for accumulating an image charge in response to radiation incident upon a second side of the substrate. The third element also includes a substrate and a metal stack disposed over a first side of the substrate. The metal stacks of the two BSI image sensor elements and the third element are electrically coupled.

Abstract: A method for forming a pad in a wafer with a three-dimensional stacking structure is disclosed. The method includes bonding a device wafer that includes an Si substrate and a handling wafer, thinning a back side of the Si substrate, depositing an anti-reflective layer on the thinned back side of the Si substrate, depositing a back side dielectric layer on the anti-reflective layer, defining a space for a pad in the back side dielectric layer and forming vias that pass through the back side dielectric layer and the anti-reflective layer and contact back sides of super contacts which are formed on the Si substrate, filling one or more metals in the vias and the defined space for the pad, and removing a remnant amount of the metal filled in the space for the pad through planarization by a CMP (chemical mechanical polishing) process.

Abstract: An assembly that attaches a ball grid array (BGA) packaged camera device to a printed circuit board (PCB) substrate is provided. The assembly includes a spacer between the device and the substrate. The spacer is configured to prevent excessive collapse of solder balls located between the device and the substrate during reflow of the solder balls. The spacer includes one of solder mask, tape, and/or legend ink.

Abstract: A light receiving element includes: a semiconductor layer; an insulating layer; an interconnect layer; and a film. The semiconductor layer includes a light receiving unit configured to convert a signal light incident on the light receiving unit into an electrical signal. The insulating layer is provided on the semiconductor layer. The interconnect layer is provided on the insulating layer. The film is provided on the insulating layer to cover the light receiving unit and be connected to the interconnect layer, the film being made of a metal or a metal nitride.

Abstract: A light receiving element includes: a semiconductor layer; a first layer; and a second layer. The semiconductor layer has a first impurity concentration. The first layer of a first conductivity type is provided inward from an upper surface of the semiconductor layer. The first layer has a second impurity concentration higher than the first impurity concentration. The first layer has a surface region on an upper surface of the semiconductor layer side and an inner region being narrower than the first region. The second layer of a second conductivity type is provided inward from the upper surface of the first semiconductor layer. The second layer has a third impurity concentration higher than the first impurity concentration.

Abstract: A semiconductor device has first wiring layers and a plurality of dummy wiring layers that are provided on the same level as the first wiring layers. The semiconductor device defines a row direction, and first virtual linear lines extending in a direction traversing the row direction. The row direction and the first virtual linear lines define an angle of 2-40 degrees, and the dummy wiring layers are disposed in a manner to be located on the first virtual linear lines. The semiconductor device also defines a column direction perpendicular to the row direction, and second virtual linear lines extending in a direction traversing the column direction. The column direction and the second virtual linear lines define an angle of 2-40 degrees, and the dummy wiring layers are disposed in a manner to be located on the second virtual linear lines.

Abstract: A method for bonding an LED assembly 71 or other electronic package 31 to a substrate PCB containing a heat-sink 52, which utilizes layers of reactive multilayer foil 51 disposed between contacts 32, 34 of the electronic package 31 and the associated contact pads 55 on the supporting substrate PCB. By initiating an exothermic reaction in the reactive multilayer foil 51, together with an application of pressure, sufficient heat is generated between the contacts 32, 34 and the associated contact pads 55 to melt adjacent bonding material 54 to obtain good electrically and thermally conductive bonds between the contacts 32, 34 and contact pads 55 without thermally damaging the electronic package 31, heat-sensitive components 35 associated with the electronic package 31, or other the supporting substrate PCB.